JP2002026659A - Oscillation start unit and oscillation start method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a conventional oscillation start unit that has had required a long time until oscillation is stabilized after a CPU 4 outputs a control signal CM (oscillation start command) at an H level. SOLUTION: When the oscillation start command is outputted to an oscillation circuit 11, a voltage signal VCPU that is a sine wave equivalent to the oscillation signal of the oscillation circuit 11 is supplied to the oscillation circuit 11 for a period of 1.25 cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an oscillation starting device and an oscillation starting method for starting an oscillation circuit.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a conventional oscillation starter. In FIG. 9, reference numeral 1 denotes an oscillation circuit of, for example, 32 kHz, 2 denotes a 32 kHz oscillator of the oscillation circuit 1, 3 denotes a resistor of the oscillation circuit 1, Reference numeral 4 denotes a CPU that switches the signal level of the control signal CM from L level to H level when starting the oscillation circuit 1, and 5 denotes a NAND circuit.

Next, the operation will be described. In a state where the oscillation circuit 1 is stopped, the CPU 4 outputs the control signal CM at L level, so that the signal level of the output terminal of the NAND circuit 5 (XC _OUT terminal of the oscillation circuit 1) becomes H level, Becomes _Vcc (see FIG. 10). The XC _IN terminal of the oscillation circuit 1 is connected to the XC _IN
Since it is short-circuited with the _OUT terminal, the signal level of the XC _IN terminal also becomes H level.

In this state, the CPU 4 controls the oscillation circuit 1
When the control signal CM (oscillation start command) at the H level is output in order to start the operation, the logic of the output level of the NAND circuit 5 is theoretically inverted to the L level, but as described above, XC _IN since the terminal and _{XC O UT} terminals are short-circuited via a resistor 3, the output level of the NAND circuit 5 logic does not immediately reversed, as shown in FIG. _{10, XC OUT}
The terminal voltage gradually decreases.

The oscillator 2 of the oscillation circuit 1 cannot start oscillating until the voltage value of the XC _OUT terminal drops from V _cc to 、 V _cc , but starts oscillating when the voltage drops to Ｖ V _cc. Then, an oscillation signal having a frequency of 32 KHz is output. However, even if the oscillation starts, as shown in FIG. 10, the oscillation is not stabilized for a while, and in the case of the 32 kHz oscillation circuit, the resistance value of the resistor 3 is relatively large.
It takes about one second from when the PU 4 outputs the H-level control signal CM to when the oscillation stabilizes.

[0006]

Since the conventional oscillation starter is configured as described above, it takes a period of time from when the CPU 4 outputs the H-level control signal CM (oscillation start command) to when the oscillation is stabilized. There was a problem that required a long time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an oscillation starting device and an oscillation starting device capable of shortening the time required from the output of an oscillation start command to the stabilization of oscillation. The aim is to get a start-up method.

[0008]

An oscillation starter according to the present invention supplies a drive signal generated by a drive signal generation means to an oscillation circuit for a predetermined period when an oscillation start instruction is output from a start instruction means. It is provided with signal supply means.

In the oscillation starting device according to the present invention, the drive signal supply means supplies the drive signal to the oscillation circuit for a period of 1.25 cycles.

[0010] In the oscillation starting device according to the present invention, the drive signal generating means generates a sine wave drive signal.

In the oscillation starting method according to the present invention, when an oscillation start command is output to the oscillation circuit, a drive signal having a waveform corresponding to the oscillation signal of the oscillation circuit is supplied to the oscillation circuit for a predetermined period. .

The oscillation starting method according to the present invention has
The drive signal is supplied to the oscillation circuit during the cycle.

The oscillation starting method according to the present invention generates a sine wave drive signal.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing an oscillation starter according to Embodiment 1 of the present invention. In the figure, 11 is an oscillation circuit, 12 is an oscillator of the oscillation circuit 11, 13 is a resistor of the oscillation circuit 11, and 14 is a control signal. A CPU that outputs the CM to the NAND circuit 15 and controls the D / A converter 17 and the transmission gate 18, 15 is a NAND circuit, 16 is a process of writing a digital value to an input register of the D / A converter 17, Transmission gate 1
A ROM in which a program for the CPU 14 to execute the control processing of 8 is stored; 17 a digital-to-analog conversion of a digital value output from the CPU 14 to output a voltage signal V _CPU (drive signal) as an analog value A D / A converter 18 is a transmission gate for connecting the D / A converter 17 to the oscillation circuit 11 under the instruction of the CPU 14.

The CPU 14 and the NAND circuit 15 constitute start command means, and the CPU 14, ROM 16 and D / A converter 17 constitute drive signal generation means.
Drive signal supply means is constituted by the CPU 14 and the transmission gate 18. Figure 2 is a timing chart illustrating waveforms of various signals, FIG. 3 is an explanatory view showing the correspondence between the digital value and the voltage signal V _CPU is the input value of the D / A converter 17, the embodiment of FIG. 4 is the invention 3 is a flowchart illustrating an oscillation start method according to the first embodiment. In the embodiment described below, it is assumed that a 1.25 cycle 32 kHz sin waveform is output 39 times at 1 μS intervals.

Next, the operation will be described. Oscillation circuit 11
Is stopped, the CPU 14 outputs the L-level control signal CM, so that the signal level of the output terminal of the NAND circuit 15 (XC _OUT terminal of the oscillation circuit 11) becomes H level.

In this state, the CPU 14 outputs an H-level control signal CM (oscillation start command) to activate the oscillation circuit 11 (step ST1). At this time, C
The PU 14 connects the D / A converter 17 to the oscillation circuit 11 and the NA
In order to connect to the ND circuit 15, the signal level of the gate control signal PD is switched from L level to H level (step ST2). Thereby, the transmission gate 1
8 becomes conductive, and the D / A converter 17 becomes the oscillation circuit 11
And the NAND circuit 15.

From the beginning of outputting the oscillation start command, the CPU 14 provides a sine-wave voltage signal V _CPU (to the XC _IN terminal of the oscillation circuit 11 and the NAND circuit 15 in order to stabilize the oscillation signal from the oscillator 12. Oscillator 12
(A signal corresponding to the oscillation signal after the stabilization by the above).
That is, when the CPU 14 executes the program stored in the ROM 16, the digital value of FIG. 3 is written into the input register of the D / A converter 17 39 times every 1 μS, and the D / A converter 17 Amplitude is 0.0V ~
A voltage signal V _{CPU of} 5.0 V is output (step S
T3, ST4). As a result, as shown in FIG.
5 cycles of the voltage signal _{V CPU} is supplied.

[0019] CPU14 has completed the supply of the voltage signal _{V CPU} of 1.25 cycles, thereafter, even by stopping the supply of the voltage signal _{V CPU,} the oscillator 12 outputs a stable oscillation signal The gate control signal P
The signal level of D is switched from H level to L level (step ST5), and the D / A converter 17 is switched to the oscillation circuit 11
Try to separate from

As is clear from the above, the first embodiment
According to, when outputting the oscillation start command to the oscillation circuit 11, to constitute a voltage signal V _CPU of sin waves corresponding to the oscillation signal of the oscillation circuit 11 to time the supply of 1.25 cycle oscillation circuit 11 Therefore, there is an effect that the time required from the output of the oscillation start command to the stabilization of the oscillation of the oscillator 12 can be reduced.

Embodiment 2 FIG. FIG. 5 is a block diagram showing an oscillation starter according to Embodiment 2 of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and a description thereof will be omitted. Reference numeral 21 denotes a control signal CM for the NAND circuit 15
And a CPU for outputting to the switch switching circuit 26,
A frequency divider that divides the operation clock φ of the PU 21 and outputs a clock φM having a period of 1 μS. The frequency divider 23 increments the count value in synchronization with the rising edge of the clock φM output from the frequency divider 22. Count value is 16
When the number reaches "26" in base, the overflow signal C
_{This is} a counter for switching the signal level of _ovf from L level to H level.

Reference numeral 24 denotes the count value of the counter 23 and D / A
A memory for storing a correspondence relationship with an input value (digital value) of the converter 25 and outputting a digital value corresponding to the count value. A memory 25 performs digital / analog conversion of the digital value output from the memory 24 and performs analog / digital conversion. A D / A converter that outputs a voltage signal V _DA (drive signal),
26 receives the H-level control signal CM from the CPU 21, sets the control signal S to the H-level, connects the D / A converter 25 to the oscillation circuit 11, and receives the H-level overflow signal _Covf from the counter 23. , Control signal S
At the L level to disconnect the D / A converter 25 from the oscillation circuit 11.

The CPU 21 and the NAND circuit 15 constitute a start command means, and the frequency divider 22, the counter 2
3, a memory 24 and a D / A converter 25 constitute drive signal generation means, and the frequency divider 22, counter 23, switch switching circuit 26 and transmission gate 18 constitute drive signal supply means. FIG. 6 is a configuration diagram showing the internal configuration of the switch switching circuit 26, FIG. 7 is a timing chart showing waveforms of various signals, and FIG.
FIG. 5 is an explanatory diagram showing a correspondence relationship between a count value input to the digital camera and a digital value output therefrom.

Next, the operation will be described. Oscillation circuit 11
Is stopped, the signal level of the output terminal of the NAND circuit 15 (XC _OUT terminal of the oscillation circuit 11) becomes H level because the CPU 21 outputs the control signal CM of L level.

In this state, the CPU 21 outputs an H-level control signal CM (oscillation start command) to activate the oscillation circuit 11. The switch switching circuit 26 has a CP
When the control signal CM of the H level is received from U21, the control signal S of the H level is output to start the counting process of the counter 23 and to make the transmission gate 18 conductive so that the D / A converter 25 oscillates. The circuit 11 is connected.

Upon receiving the H-level control signal S, the counter 23 increments the count value in synchronization with the rising edge of the clock φM output from the frequency divider 22, and outputs the count value to the memory 24. Memory 2
4 receives the count value from the counter 23 and outputs a digital value corresponding to the count value according to the correspondence table of FIG.

The D / A converter 25 converts the digital value output from the memory 24 from digital to analog,
It outputs a voltage signal V _DA (drive signal) that is an analog value. Note that the count value of the counter 23 is “2” in hexadecimal.
It is incremented until the 6 ", since the digital value output from the memory 24 is updated 39 times, as shown in FIG. 7, the waveform of the voltage signal V _DA is sin wave of 1.25 cycles.

As a result, from the beginning when the CPU 21 outputs the control signal CM (oscillation start command) at the H level, the XC _IN terminal of the oscillation circuit 11 and the NAND circuit 15
Since the in-wave voltage signal V _DA (a signal corresponding to the oscillation signal stabilized by the oscillator 12) is supplied, the oscillator 12
The oscillation signal due to is quickly stabilized.

The counter 23 has a count value in hexadecimal.
When “26” is reached, as shown in FIG.
Low signal C_ovfSignal level from L level to H level
Switch to. The switch switching circuit 26 includes a counter 23
To H level overflow signal C _ovfReceive
And the control signal S is set to the L level to issue the D / A converter 25.
To be separated from the oscillation circuit 11.

As is apparent from the above, according to the second embodiment, when the CPU 21 outputs the oscillation start command,
Since a voltage signal V _{D A} of sin waves corresponding to the oscillation signal of the oscillation circuit 11 is configured to time the supply of the oscillation circuit 11 to 1.25 cycles, the output of the oscillation start command,
There is an effect that the time required until the oscillation of the oscillator 12 is stabilized can be shortened.

[0031]

As described above, according to the present invention, when the oscillation start command is output from the start command means, the drive signal generated by the drive signal generation means is supplied to the oscillation circuit for a predetermined period. Since the means is provided, there is an effect that the time required from when the oscillation start command is output to when the oscillation is stabilized can be shortened.

According to the present invention, since the drive signal supply means supplies the drive signal to the oscillation circuit for a period of 1.25 cycles, the oscillation of the oscillation circuit can be reliably stabilized. .

According to the present invention, the drive signal generating means is s
Since the configuration is such that the in-wave drive signal is generated, there is an effect that the oscillation of the oscillation circuit can be reliably stabilized.

According to the present invention, when the oscillation start command is output to the oscillation circuit, a drive signal having a waveform corresponding to the oscillation signal of the oscillation circuit is supplied to the oscillation circuit for a predetermined period. This has the effect of shortening the time required until oscillation stabilizes after the signal is output.

According to the present invention, since the drive signal is supplied to the oscillation circuit for a period of 1.25 cycles, the oscillation of the oscillation circuit can be reliably stabilized.

According to the present invention, since the sine wave drive signal is generated, the oscillation of the oscillation circuit can be reliably stabilized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an oscillation starting device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing waveforms of various signals.

3 is an explanatory diagram showing the correspondence between the digital value and the voltage signal V _{CP U} is the input value of the D / A converter 17.

FIG. 4 is a flowchart showing an oscillation starting method according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram showing an oscillation starting device according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram showing an internal configuration of a switch switching circuit 26;

FIG. 7 is a timing chart showing waveforms of various signals.

FIG. 8 is an explanatory diagram showing a correspondence relationship between a count value input to a memory 24 and a digital value output.

FIG. 9 is a configuration diagram showing a conventional oscillation starting device.

FIG. 10 is a waveform chart showing a voltage waveform of an XC _OUT terminal.

[Explanation of symbols]

11 oscillation circuit, 12 oscillator, 13 resistor, 14 C
PU (start command means, drive signal generation means, drive signal supply means), 15 NAND circuit (start command means), 16
ROM (drive signal generation means), 17 D / A converter (drive signal generation means), 18 transmission gate (drive signal supply means), 21 CPU (start command means), 22 frequency divider (drive signal generation means, drive Signal supply means), 23 counters (drive signal generation means, drive signal supply means), 24 memories (drive signal generation means), 25
D / A converter (drive signal generation means), 26 switch switching circuit (drive signal supply means).

Continuation of the front page (72) Inventor Shinichi Suzuki 3-1-1-17 Chuo, Itami-shi, Hyogo Mitsubishi Electric System LSI Design Co., Ltd. F term (reference) 5J079 AA03 BA22 EA02 EA11 EA20 FA14 FA21 FB31 FB38 FB39 FB40 FB48 GA04 GA11

Claims (6)

[Claims] 1. A start command means for outputting an oscillation start command to an oscillation circuit, a drive signal generation means for generating a drive signal having a waveform corresponding to an oscillation signal of the oscillation circuit, and an oscillation start command from the start command means An oscillation starter comprising: a drive signal supply unit that supplies a drive signal generated by the drive signal generation unit to the oscillation circuit for a predetermined period when a command is output. 2. The oscillation starting device according to claim 1, wherein the driving signal supply means supplies the driving signal to the oscillation circuit for a period of 1.25 cycles. 3. The driving signal generating means according to claim 1, wherein the driving signal generating means generates a driving signal of a sine wave.
The oscillation starter according to the above. 4. An oscillation starting method, comprising: when an oscillation start command is output to an oscillation circuit, generating a drive signal having a waveform corresponding to the oscillation signal of the oscillation circuit, and supplying the drive signal to the oscillation circuit for a predetermined period. 5. The oscillation starting method according to claim 4, wherein the driving signal is supplied to the oscillation circuit for a period of 1.25 cycles. 6. The oscillation starting method according to claim 4, wherein a driving signal of a sine wave is generated.