JP2002026307A - Manufacturing method for power semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a power semiconductor of low on-voltage by a method with less wafer damage trouble in production, although a wafer is thick for a conventional power semiconductor element, resulting in high on-voltage with large power loss. SOLUTION: In order to raise eventual yield of a semiconductor wafer, a wafer thicker than a completed chip is used as a ribbed wafer where only a chip effective part is made thinner in a thickness machining process, and then conventional diffusion process, dicing and the like are performed for less wafer damage trouble during process, resulting in thinner chip effective part after completion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a power semiconductor device, and more particularly to a method for processing a wafer thickness.

[0002]

2. Description of the Related Art A conventional power semiconductor device manufacturing process is described as follows.
A thyristor will be described as an example. FIG. 4 is a sectional view of a thyristor manufacturing process. P from both sides of N-type semiconductor wafer 1
After the mold separation / diffusion regions 2 are formed in a lattice shape, gallium is diffused to form P-type layers 4 and 5 as shown in FIG. By selectively diffusing phosphorus into a part of the P-type layer 4, an N-type layer 6 is formed as shown in FIG.
An NPN four-layer structure is formed, and electrodes are provided on the respective exposed portions to complete the thyristor. As shown in FIG. 4, dicing is performed at a cutting line 7 corresponding to a substantially center line of the band width of the separation diffusion region 2.
As shown in (c), a plurality of power semiconductor chips were completed.

[0003]

When the chip size of the power semiconductor device formed as described above is 1 cm square,
The on-state voltage is about 1.5 V at a current of 100 A, and attempts have been made to reduce the on-state voltage to reduce the power loss that occurs in this portion. One of them is achieved by reducing the thickness of the wafer.
For example, when a wafer having a thickness of 400 microns is used, the ON voltage is 1.52 V, and when a wafer having a thickness of 360 microns is used, the ON voltage is 1.28 V. That is, the on-voltage can be reduced by making the wafer thinner. However, when the thickness of the wafer is reduced, the trouble that the breakdown voltage is reduced or the wafer is damaged during the process increases. It is an object of the present invention to reduce the trouble of wafer breakage in the manufacturing process and to produce a power semiconductor device having a low on-voltage without a decrease in withstand voltage.

[0004]

In a method of manufacturing a semiconductor chip according to the present invention, a wafer having a thickness larger than that of a completed chip is used, and a separation diffusion region which is a portion having a cutting line when each chip is cut. , A ribbed wafer is formed by partial thickness processing to cut one or both surfaces of each chip effective portion. After the formation of the ribbed wafer, each semiconductor layer is formed by processing steps such as diffusion and etching. A plurality of semiconductor chips are formed by dicing substantially the center of the rib width of the separation diffusion region.

[0005] As the size of a wafer increases, a thin wafer often causes breakage troubles during the process. Conventionally, a thyristor element having a high ON voltage of about 1.5 V has been produced by using a wafer having a thickness of 400 microns instead of a wafer having a thickness of, for example, 360 microns. In the present invention, for example, a wafer having a thickness of 400 microns is partially processed into a thickness of 400 μm in a grid pattern over the entire surface.
Since a wafer having a thickness of 360 microns having ribs of microns is to be processed in each step, the thickness of the wafer having no ribs of 3 microns is required.
In comparison with the case of using a 60-micron wafer, wafer damage in each step is drastically reduced. The completed chip cut at the ribs is a 360-micron chip with a 400-micron frame formed around its periphery, and the chip effective part is a conventional 400-micron thick chip. It is 360 microns thinner than the chip and functions as a thyristor with a lower value than the conventional on-voltage.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is shown in FIG. 1 as a process sectional view and FIG. 2 as a plan view. 1A is an N-type semiconductor wafer having a thickness of 400 microns. As shown in FIG. 2, for example, a P-type separation / diffusion is performed on a lattice-shaped region on a wafer having a diameter of 5 inches. As shown in FIG. 1 (a), the N-type semiconductor wafer subjected to the separation / diffusion is subjected to a step of removing the entire surface except for the separation / diffusion region 2 to a thickness of 360 μm by etching or the like. , FIG.
A wafer having the separation / diffusion region 2 as shown in FIG. Gallium is diffused into the chip effective surface 3 which is a newly formed surface which has been scraped off to form P-type semiconductor layers 4 and 5. When phosphorus is diffused into a part of the P-type layer 4, an N-type layer 6 is formed as shown in FIG.

[0007] Dicing along the cutting line 7
As shown in FIG. 3D and FIG. 3, for example, a 1 cm square semiconductor chip is formed. Electrodes were provided on the exposed portions of each semiconductor layer to obtain the function of a thyristor, and the characteristics of an ON voltage of 1.28 V were obtained when the chip size was 1 cm square and the ON current was 100 A. Since the on-state voltage was 0.24 V lower than that of a thyristor formed using a 400-μm-thick wafer without a grid-like rib by a conventional method, it was 24 W at 100 A. Is saved per element. Although the above description has been made by taking a thyristor as an example, a power semiconductor element such as a diode can be similarly realized based on this technical idea.

[0008]

According to the present invention, a power semiconductor device having a low on-state voltage and a small power loss as described above can be realized with less trouble of wafer breakage in industrial production, and heat generation due to power loss of the device. The amount is small, and the radiator can be downsized. This contributes to environmental preservation by reducing the material of the whole semiconductor device application product and the energy consumption during operation, and has great industrial value.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a thyristor manufacturing process showing an embodiment according to the present invention.

FIG. 2 is a plan view of a thyristor manufacturing process showing an embodiment according to the present invention.

FIG. 3 is an external perspective view of a thyristor chip showing an embodiment according to the present invention.

FIG. 4 is a cross-sectional view of a known thyristor manufacturing process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N-type semiconductor wafer 2 Separation diffusion area 3 Chip effective part (cutting surface) 4 P-type diffusion layer 5 P-type diffusion layer 6 N-type diffusion layer 7 Cutting line

Claims (1)

[Claims] Claims: 1. Through a process such as diffusion and etching,
In a method for manufacturing a power semiconductor device in which each semiconductor layer is formed on a wafer and cut into a plurality of chips, the surface of the wafer may be formed on one or both surfaces while leaving a separate diffusion region for each chip effective portion. A wafer with ribs is formed by partial thickness processing, and a wafer with ribs is formed. After each wafer is formed, each semiconductor layer is formed by the above-described processing steps. Forming a plurality of chips by dicing the semiconductor device.