JP2002026136A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the junction capacity of an input element formed on a substrate by using a substrate with high specific resistance by decreasing the impurity density of the semiconductor substrate and a semiconductor integrated circuit device, and then to surely output a fine signal by reducing the outflow of an input signal of the input element. SOLUTION: This semiconductor integrated circuit device uses a P- type high specific resistance semiconductor substrate 33 as a semiconductor substrate for an NPN transistor 31 and a junction-type FET 32. Consequently, a depletion layer is formed large in size on the substrate 33 with a reverse-bias voltage, and the junction capacity of the input element is decreased. Then the outflow of the input signal of the input element is reduced, to obtain a semiconductor integrated circuit device which surely outputs the fine signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a junction type FET or ED-MOS transistor as an input element and reduces the impurity concentration of a semiconductor substrate to increase the specific resistance, thereby reducing the junction capacitance of the input element. And a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A condenser microphone (ECM) is
It is an element for converting air vibration such as voice into an electric signal of change in capacitance value. The output signal is extremely weak, and an element for amplifying the output signal is required to have characteristics such as high input impedance and low noise.

As an input element suitable for such a demand, a junction type FET or an ED-MOS transistor is used. Among them, the junction type FET device has features such as easy integration into a BIP type IC. (For example, JP-A-58-197885).

FIG. 8 is a sectional view of a semiconductor integrated circuit device which is formed monolithically with the NPN transistor 1 by using the junction FET 2 as an input element. In this semiconductor integrated circuit device, an N ⁻ type epitaxial layer 4 is stacked on a P type semiconductor substrate 3. And
This epitaxial layer 4 is firstly formed by a P ⁺ type isolation region 5.
Are separated into an island region 6 and a second island region 7. The NPN transistor 1 is formed in the first island region 6 and the junction FET 2 is formed in the second island region 7 in a monolithic manner. The P ⁺ -type isolation region 5 is composed of a P ⁺ -type isolation region 8 that diffuses vertically from the surface of the P-type semiconductor substrate 3 and a P ⁺ type diffusion region that diffuses from the surface of the epitaxial layer 4.
^{The +} type separation region 9 is formed by connecting two members.

[0005] In the NPN transistor 1, a P-type semiconductor substrate 3 and an epitaxial layer 4 laminated on the substrate 3 are formed.
An N ⁺ -type buried layer 10 is formed between these layers, and the epitaxial layer 4 is used as a collector region. The N ⁺ type diffusion regions 13, 1
4 and P-type diffusion regions 15 are formed. The N ⁺ type diffusion region 13 serves as a collector leading region, and the N ⁺ type diffusion region 1
The NPN transistor 1 is formed by 4 serving as an emitter region and the P-type diffusion region 15 serving as a base region.

In the junction type FET 2, a P-type semiconductor substrate 3
The N ⁺ -type buried layer 11 and P ⁺ -type buried layer 12 is formed between the epitaxial layer 4 laminated thereon the substrate 3, P ⁺ -type buried layer 12 is formed by diffusion from the surface of the epitaxial layer 4 Connected to the P ⁺ well region 23. Then, an N-type channel region 16 and a P-type channel region 17 are formed on the surface of the P ⁺ well region 23 and form a channel with them. On the surface of the P ⁺ well region 12, P type diffusion regions 18 and 22 and N ⁺ type diffusion regions 19, 20, and 21 are formed, and these regions are electrically connected.

[0007]

In a conventional semiconductor integrated circuit device, an impurity is added to a semiconductor substrate so that the resistance of the semiconductor substrate becomes 2 to 4 Ω · cm. Then, on a semiconductor substrate having a small specific resistance, a junction type FET is used as an input element.
Alternatively, an ED-MOS transistor has been formed.

When the above-mentioned junction type FET or the like is used as an input element, a capacitance C1 formed by an extension electrode and an epitaxial layer with an insulating film interposed therebetween, and a PN junction capacitance C2 formed by an epitaxial layer and a semiconductor substrate. Occurs parasitically. When these are connected to the substrate-grounded ground potential GND, the junction capacitance C2 becomes 4.0.
It showed a large value of 0 to 8.00 × 10 ⁻⁵ pF / μm ² .

For this reason, in the conventional semiconductor integrated circuit device, the junction capacitance of these elements becomes large.
The input signal leaked to the ground potential GND via the capacitors C1 and C2, the level of the input signal was lowered, and a desired output signal could not be obtained. In particular, since an input element having a high input impedance is used in this semiconductor integrated circuit device, a minute input signal is further reduced and the signal is amplified, so that the S / N (signal-to-noise ratio) deteriorates. A challenge has arisen.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and a semiconductor integrated circuit device according to the present invention has a semiconductor substrate resistance of 1000 Ω · cm or more. Impurities added to the substrate have been reduced. The junction capacitance of the input element formed on the semiconductor substrate is 4.00 to 8.00 × 10 ⁻⁶ pF / μm.
^It has a structure of ² .

As a result, the PN junction capacitance formed between the epitaxial layer and the semiconductor substrate decreases. By that,
An outflow of an input signal in the semiconductor integrated circuit device can be prevented, and a semiconductor integrated circuit device capable of reliably outputting a small signal can be obtained.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an NPN transistor 31 and a junction type.
It is sectional drawing of IC which incorporated FET32. P^-
N-type single crystal silicon substrate 33 is vapor-deposited by N
Is N ^-7-9 μm thick epitaxial layer 3 laminated by
4 are formed. And, the epitaxial layer 34
Penetrating completely through the person⁺NPN by the mold separation region 35
A first island region 36 forming the transistor 31 and a junction
To the second island region 37 forming the type FET 32
Separated. The separation region 35 is located above the surface of the substrate 33.
Downwardly diffused first isolation region 38 and epitaxy
From the second isolation region 39 formed from the surface of the
The epitaxial layer 34 is connected to the island
Separate into pieces.

The specific resistance of the substrate 3 (see FIG. 8) of the conventional semiconductor integrated circuit device is about 2 to 4 Ω · cm, whereas the specific resistance of the semiconductor integrated circuit device of the present invention is 1000 Ω · cm. A substrate 33 having a high specific resistance of not less than cm is used.

[0015] NPN transistor 31, N on the substrate 33 of high resistivity as described above ^- are stacked epitaxial layer 34. An N ⁺ -type buried layer 41 is formed between the substrate and the epitaxial layer 34 laminated on the substrate 33, and the epitaxial layer 34 is used as a collector region. Then, N ⁺ type diffusion regions 44 and 45 and a P type diffusion region 46 are formed in the epitaxial layer 34. The N ⁺ type diffusion region 44 becomes a collector leading region,
N ⁺ type diffusion region 45 becomes an emitter region, and P type diffusion region 46 becomes a base region.

Here, although not shown in the figure, when other peripheral circuits are integrated and monolithically formed, an electrode wiring of Al on the silicon oxide film 55, an interlayer insulating film of a polyimide based insulating film, A polyimide-based jacket coat or the like is formed.

However, when the NPN transistor 31 is formed on the substrate 33 having a high specific resistance as in the present invention, the N
Leakage current from the PN transistor 31 flows to GND grounded to the substrate 33. As a result, the potential of GND rises, so that the reverse bias state is eliminated, and a current flows through the portion where the PN junction has occurred, thereby causing a malfunction of the circuit.

As a countermeasure, according to the present invention, in the first island region 36 where the NPN transistor 31 is formed, boron (B) is ion-implanted from the surface of the substrate 33 in advance to form the P ⁻ type buried layer 40. I have. As a result, the P ⁻ type buried layer 40 plays the role of the conventional substrate 3, so that the NPN transistor 31
In this case, it is possible to achieve the prevention of a leak current, the junction separation between circuit elements, and the like.

Next, in the junction type FET 32, similarly to the NPN transistor 31, the N ⁻ type epitaxial layer 3 is formed on the high specific resistance P ⁻ type single crystal silicon substrate 33.
4 are stacked. Then, an N ⁺ -type buried layer 42 and a P ⁺ -type buried layer 43 are formed between the substrate 33 and the epitaxial layer 34 laminated on the substrate 33, and the P ⁺ -type buried layer 43 is separated from the surface of the epitaxial layer 34. It is connected to the P ⁺ well region 47 formed by diffusion. Wherein the concentration of N ⁺ -type buried layer 42, P ⁺ -type buried layer 4
Since the concentration is higher than 3, the region where the two are connected becomes an N ⁺ type buried layer. And the P ⁺ well region 4
On the surface of 7, an N-type channel region 48 and a P ⁺ -type top gate region 49 are formed, and they form a channel. The N ⁺ type diffusion regions 51 and 53 serve as drain electrodes, and the N ⁺ type diffusion region 52 serves as a source electrode.

In the present invention, the junction capacitance of the junction FET 32 can be reduced by using the substrate 33 having a high specific resistance as described above. In the junction FET 32, a PN junction capacitance between the substrate 33 and the N ⁺ -type buried layer 42 is generated by applying a reverse bias voltage. In particular, P
^―― type substrate 33 and N ⁻ type first epitaxial layer 34
In the region where is in contact, a larger PN junction capacitance is generated. However, since this junction capacitance is formed via the P ⁻ -type single-crystal silicon substrate 33, when a reverse bias voltage is applied to the PN junction, the depletion layer is greatly expanded and the junction capacitance is reduced. Specifically, the specific resistance of the substrate is changed from the conventional 2 to 4 Ω · cm to 1000 Ω · c of the present invention.
m or more, the junction capacitance can be reduced to the conventional value of 4.0.
0 to 8.00 × 10 ⁻⁵ pF / μm ² to 4.0 of the present invention.
0 to 8.00 × 10 ⁻⁶ pF / μm ² .

As a result, in the semiconductor integrated circuit device of the present invention in which a junction FET and an ED-MOS transistor having a large input impedance are used as input elements, these input signals are input as small signals with high impedance. However, by using the substrate 33 having a high specific resistance, the junction capacitance of the input element is reduced. As a result, the input signal is supplied to the ground potential GND through these junction capacitors.
It is possible to obtain a semiconductor integrated circuit device that can be prevented from flowing out into the semiconductor integrated circuit and can output a small signal without fail.

As shown in FIG. 2, an NPN transistor 61 may be formed in the first island region 36, and an ED-MOS transistor 62 may be formed in the second island region as an input element.

The NPN transistor 61 is formed as described above. Then, the substrate 65 and the epitaxial layer 6
6 by the P ⁻ type buried layer 77 formed between
Prevention of leakage current in the PN transistor 61, junction separation between circuit elements, and the like can be achieved.

[0024] ED-MOS transistor ^{62, P -}
Layer 9 having a thickness of 7 to 9 μm laminated on a single-crystal silicon substrate 65 of N type by N or N ⁻ by vapor phase epitaxy.
6 are formed. The substrate 65 and the epitaxial layer 66
N ⁺⁺ type buried layers 67 and 68 are formed between the layers. Then, on the surface of the epitaxial layer 66, P ⁺ type diffusion regions 69, 70, and 7 serving as source or drain regions are provided.
2, 73 and a P ^- type channel region 71 are formed,
Gate electrodes 74 and 75 are formed thereon. Thus, the depletion type MOS transistor 63 and the enhancement type transistor 6
4 are formed. And this depletion type MOS
Transistor 63 and enhancement transistor 6
4, a LOCOS oxide film 76 is formed. The LOCOS oxide film 76 also serves as a channel stopper by being formed of a thick oxide film in addition to separating these two elements. Depletion type MO
The S transistor 63 is turned on when the gate voltage is 0 V,
It turns off when voltage is applied to the gate. On the other hand, the enhancement type MOS transistor 64 operates in the opposite manner. Even when the ED-MOS transistor 62 is used as the input element, similarly to the case where the junction FET is formed as the input element, the substrate 65 having a high specific resistance is used.
Is used, the junction capacitance of the input element is reduced. As a result, it is possible to prevent the input signal from flowing out to the ground potential GND via these junction capacitors, and it is possible to obtain a semiconductor integrated circuit device capable of reliably outputting a small signal.

Next, a method of manufacturing the semiconductor integrated circuit device of the present invention shown in FIG. 1 will be described with reference to FIGS.

First, as shown in FIG.
P ^- type single crystal silicon substrate 3 of 0 Ω · cm or more
Prepare 3 This substrate 33 has a P ⁻ -type buried layer 4 in which boron (B) is ion-implanted into a part of the substrate in advance.
0 is formed.

Next, as shown in FIG. 4, the surface of the substrate 33 is thermally oxidized to form an oxide film, and the oxide film is photo-etched to form respective selective masks. Then, boron (B) forming the first isolation region 38 of the isolation region 35 and the P ⁺ type buried layer 43 and phosphorus (P) or antimony (Sb) forming the N ⁺ type buried layers 41 and 42 on the surface of the substrate 33 are formed. Spread).

Next, as shown in FIG. 5, after removing all the oxide film used as the selection mask, the substrate 33 is placed on a susceptor of an epitaxial growth apparatus, and a high temperature of about 1180 ° C. is applied to the substrate 33 by lamp heating. By applying SiH ₂ Cl ₂ gas and H ₂ gas into the reaction tube, the N or N ⁻ epitaxial layer 34 is formed to a thickness of 7 to 9 μm.
m. At this time, at the same time, the first separation region 3
8, N ⁺ type buried layers 41 and 42, P ⁻ type buried layer 40
And the P ⁺ type buried layer 43 is diffused.

Next, as shown in FIG. 6, the surface of the epitaxial layer 34 is thermally oxidized to form a selection mask. This heat treatment also slightly diffuses the first isolation region 38. Next, the selection mask is changed, and boron (B) forming the second isolation region 39 of the isolation region 35 and the P-type diffusion regions 46 and 47 are diffused. Then, a heat treatment is applied to the entire substrate 33 while applying an oxide film, and the first and second isolation regions 38 and 39 are diffused to connect them.

Next, as shown in FIG. 7, the first island region 3
N ⁺ -type diffusion region 44 and 45 formed in 6, N ⁺ -type diffusion region 4
NPN transistor 31 is completed by using 4 as a collector lead-out region, N ⁺ type diffusion region 45 as an emitter region, and P type diffusion region 46 as a base region. And the second
The P ⁺ type buried layer 43 in the island region 37 is connected to the P ⁺ well region 47 formed by diffusion from the surface of the epitaxial layer 34. Then, on the surface of the P ⁺ well region 47, an N-type channel region 48 and a P ⁺ -type top gate region 49 are formed, and they form a channel.
The P-type diffusion regions 50 and 54 serve as base regions,
⁺ Type diffusion regions 51 and 53 play the role of a drain electrode, and N ⁺ type diffusion region 52 plays a role of a source electrode.
Thus, the junction FET 32 is completed. Thereafter, as shown in FIG. 1, these elements are electrically connected to form the structure of the semiconductor integrated circuit device of FIG.

[0031]

According to the present invention, a P ⁻ -type single-crystal silicon substrate in a semiconductor integrated circuit device having a specific resistance of 1000 Ω · cm or more and a low impurity concentration is used. This makes it possible to reduce the junction capacitance of input elements such as junction FETs and ED-MOS transistors formed on the substrate. Specifically, the specific resistance of the substrate is changed from the conventional 2 to 4 Ω · cm to 1000 Ω of the present invention.
Cm, the junction capacitance can be increased from 4.00 to 8.00 × 10 ⁻⁵ pF / μm ² of the present invention to 4.00 to 8.00 × 10 ⁻⁶ pF / μm ^{2 of the} present invention. become. These input elements have a high input impedance and a small input signal. Therefore, the junction capacitance of these input elements is reduced, so that the input signal passes through the junction capacitance to the ground potential GN.
It is possible to obtain a semiconductor integrated circuit device that can be prevented from flowing out to D and that can reliably output a small signal.

In the case of an NPN transistor formed on the same P ⁻ -type single-crystal silicon substrate as these input elements, boron (B) is ion-implanted into the surface of the substrate on which the NPN transistor is formed. ^- type buried layer is formed. Then, an NPN transistor is formed using the P ⁻ type buried layer as a substrate. As a result, the P ⁻ -type buried layer plays the role of the conventional substrate, and can prevent leakage current in the NPN transistor, achieve junction separation between circuit elements, and the like.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a semiconductor integrated circuit device of the present invention.

FIG. 2 is a sectional view illustrating a semiconductor integrated circuit device of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing method of the present invention.

FIG. 4 is a sectional view illustrating a manufacturing method of the present invention.

FIG. 5 is a sectional view illustrating a manufacturing method of the present invention.

FIG. 6 is a sectional view illustrating a manufacturing method of the present invention.

FIG. 7 is a cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 8 is a cross-sectional view illustrating a conventional semiconductor integrated circuit device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/337 29/808 F term (Reference) 5F003 AP04 AP05 BA11 BA25 BA91 BC01 BC02 BC08 BG05 BJ15 BJ16 BM01 BP31 5F048 AA07 AA10 AC02 AC07 BA07 BA13 BD05 BG12 BH01 CA03 CA07 5F082 AA06 BA02 BA04 BA12 BA13 BA22 BA47 BC03 BC08 BC09 EA02 EA22 5F102 FA05 GA02 GA12 GB01 GC01 GD04 GJ00 GK02 GL03 GM02 HC01

Claims (5)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of a reverse conductivity type laminated on a surface of the substrate, and a semiconductor substrate of one conductivity type separating the epitaxial layer to form first and second island regions. An isolation region, wherein the impurity concentration of the semiconductor substrate is reduced to increase the specific resistance;
And a surface impurity concentration of the semiconductor substrate is increased by forming a buried layer of one conductivity type in the semiconductor substrate below one of the island regions of the second island region. . 2. The semiconductor substrate according to claim 1, wherein said semiconductor substrate has a specific resistance of 1000Ω ·
2. The semiconductor integrated circuit device according to claim 1, wherein the distance is not less than cm. 3. A junction type FET used as an input element in the first or second island region having no buried layer.
2. The semiconductor integrated circuit device according to claim 1, wherein an ED-MOS transistor is formed. 4. The semiconductor integrated circuit device according to claim 1, wherein an NPN transistor is formed in said first or second island region having said buried layer in said semiconductor substrate. 5. A step of preparing a semiconductor substrate of one conductivity type; a step of forming a buried layer of one conductivity type by ion-implanting and diffusing ions into a part of the semiconductor substrate; Forming a buried layer of one type and an isolation region of one conductivity type; forming an epitaxial layer of the opposite conductivity type on the semiconductor substrate; forming the isolation region penetrating the epitaxial layer; Separating an island region and a second island region; forming an NPN transistor in the island region of the first or second island region where the buried layer is formed in the semiconductor substrate; Forming a junction type FET or ED-MOS transistor used as an input element in an island region of the second island region where the buried layer is not formed in the semiconductor substrate. Semiconductor integrated circuit device and manufacturing method thereof.