JP2002025268A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which wasteful charging and discharging currents can be prevented from being made to flow to the bit line of a reference potential side while a sense amplifier senses and when shift is made from precharging in a memory cell to data reading. SOLUTION: This device is provided with memory cells 10 to 13, the sense amplifier 14 for reading data stored in the memory cells 10 to 13 and outputting the data, bit lines BL (0), ZBL (0), BL (1) and ZBL (1) which are connected to the memory cells 10 to 13 by one bit line to the cells respectively and connected to the sense amplifier by two lines respectively as a pair, circuits 15 and 16 for precharging the pair of the respective bit lines, and transistors Q8 to Q11 for independently performing connection/disconnection between the respective bit lines and the sense amplifier 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device including a DRAM cell for embedding logic.

[0002]

2. Description of the Related Art Conventionally, a DR for mixed logic is used.
As a semiconductor device including an AM (Dynamic Random Access Memory) cell,
For example, a semiconductor device as shown in FIG. 3 is provided.

Each of the DRAM memory cells 100 to 103 included in the semiconductor device has a transistor Q1.
01 and a capacitor C101.
A charge corresponding to one bit of data is stored in the capacitor C101.
To store 1-bit data.

The transistor Q101 of the memory cell 100
Is connected to a word line WL (0).
The bit line BL (0) is connected to the drain of the transistor Q101. Further, one electrode of the capacitor C101 of the memory cell 100 is connected to the source of the transistor Q101. The other electrode of the capacitor C101 is maintained at the intermediate potential V _DD / 2.

The potential V _DD indicates the power supply potential applied to the drain of the transistor Q101 when storing high-level data in the memory cell, and the same applies to each of the transistors described below. .

The transistor Q101 of the memory cell 101
Is connected to the word line WL (1).
A bit line ZBL (0) paired with the bit line BL (0) is connected to the drain of the transistor Q101. Further, one electrode of the capacitor C101 of the memory cell 101 is connected to the source of the transistor Q101. The other electrode of the capacitor C101 is maintained at the intermediate potential V _DD / 2.

The transistor Q101 of the memory cell 102
Is connected to a word line WL (2).
The bit line BL (1) is connected to the drain of the transistor Q101. Further, one electrode of the capacitor C101 of the memory cell 102 is connected to the source of the transistor Q101. The other electrode of the capacitor C101 is maintained at the intermediate potential V _DD / 2.

The transistor Q101 of the memory cell 103
Is connected to a word line WL (3).
A bit line ZBL (1) paired with the bit line BL (1) is connected to the drain of the transistor Q101. Further, one electrode of the capacitor C101 of the memory cell 103 is connected to the source of the transistor Q101. The other electrode of the capacitor C101 is maintained at the intermediate potential V _DD / 2.

The pair of bit lines BL (0), ZB (B) is located between bit line BL (0) and bit line ZBL (0).
An equalizing circuit 105 for precharging L (0) to the intermediate potential V _DD / 2 is formed. This equalizing circuit 105 includes three transistors Q102 to Q104.
It is constituted by. Transistors Q102 to Q1
A control line BLEQ (0) for turning on / off the equalizing circuit 105 is commonly connected to each of the gates 04. A wiring VBL (0) for supplying the intermediate potential V _DD / 2 is connected to the source or the drain of the transistors Q103 and Q104.

Similarly, each bit line BL (1) and bit line ZBL (1) is
(1) An equalizing circuit 106 for precharging ZBL (1) to the intermediate potential V _DD / 2 is formed.
This equalizing circuit 106 has three transistors Q10
5 to Q107. Transistor Q
A control line BLEQ (1) for turning on / off the equalizing circuit 106 is commonly connected to each gate of 105 to Q107. Transistors Q106, Q1
A wiring VBL (1) for supplying the intermediate potential V _DD / 2 is connected to the source or the drain of 07.

The sense amplifier 104 has a function of reading and outputting data from each memory cell forming one row of the memory cell array, and forms a pair of signal lines BLSA and ZB.
LSA is connected.

The bit line BL is connected to one end of the signal line BLSA.
(0) is connected via a transistor Q108, and a bit line BL (1) is connected to the other end of the transistor Q1.
10 are connected. An input / output line IO for data input / output is connected to the signal line BLSA by the transistor Q.
It is connected via 112.

On the other hand, a bit line ZBL (0) is connected to one end of the signal line ZBLSA via a transistor Q109, and a bit line ZBL (1) is connected to the other end via a transistor Q111. I have. The input / output line ZIO for inputting / outputting data paired with the input / output line IO is connected to the signal line ZBLSA via the transistor Q113.

A control line CL (0) for turning on / off each of the transistors Q108 and Q109 is commonly connected to each gate of the transistors Q108 and Q109. On the other hand, a control line CL (1) for turning on / off each of the transistors Q110 and Q111 is commonly connected to each gate of the transistors Q110 and Q111. The gates of the transistors Q112 and Q113 are commonly connected to a column selection line CSL for turning on / off the transistors Q112 and Q113.

In the semiconductor device described above, for example, data is read from each memory cell forming one row of the memory cell array and output in accordance with the timing shown in FIG. FIG. 4 is a timing chart in the case where low-level data is stored in the memory cell 100 and this data is read from the memory cell 100 and output.

First, by setting the control lines CL (0) and CL (1) to high level and turning on the transistors Q108 to Q111, the pair of bit lines BL (0) and ZBL (0) and the bit line BL (1) The pair of ZBL (1) is connected to the sense amplifier 104 via the pair of signal lines BLSA and ZBLSA.

Next, control lines BLEQ (0), BLEQ
(1) is set to a high level to equalize circuits 105 and 10
6 to turn on the bit lines BL (0), ZBL
(0) pair and bit lines BL (1), ZBL
The pair (1) is precharged to the intermediate potential V _DD / 2.
Thereafter, the control line CL (1) is set to low level to turn off the transistors Q110 and Q111, thereby connecting the pair of the bit lines BL (1) and ZBL (1) to the sense amplifier 10.
Cut off from 4.

Further, by turning the control line BLEQ (0) to low level and turning off the equalizing circuit 105,
A pair of bit lines BL (0) and ZBL (0) is set to a floating state. Since the control line BLEQ (1) is still kept at the high level and the equalizing circuit 106 is on, the bit lines BL (1), ZB
The precharge of the pair of L (1) is continued.

Next, by setting the word line WL (0) to high level and turning on the transistor Q101 of the memory cell 100, the capacitor C1 of the memory cell 100 is turned on.
01 moves to the bit line BL (0), and the potential of the bit line BL (0) is changed to the intermediate potential V _DD /
Change slightly from 2. For example, when low-level data is stored in the memory cell 100, the potential of the bit line BL (0) slightly decreases from V _DD / 2.
Note that since the transistor Q101 of the memory cell 101 is off, the potential of the bit line ZBL (0) becomes V
_DD / 2 is maintained.

Further, by turning on the sense amplifier 104, the sense amplifier 104 is connected to the bit line ZBL.
The bit line BL (0) is set while setting the potential of (0) as the reference potential.
A small change in the potential is detected (sensed) and differentially amplified.
Further, the amplified potential is applied to the bit lines BL (0) and ZBL.
Apply to (0). Thereby, for example, the memory cell 1
When low level data is stored in 00,
The potential of the bit line BL (0) is at the low level ground potential 0V.
Meanwhile, the potential of the bit line ZBL (0) rises to the high-level power supply potential _VDD .

When the column selection line CSL is set to the high level to turn on the transistors Q112 and Q113, the data read from the memory cell 100 is output to the peripheral circuit through the input / output lines IO and ZIO.

[0022]

By the way, in a DRAM, when data is read from a memory cell, the data stored in the memory cell is destroyed, so that the charge transferred from the capacitor of the memory cell to the bit line is lost. It is necessary to rewrite the data in the memory cell by amplifying the data by the sense amplifier and supplying (refreshing) the same to the same capacitor. Therefore, it is necessary to amplify the potential of the bit line connected to the memory cell from which data has been read to a value that can sufficiently refresh the memory cell.

In a conventional semiconductor device including a DRAM, as shown in FIG. 4, for example, when low-level data is stored in a memory cell 100, a bit line BL (0) is sensed by a sense amplifier 104. the potential of the bit line due to potential drops to ground potential 0V of ZBL (0) rises to the power supply potential V _DD V. However,
Thus, it is unnecessary to amplify the potential of the bit line ZBL (0) on the reference potential side. For this reason, there is a problem that during charging by the sense amplifier 104 or when shifting from precharging to reading of data in the memory cell, useless charging / discharging current flows to the bit line ZBL (0) on the reference potential side. .

Therefore, the present invention provides a semiconductor device which can prevent a useless charge / discharge current from flowing through a bit line on the reference potential side during sensing by a sense amplifier or when shifting from precharge to reading of data in a memory cell. The purpose is to provide.

[0025]

In order to solve the above problems, a semiconductor device according to the present invention forms a memory cell array and includes a plurality of memory cells for storing supplied data, and a first terminal. A sense amplifier that differentially amplifies the signal applied to the second terminal and the signal applied to the second terminal to read data stored in the memory cell and applies a differential output to each terminal; A first bit line connected to the first group of memory cells, a second bit line connected to the second group of memory cells, and precharge means for precharging the first and second bit lines And the first
And a second switch for opening and closing between the second bit line and the second terminal of the sense amplifier. And at least one of the first group and the second group of memory cells.
And a control means for activating the connected word line and controlling the precharge means and the first and second switch means.

In the above invention, the control means controls connection / disconnection between the first bit line and the sense amplifier;
The connection / cutoff between the second bit line and the sense amplifier is controlled independently. For this reason, even if the potential of the bit line connected to the memory cell from which data is read is amplified to a value that can sufficiently refresh the memory cell, the bit line paired with the bit line, that is, The potential of the bit line on the reference potential side with respect to the bit line is not unnecessarily amplified. Therefore, during the sensing by the sense amplifier or during the transition from the precharge to the data read in the memory cell, it is possible to prevent the useless charge / discharge current from flowing to the bit line on the reference potential side, and the DR included in the semiconductor device can be prevented.
It is possible to significantly reduce the operating current of the AM and reduce power consumption.

[0027] In the above invention, the control means is the first type.
It is preferable to open the first and second switch means after a predetermined time has elapsed since the start of data reading via the bit line, and to close the first switch means after the predetermined time has elapsed. In this case, since the bit line having a large load capacity is cut off from the sense amplifier during sensing, the speed of the data read operation in the memory cell can be increased.

In the above invention, the control means includes:
The setting may be such that the second switch is opened after a lapse of a predetermined time from the start of data reading via the first bit line. The semiconductor device may include a DRAM, and the sense amplifier may use a shared sense amplifier system.

[0029]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing a part of a semiconductor device including a DRAM cell for logic embedding. FIG. 1 shows four of a plurality of memory cells forming one row of a memory cell array, and sense amplifiers for reading and outputting data stored in these memory cells.

As shown in FIG. 1, memory cells 10-13
Are composed of a transistor Q1 and a capacitor C1, and store one-bit data by storing a charge corresponding to one-bit data in the capacitor C1.

The word line WL (0) is connected to the gate of the transistor Q1 of the memory cell 10. Also,
The bit line BL is connected to the drain of the transistor Q1.
(0) is connected. Further, the transistor Q
One electrode of the capacitor C1 of the memory cell 10 is connected to one source. The other electrode of the capacitor C1 is maintained at the intermediate potential V _DD / 2.

The potential _VDD indicates a power supply potential applied to the drain of the transistor Q1 when storing high-level data in the memory cell, and the same applies to each of the transistors described below. .

The word line WL (1) is connected to the gate of the transistor Q1 of the memory cell 11. Also,
The bit line BL is connected to the drain of the transistor Q1.
The bit line ZBL (0) paired with (0) is connected. Further, one electrode of the capacitor C1 of the memory cell 11 is connected to the source of the transistor Q1. The other electrode of the capacitor C1 is maintained at the intermediate potential V _DD / 2.

The word line WL (2) is connected to the gate of the transistor Q1 of the memory cell 12. Also,
The bit line BL is connected to the drain of the transistor Q1.
(1) is connected. Further, the transistor Q
One electrode of the capacitor C1 of the memory cell 12 is connected to one source. The other electrode of the capacitor C1 is maintained at the intermediate potential V _DD / 2.

The word line WL (3) is connected to the gate of the transistor Q1 of the memory cell 13. Also,
The bit line BL is connected to the drain of the transistor Q1.
The bit line ZBL (1) paired with (1) is connected. Further, one electrode of the capacitor C1 of the memory cell 13 is connected to the source of the transistor Q1. The other electrode of the capacitor C1 is maintained at the intermediate potential V _DD / 2.

The word lines WL (0) and WL (1) are connected to the row decoder 20, and the word lines WL (2) and WL (3)
Are connected to the row decoder 21. The column selection line CSL is connected to the column decoder 30. These decoders are controlled by the control circuit 40 and form a control means as a whole.

Between the bit line BL (0) and the bit line ZBL (0) forming a pair, each bit line BL (0), ZB
An equalizing circuit 15 for precharging L (0) to the intermediate potential V _DD / 2 is formed. This equalizing circuit 15 is constituted by three transistors Q2 to Q4. The equalizer circuit 15 is turned on / off by the control circuit 40 at each gate of the transistors Q2 to Q4.
A control line BLEQ (0) for turning off is commonly connected. A wiring VBL for supplying the intermediate potential V _DD / 2 to the source or drain of the transistors Q3 and Q4.
(0) is connected.

Similarly, each pair of bit lines BL (1) and ZBL (1)
(1) An equalizing circuit 16 for precharging ZBL (1) to the intermediate potential V _DD / 2 is formed. This equalizing circuit 16 includes three transistors Q5 to Q7.
It is constituted by. A control line BLEQ (1) for turning on / off the equalizing circuit 16 by the control circuit 40 is commonly connected to the gates of the transistors Q5 to Q7. A wiring VBL (1) for supplying the intermediate potential V _DD / 2 is connected to the sources or drains of the transistors Q6 and Q7.

The sense amplifier 14 has a function of reading and outputting data from each memory cell forming one row of the memory cell array, and forms a pair of signal lines BLSA and ZBL.
SA is connected. In the present embodiment, a shared sense amplifier system in which pairs formed by two bit lines are connected one by one to the left and right sides of the sense amplifier 14 is used.

That is, the bit line BL (0) is connected to one end of the signal line BLSA via the transistor Q8, and the bit line BL (1) is connected to the other end of the signal line BLSA.
0. An input / output line IO for input / output of data is connected to the signal line BLSA by the transistor Q.
12 are connected. A control line CL (0) for turning on / off the transistor Q8 by the control circuit 40 is connected to the gate of the transistor Q8. Further, a control line CL (1) for turning on / off the transistor Q10 by the control circuit 40 is connected to the gate of the transistor Q10.

On the other hand, a bit line ZBL (0) is connected to one end of the signal line ZBLSA via a transistor Q9, and a bit line ZBL (1) is connected to the other end via a transistor Q11. I have. Also, the signal line ZBL
An input / output line ZIO for data input / output is connected to SA via a transistor Q13. Transistor Q
9 is connected to a control line ZCL (0) for turning on / off the transistor Q9 by the control circuit 40. The control line ZCL (0) is connected to the control line CL.
Paired with (0). Also, the transistor Q11
The transistor Q
11 is connected to a control line ZCL (1) for turning on / off the control line CL.
Paired with (1).

The gates of the transistors Q12 and Q13 are connected to the transistors Q12 and Q13 by the column decoder 30.
13 are commonly connected to a column selection line CSL for turning on / off.

In the semiconductor device described above, for example, data is read from each memory cell forming one row of the memory cell array and output according to the timing shown in FIG. FIG. 2 is a timing chart in the case where low-level data is stored in the memory cell 10 and this data is read from the memory cell 10 and output.

First, by setting the pair of control lines CL (0) and ZCL (0) and the pair of control lines CL (1) and ZCL (1) to high level and turning on the transistors Q8 to Q11, the bit A pair of lines BL (0) and ZBL (0) and a pair of bit lines BL (1) and ZBL (1) are connected to the sense amplifier 14 via a pair of signal lines BLSA and ZBLSA.

Next, control lines BLEQ (0), BLEQ
By turning on (1) the high level and turning on the equalizing circuits 15 and 16, the bit lines BL (0), ZBL
(0) pair and bit lines BL (1), ZBL
The pair (1) is precharged to the intermediate potential V _DD / 2.
Thereafter, the pair of bit lines BL (1) and ZBL (1) is cut off from the sense amplifier 14 by turning the pair of control lines CL (1) and ZCL (1) low and turning off the transistors Q10 and Q11. I do.

Further, by turning the control line BLEQ (0) to low level and turning off the equalizing circuit 15, the pair of bit lines BL (0) and ZBL (0) is brought into a floating state. Since the control line BLEQ (1) is kept at the high level and the equalizing circuit 16 is in the ON state, the precharge of the pair of the bit lines BL (1) and ZBL (1) is continued.

Next, by setting the word line WL (0) to high level and turning on the transistor Q1 forming the memory cell 10, the electric charge stored in the capacitor C1 forming the memory cell 10 is transferred to the bit line BL ( Move to 0). As a result, the potential of the bit line BL (0) slightly changes from the intermediate potential V _DD / 2. For example, when low-level data is stored in the memory cell 10,
The potential of the bit line BL (0) slightly decreases from V _DD / 2. Note that since the transistor Q1 included in the memory cell 11 is off, the potential of the bit line ZBL (0) is kept at V _DD / 2.

Further, by turning on the sense amplifier 14, the sense amplifier 14 detects (senses) a minute change in the potential of the bit line BL (0) while using the potential of the bit line ZBL (0) as the reference potential. Perform differential amplification. After a predetermined time from the start of sensing by the sense amplifier 14, that is, after amplifying the potential of the bit line ZBL (0) to some extent, the control lines CL (0) and ZCL (0) are set to low level, and the transistors Q8 and Q9 Is turned off, the bit lines BL (0) and ZBL (0) are cut off from the sense amplifier 14.

Thus, the potential of bit line BL (0) is differentially amplified to some extent, and bit line ZBL (0) is amplified.
Is also differentially amplified to some extent. For example, when low-level data is stored in the memory cell 10,
While the potential of the bit line BL (0) further decreases slightly,
The potential of bit line ZBL (0) slightly increases from intermediate potential V _DD / 2. At this time, the signal lines BLSA, ZBL
Since the SA is connected to the sense amplifier 14, the potential of the signal line BLSA drops to the ground potential 0V, and the potential of the signal line ZBLSA rises to the power supply potential V _DD to form data to be output to the peripheral circuit. You.

When the column selection line CSL is set to the high level to turn on the transistors Q12 and Q13, data read from the memory cell 10 is output to peripheral circuits through the input / output lines IO and ZIO.

Thereafter, the control line CL (0) is set to the high level and the transistor Q8 is turned on again, so that the potential of the bit line BL (0) is set to a value (0 V in the figure) for sufficiently refreshing the memory cell 10. ), The same data as before is written into the memory cell 10 again. When rewriting the data of each of the memory cells 10 to 13, the control lines CL (0) and ZCL (0)
Only the bit line connected to the memory cell in which data is to be rewritten needs to be at a high level.

As described above, in this embodiment, the transistor Q8 for connecting / disconnecting the bit line BL (0) and the sense amplifier 14 and the bit line ZBL
(0) and the transistor Q9 for connecting / disconnecting the sense amplifier 14 are connected to separate control lines CL (0), Z
It is connected to the control circuit 40 via CL (0). Therefore, under the control of the control circuit 40, the transistor Q8
While the transistor Q9 is turned off, the potential of the bit line BL (0) is amplified to a value that sufficiently refreshes the memory cell 10 even if the potential of the bit line BL (0) is amplified.
The potential of L (0) is not unnecessarily amplified. Therefore, according to the present embodiment, during sensing by the sense amplifier 14,
When shifting from precharge to reading of data in a memory cell, useless charge / discharge current can be prevented from flowing to a bit line on the reference potential side, and a DRAM included in a semiconductor device can be prevented.
It is possible to greatly reduce the operating current and power consumption.

During the sensing operation of the sense amplifier 14, the bit lines BL (0), ZBL
Since (0) is cut off from the sense amplifier 14, the speed of the data read operation in the memory cell can be increased.

In this embodiment, the control line ZCL
When (0) is set to low level, the control line CL (0) is also set to low level. After that, the control line CL (0) needs to be set to high level for refreshing the memory cell 10. , The control line C as shown by the dashed line in FIG.
L (0) may be kept at a high level. In this case, the potential of the bit line BL (0) is amplified according to the alternate long and short dash line, and the operation of reading data from the memory cell is slightly slower than that of the present embodiment. The effect can be obtained.

[0056]

As described above, according to the present invention,
During sensing by the sense amplifier or when shifting from precharge to reading of data in the memory cell, useless charge / discharge current can be prevented from flowing to the bit line on the reference potential side.

[Brief description of the drawings]

FIG. 1 is a diagram showing a part of a memory cell array of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a timing of reading and outputting data from a memory cell in the semiconductor device of FIG. 1;

FIG. 3 is a diagram showing a part of a memory cell array of a conventional semiconductor device.

FIG. 4 illustrates an example of a timing at which data is read from a memory cell and output in the semiconductor device of FIG. 3;

[Description of Signs] 10 to 13 Memory cell 14 Sense amplifier 15, 16 Equalizing circuit 20, 21 Row decoder 30 Column decoder 40 Control circuit Q1 to Q13 Transistor C1 Capacitor WL (0) to WL (3) Word line BL (0) , ZBL (0), BL (1), ZBL (1)
Bit lines CL (0), ZCL (0), CL (1), ZCL (1)
Control line

Claims (5)

[Claims] A plurality of memory cells for forming a memory cell array and storing supplied data; and differentially amplifying a signal applied to a first terminal and a signal applied to a second terminal. By doing so, a sense amplifier that reads data stored in a memory cell and applies a differential output to each terminal, a first bit line connected to a first group of memory cells, A second bit line connected to a memory cell, a precharge unit for precharging the first and second bit lines, and a first terminal of the sense amplifier. A first switch for opening and closing between the first group and the second group; a second switch for opening and closing between the second bit line and a second terminal of the sense amplifier; At least one of the memory cells With activating connection word line, the semiconductor device comprising a control means for controlling said precharging means and said first and second switching means. 2. The control means opens the first and second switch means after a lapse of a predetermined time from the start of data reading through the first bit line, and further after the lapse of a predetermined time, 2. The semiconductor device according to claim 1, wherein the first switch is closed. 3. The semiconductor device according to claim 1, wherein said control means opens said second switch means after a lapse of a predetermined time from the start of data reading via said first bit line. apparatus. 4. The semiconductor device according to claim 1, wherein said semiconductor device includes a dynamic random access memory (DRAM). 5. The semiconductor device according to claim 1, wherein said sense amplifier uses a shared sense amplifier system.