JP2002024315A - シミュレーションによって送信元同期リンク機能設計を検証するためのプログラマブル遅延要素 - Google Patents

シミュレーションによって送信元同期リンク機能設計を検証するためのプログラマブル遅延要素

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Publication number
JP2002024315A
JP2002024315A JP2001124299A JP2001124299A JP2002024315A JP 2002024315 A JP2002024315 A JP 2002024315A JP 2001124299 A JP2001124299 A JP 2001124299A JP 2001124299 A JP2001124299 A JP 2001124299A JP 2002024315 A JP2002024315 A JP 2002024315A
Authority
JP
Japan
Prior art keywords
delay
data
slice
delay element
data slice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001124299A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002024315A5 (enExample
Inventor
Darren S Jue
ダレン・エス・ジュー
Ashish Gupta
アシシュ・ガプタ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2002024315A publication Critical patent/JP2002024315A/ja
Publication of JP2002024315A5 publication Critical patent/JP2002024315A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2001124299A 2000-04-28 2001-04-23 シミュレーションによって送信元同期リンク機能設計を検証するためのプログラマブル遅延要素 Pending JP2002024315A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/560191 2000-04-28
US09/560,191 US6611936B2 (en) 2000-04-28 2000-04-28 Programmable delay elements for source synchronous link function design verification through simulation

Publications (2)

Publication Number Publication Date
JP2002024315A true JP2002024315A (ja) 2002-01-25
JP2002024315A5 JP2002024315A5 (enExample) 2006-11-24

Family

ID=24236742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001124299A Pending JP2002024315A (ja) 2000-04-28 2001-04-23 シミュレーションによって送信元同期リンク機能設計を検証するためのプログラマブル遅延要素

Country Status (3)

Country Link
US (1) US6611936B2 (enExample)
EP (1) EP1150224A3 (enExample)
JP (1) JP2002024315A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012105013A1 (ja) * 2011-02-02 2012-08-09 富士通株式会社 回路設計支援装置、回路設計支援プログラムおよび回路設計支援方法

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US6785832B2 (en) * 2001-06-22 2004-08-31 International Business Machines Corporation Process independent source synchronous data capture apparatus and method
US6920584B2 (en) * 2001-11-02 2005-07-19 Sun Microsystems, Inc. System design verification using selected states of a processor-based system to reveal deficiencies
FR2841668B1 (fr) * 2002-06-26 2006-08-11 Emulation And Verification Eng Procede et systeme d'emulation d'un circuit sous test associe a un environnement de test
US7382824B1 (en) * 2004-08-13 2008-06-03 Emc Corporaration Method and apparatus for accurate modeling of multi-domain clock interfaces
US7355435B2 (en) * 2005-02-10 2008-04-08 International Business Machines Corporation On-chip detection of power supply vulnerabilities
US20060176096A1 (en) * 2005-02-10 2006-08-10 International Business Machines Corporation Power supply insensitive delay element
US7279949B2 (en) * 2005-02-11 2007-10-09 International Business Machines Corporation Programmable delay element
US7131093B1 (en) 2006-02-07 2006-10-31 International Business Machines Corporation Methods and apparatus for creating a programmable link delay
US8887045B2 (en) * 2008-06-11 2014-11-11 Caterpillar Inc. System and method for providing data links
CN102591754A (zh) * 2011-01-18 2012-07-18 智比特信息技术（镇江）有限公司 用于由计算机控制的电子产品的自动测试方法
US20180181332A1 (en) * 2014-10-29 2018-06-28 International Business Machines Corporation Expanding a dispersed storage network memory beyond two locations
US20180113747A1 (en) * 2014-10-29 2018-04-26 International Business Machines Corporation Overdrive mode for distributed storage networks
US10095582B2 (en) * 2014-10-29 2018-10-09 International Business Machines Corporation Partial rebuilding techniques in a dispersed storage unit
US10459792B2 (en) * 2014-10-29 2019-10-29 Pure Storage, Inc. Using an eventually consistent dispersed memory to implement storage tiers
US10223033B2 (en) * 2014-10-29 2019-03-05 International Business Machines Corporation Coordinating arrival times of data slices in a dispersed storage network
CN112448867B (zh) * 2020-11-26 2022-06-21 海光信息技术股份有限公司 信号延时测试方法、装置、计算机可读存储介质及电子设备

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US5633813A (en) * 1994-05-04 1997-05-27 Srinivasan; Seshan R. Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits
US5862361A (en) * 1995-09-07 1999-01-19 C.A.E. Plus, Inc. Sliced synchronous simulation engine for high speed simulation of integrated circuit behavior
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US6115769A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Method and apparatus for providing precise circuit delays
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US6078545A (en) * 1996-12-26 2000-06-20 Oki Electric Industry Co., Ltd. Data transfer circuit
US6133751A (en) * 1998-08-05 2000-10-17 Xilinx, Inc. Programmable delay element
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US6073194A (en) 1997-07-31 2000-06-06 Advanced Micro Devices, Inc. Transaction based windowing methodology for pre-silicon verification
US5936977A (en) * 1997-09-17 1999-08-10 Cypress Semiconductor Corp. Scan path circuitry including a programmable delay circuit
US5970052A (en) 1997-09-19 1999-10-19 International Business Machines Corporation Method for dynamic bandwidth testing
US5936953A (en) * 1997-12-18 1999-08-10 Raytheon Company Multi-mode, multi-channel communication bus
US6222407B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Dual mode programmable delay element
US6421784B1 (en) * 1999-03-05 2002-07-16 International Business Machines Corporation Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element
US6397354B1 (en) * 1999-03-26 2002-05-28 Hewlett-Packard Company Method and apparatus for providing external access to signals that are internal to an integrated circuit chip package
US6378092B1 (en) * 1999-10-15 2002-04-23 Hewlett-Packard Company Integrated circuit testing
US6348827B1 (en) * 2000-02-10 2002-02-19 International Business Machines Corporation Programmable delay element and synchronous DRAM using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012105013A1 (ja) * 2011-02-02 2012-08-09 富士通株式会社 回路設計支援装置、回路設計支援プログラムおよび回路設計支援方法
JPWO2012105013A1 (ja) * 2011-02-02 2014-07-03 富士通株式会社 回路設計支援装置、回路設計支援プログラムおよび回路設計支援方法

Also Published As

Publication number Publication date
EP1150224A2 (en) 2001-10-31
US6611936B2 (en) 2003-08-26
US20030106005A1 (en) 2003-06-05
EP1150224A3 (en) 2003-04-02

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