JP2002023968A - Controller of semiconductor storage device and flash memory storage system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor storage device controller reducing its power consumption by reducing the power consumption of a memory storing a program for controlling a CPU. SOLUTION: A flash memory controller 100 has a host interface circuit 4 for electrically connecting a host system 1, a CPU 5 for controlling respective constitutional parts in the controller 100, RAMs 12, 13 allowed to be individually operated as work areas such as the storage and stack areas of a control program of the CPU 5, a ROM 7 for storing a boot program, a sequencer 8 for controlling respective constitutional parts in the controller 100, an ECC circuit 9 for detecting/correcting a data error, a sector buffer and management information buffer memory 10 for temporarily storing data outputted from the host system 1 and the flash memory 3 and storing table data for managing a defective data area, and a flash memory interface circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a control device for a semiconductor memory device, and more particularly to a control device for controlling a flash memory.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional flash memory controller 90. FIG. 3 shows a flash memory storage system in which the host system 1 and the flash memory 3 are connected to the flash memory controller 90.

[0003] The flash memory controller 90 is a control device for writing data to the flash memory 3 and reading data from the flash memory 3, and writes data avoiding a defective memory area included in the flash memory 3. Like, flash memory 3
It also has a function of managing the memory area.

As shown in FIG. 4, a flash memory controller 90 includes a host interface circuit 4 for making an electrical connection to the host system 1 and a CPU (Central Processing Unit) for controlling each component inside the controller.
5. RAM (Random Access Memory) which is a work area for storing a control program of the CPU 5 and a stack area, etc.
ry) 6, a ROM 7 for storing a boot program for activating the flash memory controller 90 when the power of the flash memory controller 90 is turned on, a sequencer 8 for controlling a routine operation of each component inside the controller, and an ECC for detecting and correcting data errors. Error Correcting C
odes) circuit 9, a sector buffer and management information buffer memory 10 for storing table data for temporarily storing data from the host system 1 and the flash memory 3 and managing a defective data area, and the flash memory 3. It has a flash memory interface circuit 11 for performing an interface.

When a power supply voltage is applied from the host system 1 to the flash controller 90 and the flash memory 3, the CPU 5 starts a preparation operation according to a boot program stored in the ROM 7.

That is, first, the CPU 5 reads a program for operating the controller stored in the flash memory 3 in accordance with the boot program, and
Then, the table data for managing the defective data area, which is also stored in the flash memory 3, is read out and transferred to the sector buffer and management information buffer memory 10 to complete the operation preparation.

Thereafter, the operation of the flash memory controller 90 is controlled by the CPU 5 based on the control program transferred to the RAM 6.

[0008]

As described above,
In the flash memory controller 90, the CPU 5
Since the program stored in the RAM 6 must be constantly read for the operation of the above, the ratio of the operating current of the RAM 6 to the operating current of the flash memory controller 90 is large, and the power consumption of the RAM 6 cannot be ignored.

Further, when the memory capacity of the RAM 6 is increased, the area of the memory cell array is increased, and the capacitive load parasitic on the word lines and bit lines is increased. It becomes necessary to enhance the driving capability of the driver, and as a result, there is a problem that the power consumption of the RAM 6 increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has been made in consideration of the problem of reducing the power consumption of a memory storing a program for controlling a CPU, thereby controlling a semiconductor memory device having reduced power consumption. The aim is to obtain a device.

[0011]

According to a first aspect of the present invention, there is provided a control device for a semiconductor memory device, which controls a data read / write operation of the semiconductor memory device. A first random access memory and a second random access memory which are separately operable for storing a program for controlling the operation of the control device in a divided manner.

The control device for a semiconductor memory device according to claim 2, wherein the first random access memory stores a program for controlling an operation of reading the data from the semiconductor memory device. The second random access memory stores a program for controlling an operation of writing the data to the semiconductor memory device.

According to a third aspect of the present invention, in the control device for a semiconductor memory device, the first random access memory is configured to perform a normal read operation of the data from the semiconductor memory device and a normal read operation of the data to the semiconductor memory device. A program for controlling a write operation is stored, and the second random access memory stores a program for dealing with an error in the normal write and the normal read operation of the data in the semiconductor memory device.

According to a fourth aspect of the present invention, there is provided a control device for a semiconductor memory device, which reads data from the semiconductor memory device,
A control device for controlling a write operation, comprising first and second read-only memories provided in the control device and separately operable for storing a program for controlling the operation of the control device in a divided manner. The first read-only memory stores a program for controlling an operation of reading the data from the semiconductor storage device, and the second read-only memory stores a program of writing the data to the semiconductor storage device. Stores the program to be controlled.

According to a fifth aspect of the present invention, a control device for a semiconductor memory device reads data from the semiconductor memory device,
A control device for controlling a write operation, comprising first and second read-only memories provided in the control device and separately operable for storing a program for controlling the operation of the control device in a divided manner. The first read-only memory stores a program that controls a normal read operation of the data from the semiconductor storage device and a normal write operation of the data to the semiconductor storage device, and the second read-only memory stores A control device for a semiconductor storage device, which stores a program for dealing with an error in the normal writing and the normal reading operation in the semiconductor storage device of the data.

A flash memory storage system according to a sixth aspect of the present invention includes a flash memory as the semiconductor storage device, and the control device according to any one of the first to fifth aspects, A control device is a flash memory controller that controls data read and write operations of the flash memory based on instructions from a host system.

[0017]

FIG. 1 shows a configuration of a flash memory controller 100 as an embodiment of a control device for a semiconductor memory device according to the present invention.

<A. Apparatus Configuration> In FIG. 1,
1 shows a flash memory storage system in which a host system 1 and a flash memory 3 are connected to a flash memory controller 100.

The flash memory controller 100 includes:
A control device that writes data to the flash memory 3 and reads data from the flash memory 3. The memory device of the flash memory 3 is configured to write data while avoiding a defective memory region included in the flash memory 3. It also has the function of managing

As shown in FIG. 1, a flash memory controller 100 includes a host interface circuit 4 for making an electrical connection to a host system 1 and a CPU (Central Processing Unit) for controlling each component inside the controller.
t) 5, independently operable independent RAMs (Random Access Memory) 12 and 13 serving as a work area such as a storage area for a control program for the CPU 5 and a stack area, and the flash memory controller 100 is activated when the flash memory controller 100 is powered on. ROM 7 for storing a boot program to be executed, a sequencer 8 for controlling a routine operation of each component inside the controller, and ECC (Error Correcting Codes) for detecting and correcting data errors.
A circuit 9, a sector buffer and management information buffer memory 10 for storing table data for temporarily storing data from the host system 1 and the flash memory 3 and managing a defective data area, and an interface with the flash memory 3. And a flash memory interface circuit 11.

Next, the operation of the flash controller 100 will be described. <B. Device operation><B-1. Preparation Operation> When a power supply voltage is applied from the host system 1 to the flash controller 100 and the flash memory 3, the CPU 5 starts the preparation operation according to the boot program stored in the ROM 7.

That is, first, the CPU 5 reads a program for operating the controller stored in the flash memory 3 according to the boot program, and
2 and 13 and then read the table data for managing the defective data area also stored in the flash memory 3 and transfer it to the sector buffer and management information buffer memory 10 to complete the operation preparation. .

Thereafter, the operation of the flash memory controller 100 is controlled by the CPU 5 based on the control program transferred to the RAMs 12 and 13.

Here, prior to describing the operation of the CPU 5, a problem inherent to the flash memory will be described.

The flash memory has an inherent problem that, unlike other storage devices such as a RAM, the occurrence rate of defective elements (defective data areas) is high. Therefore, actual addresses in the flash memory, so-called physical sector addresses, have a discontinuous structure, and the physical sector address of the usable data area does not match the logical sector address specified by the host system 1 and is inconsistent. Occurs.

Due to such an inconsistency, the logical sector address from the host system 1 cannot accurately access the physical sector address in the flash memory. Therefore, the CPU 5 prepares table data for managing the defective data area in advance, and When a specific logical sector address is specified from the system 1, the operation of converting the address into an actual physical sector address is performed by referring to the table.

<B-2. Operation of CPU 5><B-2-1. Data Read Operation> Host System 1
When a data read command is output, the CPU 5 of the flash memory controller 100 detects this command and performs the following operation.

First, as described above, the logical sector address specified by the host system 1 is converted into the physical sector address in the flash memory 3 based on the table data in the sector buffer and the management information buffer memory 10.

Next, the data read operation is instructed to the sequencer 8 by designating the physical sector address.

The sequencer 8 operates the flash memory interface circuit 11 to read data including ECC from the flash memory 3.

The read data is temporarily stored in the sector buffer and management information buffer memory 10 and is also transferred to the ECC circuit 9.

The ECC circuit 9 checks whether there is an error in the data in the sector buffer and the management information buffer memory 10 based on the ECC code. If there is no error, the data is transferred to the host interface circuit 4.
Is transferred to the host system 1 through

When the ECC circuit 9 detects that there is an error in the data in the sector buffer and the management information buffer memory 10, the CPU 5 sends the errored sector information from the ECC circuit 9 and, if possible, corrects it. The read data is read, and the corresponding data in the sector buffer and management information buffer memory 10 is corrected.

Thereafter, the data is transferred to the host system 1
Is forwarded to If the error content exceeds the correction capability of the ECC circuit 9, the CPU 5 outputs a data error to the host system 1.

<B-2-2. Data Write Operation> When a data write command is output from the host system 1 and data is transferred, the CPU 5 of the flash memory controller 100 detects this command and performs the following operation.

First, the transferred data is temporarily stored in the sector buffer and management information buffer memory 10.

Next, based on the table data in the sector buffer and management information buffer memory 10, the logical sector address specified by the host system 1 is converted into a physical sector address in the flash memory 3.

The data write operation is instructed to the sequencer 8 by designating the physical sector address.

The sequencer 8 operates the flash memory interface circuit 11 to write data in the sector buffer and the management information buffer memory 10 to the flash memory 3 via the flash memory interface circuit 11. This data is also sent to the ECC circuit 9 at the same time.
And an ECC code is generated.

Then, the generated ECC code is written in the ECC code storage area of the physical sector in which the data has been written.

When the data including the ECC code is normally written in the flash memory 3, the sequencer 8 detects the fact and notifies the CPU 5, and the CPU 5 notifies the host system 1 of the end of the writing.

If the CPU 5 detects that a write error has occurred in writing to the flash memory 3 via the sequencer 8, the CPU 5 converts the logical sector address to the physical sector address in the sector buffer and the management information buffer memory 10. The data is changed, and a logical sector address specified by the host system 1 is allocated to a spare area existing in the flash memory 3 to perform the above-described write operation.

The operation of the CPU 5 described above is performed based on the control programs stored in the RAMs 12 and 13 as described above.

<C. Configuration of RAM 12> Here, RAM
The configuration of 12 and 13 will be described. In addition, RAM
Since 12 and 13 have the same configuration, the configuration of the RAM 12 will be described below as a representative.

FIG. 2 is a block diagram showing the configuration of the RAM 12. As shown in FIG. 2, the RAM 12 includes an address latch 113 for latching an input address signal, a write signal latch 114 for latching an input write signal,
AND to which memory select signal and clock signal are input
A gate 115, an address decoder 116 connected to the address latch 113, a memory cell array 124, a main address decoder and a word line driver 117 for selecting a word line of the memory cell array 124 based on the address signal, and a memory cell array 1 based on the address signal.
A which is connected to a column sector 118 for selecting 24 bit lines, a write signal latch 114 and an AND gate 115 and performs an AND operation of a write signal and a memory select signal
ND gate 119, data input latch 120 for latching input data, data output latch 121 for latching output data, write driver 122 connected to data input latch 120, and data output latch 1
A sense amplifier 123 is provided between the column selector 21 and the column selector 118.

<D. Operation of RAM 12><D-1. Data Read Operation> Next, a data read operation of the RAM 12 will be described. To read data, an address on the memory cell array 124 is specified based on the input address signal, and the write signal is set to an “H (high potential)” signal, and the memory selection signal is set to “L”.
(Low potential) signal. The memory selection signal is applied to the inverted input of the AND gate 115.

The memory selection signal input to AND gate 115 is output as an "H" signal at the rising edge of the clock input, and the address signal and the write signal are latched by address latch 113 and write signal latch 114, respectively. .

The address signal latched by address latch 113 is decoded by address decoder 116,
Main address decoder and word line driver 117
And the column sector 118. The address signal is further decoded by the main address decoder and word line driver 117, and selects and drives one word line 125 in the memory cell array 24.

On the other hand, the column selector 118 selects the bit line 126 in the memory cell array 124. The data in one memory cell 127 thus selected is transmitted to the output latch 121 via the sense amplifier 123. This data is output as a data output signal at the falling edge of the clock input.

<D-2. Data Write Operation> On the other hand, in order to write data,
20, the address on the memory cell array 124 is specified based on the input address signal, the write signal is an "L" signal, and the memory select signal is an "L" signal.
Give as a signal.

The memory selection signal is output as an "H" signal at the rising edge of the clock input, and the address signal, the write signal, and the data are stored in the address latch 113, the write signal latch 114, and the data input latch 1, respectively.
20 latched.

The address signal latched by address latch 113 is decoded by address decoder 116,
Main address decoder and word line driver 117
And the column sector 118. The address signal is further decoded by the main address decoder and word line driver 117, and selects and drives one word line 125 in the memory cell array 124.

The write driver 122 has an AND gate 1
The data input latch 120 is activated when the output of the data input 19 is activated (the write signal is supplied to the inverted input of the AND gate 119).
, The bit line 126 is driven by the write driver 122 to the value of the data input (“H” or “L”),
Data is written to the memory cell 127.

<E. Action and Effect> Thus, the RAM 12
In (and 13), a main address decoder, a word line driver 117 and a write driver 122 are required to drive a word line and a bit line, and the area of the memory cell array 124 is increased in order to increase the memory capacity. Since the parasitic load on the word line and the bit line increases, it is necessary to increase the driving capability of the word line and the bit line driver in order to obtain a certain access time. However, in the flash memory controller 100 according to the present invention, the CPU 5
Is stored separately in the RAMs 12 and 13. For example, if the same control program as that of the related art is stored, the required memory capacity of the RAMs 12 and 13 is the same as that of the related art. RAM in flash memory controller 90 (FIG. 4)
6 (FIG. 4). As a result,
The area of the memory cell array 124 can be smaller than that used for the RAM 6, and the driving capability of each driver can be small. Therefore, the power consumption of the RAMs 12 and 13 can be reduced as compared with the RAM 6.

The control program of the CPU 5 is a RAM.
Since the RAMs 12 and 13 are divided and stored, the RAMs 12 and 13 do not operate in parallel under the control of the CPU 5, and the provision of the RAMs 12 and 13 ensures that the power consumption of the flash memory controller 100 is reduced. Less than.

<F. First Example of Dividing Control Program> As an example of dividing the control program, a program for reading data from the flash memory 3 is stored in the RAM 12, and a program for writing data to the flash memory 3 is stored in the RAM 13. A mode of storing is conceivable.

By doing so, the RAM 12 and RA
M13 can be reliably prevented from operating in parallel, and the power consumption of the flash memory controller 100 can be reduced.

<G. Second aspect of control program division> As another example of the control program division, the RAM 1
2 may store a program related to normal reading and writing, and the RAM 13 may store a program for coping with errors in writing and reading operations in the flash memory 3.

By doing so, it is not necessary to store in the RAM 12 a program for dealing with an error in the flash memory which is unnecessary in normal operation.
Since the storage capacity of the AM 12 can be reduced, and only the program for coping with errors in the flash memory need be stored in the RAM 13, the storage capacity of the RAM 13 can be significantly reduced, and the power consumption of the flash memory controller 100 can be further reduced. Can be reduced.

<H. Modification> In the flash memory controller 100 described with reference to FIG. 1, the boot program is stored in the ROM 7, and the program for controlling the operation of the CPU 5 is divided and stored in the RAM 12 and the RAM 13. RAM12 and RAM as in the flash memory controller 100A shown in FIG.
13, a separately operable independent ROM 2 that stores a program for controlling the operation of the CPU 5 in a divided manner.
8 and 29 may be provided.

In general, a ROM has a simpler structure than a RAM and can have a higher degree of integration, so that it can be smaller than a RAM with the same memory capacity. Therefore, RAM
ROMs 28 and 29 instead of 12 and RAM 13
The size of the controller can be reduced by using.

In FIG. 3, the same components as those of the flash memory controller 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The operation of the flash memory controller 100A is the same as that of the flash memory controller 10A except that a program for controlling the operation of the CPU 5 is read from the ROMs 28 and 29.
Since it is the same as 0, the description is omitted.

In this example, the boot program is stored in the ROM 28 or 29, and the point that the boot program is read from the ROM 28 or 29 when the power is turned on is different from the flash memory controller 100. .

Also, unlike the RAMs 12 and 13, R
Since the OM 28 and the ROM 29 cannot be used as a work area such as a stack area, a writable and readable memory such as a RAM is separately provided as a work area such as a stack area, but is not shown.

The same effect can be obtained by adopting the above-described first and second modes as the mode of dividing the control program stored in the ROM 28 or 29.

In FIGS. 1 and 3, flash memory 3 is shown as a separate semiconductor chip formed on a different semiconductor substrate from flash memory controllers 100 and 100A. It goes without saying that 100 and 100A may be formed on the same semiconductor substrate to form one chip.

[0067]

According to the semiconductor memory device control device of the first aspect of the present invention, the first and second individually operable random memories for dividing and storing the program for controlling the operation of the control device are stored. Since the access memory is provided, for example, if the same control program as that of the related art is stored, the first and second random access memories are compared with the case where all the control programs are stored in one random access memory. Each required memory capacity is smaller. As a result, the area of the memory cell array included in the first and second random access memories can be reduced, the parasitic capacitance of the word lines and bit lines of the memory cell array can be reduced, and the driving capability of the driver can be reduced.
Power consumption can be reduced, and battery life can be extended when applied to a battery-driven portable device or the like.

According to the semiconductor memory control device of the second aspect of the present invention, the first and second random access memories can be reliably prevented from operating in parallel.
The power consumption of the control device can be reduced.

According to the third aspect of the present invention, the first random access memory stores a program for coping with an error of the semiconductor memory device which is unnecessary in the normal operation. Since there is no need, the storage capacity of the first random access memory can be reduced, and the second random access memory only needs to store a program for coping with an error in the semiconductor memory device. The storage capacity of the random access memory can be significantly reduced, and the power consumption of the control device can be further reduced.

According to a fourth aspect of the present invention, there is provided a semiconductor memory device control apparatus according to the fourth aspect, wherein first and second individually operable read-only memories for dividing and storing a program for controlling the operation of the control apparatus. Wherein the first read-only memory stores a program for controlling a data read operation from the semiconductor memory device, and the second read-only memory stores a program for controlling a data write operation to the semiconductor memory device. Since the control program is stored, for example, if the same control program as that of the related art is stored, compared to the case where all the control programs are stored in one random access memory, each of the required first and second read-only memories is required. Has a smaller memory capacity. As a result,
The area of the memory cell array included in the first and second read-only memories can be reduced, the parasitic capacitance of word lines and bit lines of the memory cell array can be reduced, the driving capability of the driver can be reduced, and power consumption can be reduced. . Further, the first and second read-only memories can be reliably prevented from operating in parallel, and the power consumption of the control device can be reduced.

According to the fifth aspect of the present invention, the first and second individually operable read-only memories for dividing and storing the program for controlling the operation of the control device are stored. Wherein the first read-only memory stores a program for controlling a data read operation from the semiconductor memory device, and the second read-only memory stores a program for controlling a data write operation to the semiconductor memory device. Since the control program is stored, for example, if the same control program as that of the related art is stored, compared to the case where all the control programs are stored in one random access memory, each of the required first and second read-only memories is required. Has a smaller memory capacity. As a result,
The area of the memory cell array included in the first and second read-only memories can be reduced, the parasitic capacitance of word lines and bit lines of the memory cell array can be reduced, the driving capability of the driver can be reduced, and power consumption can be reduced. . Further, since it is not necessary to store a program for dealing with an error of the semiconductor memory device which is unnecessary in the normal operation in the first read-only memory, the storage capacity of the first read-only memory can be reduced. Since only the program for coping with the error of the semiconductor memory device needs to be stored in the second read-only memory, the storage capacity of the second read-only memory can be significantly reduced, and the power consumption of the control device can be further reduced. it can.

According to the flash memory storage system of the sixth aspect of the present invention, power consumption can be reduced, and when applied to a battery-driven portable device or the like, the battery life can be extended.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a control device for a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a random access memory according to the embodiment of the control device of the semiconductor memory device according to the present invention;

FIG. 3 is a block diagram showing a configuration of a modification of the embodiment of the control device of the semiconductor memory device according to the present invention.

FIG. 4 is a block diagram showing a configuration of a control device of a conventional semiconductor memory device.

Claims (6)

[Claims] 1. A control device for controlling a data read / write operation of a semiconductor memory device, wherein the control device is provided in the control device and separately divides and stores a program for controlling the operation of the control device. A control device for a semiconductor memory device, comprising a first and a second random access memory that can be used. 2. The first random access memory stores a program for controlling an operation of reading the data from the semiconductor memory device, and the second random access memory stores the program in the semiconductor memory device. 2. The control device for a semiconductor memory device according to claim 1, wherein said control device stores a program for controlling a write operation of said semiconductor device. 3. The first random access memory stores a program for controlling a normal read operation of the data from the semiconductor memory device and a normal write operation of the data to the semiconductor memory device. The control device for a semiconductor memory device according to claim 1, wherein the access memory stores a program for coping with an error in the normal writing and the normal reading operation of the data in the semiconductor memory device. 4. A control device for controlling a data read / write operation of a semiconductor memory device, wherein the control device is provided in the control device and separately divides and stores a program for controlling the operation of the control device. First and second read-only memories, wherein the first read-only memory stores a program for controlling an operation of reading the data from the semiconductor memory device, and wherein the second read-only memory is A control device for a semiconductor storage device, which stores a program for controlling an operation of writing the data to the semiconductor storage device. 5. A control device for controlling a data read / write operation of a semiconductor memory device, wherein the control device is provided in the control device and separately divides and stores a program for controlling the operation of the control device. A first read-only memory capable of controlling a normal read operation of the data from the semiconductor storage device and a normal write operation of the data to the semiconductor storage device; The second read-only memory is a control device for a semiconductor memory device, which stores a program for dealing with an error in the normal writing and the normal reading operation of the data in the semiconductor memory device. 6. A flash memory as the semiconductor storage device, and the control device according to claim 1, wherein the control device is configured to: A flash memory storage system, which is a flash memory controller that controls data read and write operations of the flash memory.