JP2002023723A - False fly-back pulse generating system false - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dispense with adjustment for each device, which adjustment becomes necessary because the use of a low-cost and commercially available IC for exclusive TV use, as a video signal processing IC, to falsely generate FBP(fly-back pulse) causes a large fluctuation in the pulse width due to tempera ture characteristic of IC and difference of resistance value resulting in difficulty in matching a fly-back period of video with a blanking interval. SOLUTION: False FBP pulses are divided into blanking pulses and various process detection inhibiting pulses and these pulses are independently generated. By utilizing the fact that in the video display device which dose not require deflection processes, a blanking interval does not need to be matched to the fly-back interval of video signals, by completing the blanking interval after the clamp pulse completion performed after the output of video signal processing IC, an optimum clamping is assured and interruption of the video signals is prevented. Thus, adjustment normally required for every device is no longer needed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit of a video display device having no deflection system processing, and to various adjustments (color, tint, hue, YCbCr / YP) for a video signal.
bPr / RGB processing).

[0002]

2. Description of the Related Art In a video display device using a cathode ray tube, a sync separation circuit, a deflection circuit,
An image display period and a retrace period are defined by the deflection coil, and a retrace pulse (flyback pulse; hereinafter, referred to as an FBP pulse) corresponding to the retrace period is created.

When the display device is a cathode ray tube system, the FBP pulse is used as a blanking process of a video signal processing circuit and other timing signals. This is because the horizontal / vertical frequency of the input video signal and the deflection frequency for driving the deflection coil are generally the same, that is, the retrace period of the deflection system and the retrace period of the input video signal are almost the same. Such a system was adopted (by NHK TV technical textbook, edited by Japan Broadcasting Corporation).

As described above, the video signal processing circuit for TV (synchronous separation processing, YCbCr / YPbPr processing, etc.) uses a blank pulse and various processing detection inhibiting pulses as F pulses.
A BP pulse is input, and various processes (black extension, blanking process, etc.) are performed based on this pulse.

When the display device is other than a cathode ray tube (pixel display device; liquid crystal panel, DMD panel, PDP
Etc.), it is necessary to create an FBP pulse because the deflection system processing circuit is unnecessary. If the input video signal of the video signal processing circuit for TV and the video display period (the number of effective pixels) of the display device match, a blanking pulse from a timing generator or the like for driving the display device may be used as the FBP pulse. Good. However, when the input video signal and the video display period of the display device are different due to a scan converter (enlargement / reduction processing, frame rate conversion) or the like after the video signal processing circuit, a one-shot multivibrator (standard logic 74HC221, etc.) For example, an FBP pulse is created by tapping a synchronization signal or using an L (coil) and a C (capacitor) and is used in a video signal processing circuit for TV.

[0006]

The video signal processing circuit comprises:
There are many distributions of TV-specific ICs on the market, and they are available at low cost.

However, when an FBP pulse is created in a simulated manner as described in the prior art, there is a large variation in the pulse width due to an error in the temperature characteristic and resistance value of the IC, and the pulse width may be made to coincide with the actual video retrace period. difficult. If it is longer than the retrace period, the image will be interrupted, and if it is smaller, it will cause malfunctions in various processes. Therefore, adjustment is required for each device.

Further, since the retrace period of an image differs depending on the type of image signal, it is necessary to change the one-shot multivibrator or the multiplier of L (coil) and C (capacitor), which increases the circuit scale and cost.

According to the present invention, when a video signal processing circuit for a TV is used in a video display device which does not require deflection processing, the above adjustment is eliminated by using a new blank pulse generation method, thereby reducing the manufacturing cost. By reducing the number of pixels and using a new method for generating various types of process detection inhibition pulses, a circuit independent of the type of video signal is realized, and the circuit size and cost are reduced.

[0010]

In order to achieve the above object, the present invention employs a method in which a pseudo FBP pulse is divided into a blanking pulse and various processing detection inhibiting pulses, and separately formed.

This method focuses on the fact that in a video display device which does not require deflection processing, it is not necessary to make the blanking period coincide with the blanking period of the video signal, and the blanking period is set to the output of the video signal processing IC. By ending after the end of the subsequent clamp pulse, an optimal clamp is assured and the image is prevented from being interrupted. This eliminates the need for adjustment for each device.

Further, the video signal processing circuit for TV performs various processes (detection of a black level, a white level, etc. during a video period, black extension correction and other correction processes) from the synchronization signal. Ideally, this detection is made to coincide with the validity period of the video, but even if the validity period is reached, the effects of the various processes slightly vary. Therefore, malfunctions are prevented by setting the detection prohibition pulses of various processes to be shorter than the effective period of the video.

[0013] This setting can be made smaller than the video signal type depending on whether the video signal type is divided into blocks for all video signal types or whether all the video signal types are shorter than the video validity period. A circuit that is small or independent of the type of video signal can be realized, and the circuit scale can be reduced and the cost can be reduced.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of a video signal processing unit of a video display device according to the present invention. In FIG. 1, 1 is a horizontal synchronizing signal generation circuit, 2 is a clamp pulse generation circuit, 3 is a video processing circuit, 4 is an A / D converter,
Reference numeral 5 denotes a video signal control (blanking pulse generation) circuit.

When the video signal A is input, the horizontal synchronization signal generating circuit 1 separates the synchronization signal from the video signal A and generates a horizontal synchronization signal. On the other hand, the clamp pulse generating circuit 2 is a timing signal (clamp pulse) generating circuit which receives the video signal A and uses the back porch to determine the DC potential in the pedestal period. The video signal control circuit 5 receives the outputs of the horizontal synchronizing signal generation circuit 1 and the clamp pulse generation circuit 2 and determines a blanking period of the video signal. In addition, a blanking pulse and a detection prohibition pulse for prohibiting black level detection used for black extension control of the video signal and the like are created. The video signal processing circuit 3 receives the output of the video signal A, the horizontal synchronizing signal generation circuit 1, the clamp pulse generation circuit 2, the output of the video signal control circuit 5 and the like, determines the DC level reproduction of the video signal A, performs black extension operation, and the like. Various processes are performed.

The output of the video signal processing circuit 3 is input to an A / D converter 4, where it is digitized, subjected to enlargement / reduction, frame rate conversion processing, etc., and sent to a fixed pixel display device (such as a liquid crystal panel).

FIG. 2 is a block diagram of a video signal processing circuit control section showing an embodiment of the present invention, and FIG. 3 is a timing chart for FIG. The English symbols shown in FIG. 3 correspond to the English symbols shown in FIG.

The polarity of a pulse corresponding to the clamp pulse output from the clamp pulse generating circuit 2 is inverted by an inverter circuit 6 (the inverter system is a standard logic I
C, any transistor, etc.), and 7 (flip-flop circuit). By connecting a capacitor between this pulse and GND, the video processing circuit 3 can be more stably
Afterwards can be clamped. The horizontal synchronization signal output from the horizontal synchronization signal generation circuit 1 is input to a preset of the flip-flop circuit 7. The data of the flip-flop circuit 7 and the clear terminal are fixed to the power supply (H level), and the output of / Q and the horizontal synchronizing signal output from the clamp pulse generation circuit 2 or the video processing circuit 3 are ANDed by the AND circuit 8. Thus, a blanking pulse that can be optimally clamped after the video processing circuit 3 can be created.

FIG. 4 shows an example in which an AFC circuit is applied to the horizontal synchronizing signal generation circuit 1. In FIG. 4, 9 is a horizontal sync separation circuit, 10 is an AFC circuit, 11 is an integration circuit,
Reference numeral 12 denotes a horizontal oscillation circuit, and reference numeral 13 denotes a countdown circuit.

The horizontal sync separation circuit 9 separates the video signal A, and the AFC circuit 10 compares the output frequency of the horizontal sync separation circuit 9 with the output frequency phase of the countdown circuit 13 and operates to match the two phases. . The output of the AFC circuit 10 is passed through an integration circuit 11, and the output 12 is connected to a horizontal oscillation circuit to control the oscillation frequency. Countdown circuit 13
Counts down the output of the horizontal oscillation circuit 12
Returned to circuit. The offset B is input to the integration circuit 11 and changes the oscillation phase of the horizontal oscillation circuit 12 to generate a phase difference between the output pulse of the horizontal synchronization separation circuit 9 and the output pulse of the countdown circuit 13. By using the countdown circuit 13 as an output of the horizontal synchronizing signal generation circuit 1, the phase of the horizontal synchronizing signal can be advanced, and this blanking pulse can be generated before the horizontal synchronizing signal (front porch). Become. At this time, there is a delay difference between the horizontal synchronizing signal and the video signal. However, there is no problem because the difference can be generally corrected by a scan converter or the like.

The detection prohibition pulse for various processes may be set to be shorter than the effective period of the video.

Using the above, the phase of the horizontal synchronizing signal is advanced to the point where the image is valid, and the detection inhibition pulse is started at this edge. The end position may be the output end position of the clamp pulse generation circuit 2 or the detection prohibition pulse may be terminated after a certain period (position equal to or more than the back porch) from the start position by the one-shot multivibrator, counter, decoder, or the like. Should be set to. As an example of this circuit configuration, a circuit using a one-shot multivibrator is shown in FIG. 5, and a timing chart is shown in FIG. The English symbols and the like in each part mean the same as above.

9 is a one-shot multivibrator, 1
0 indicates a switch. In this figure, since a one-shot multivibrator containing two circuits is used, two types of detection inhibition pulses can be created by switching the output with a switch.

These use means for measuring the horizontal synchronization of the video signal A, and determine the starting position and pulse width of the blanking pulse based on the measurement result.

A circuit having less than the type of video signal or a circuit independent of the type of video signal, depending on whether the type of the video signal is divided into blocks or whether all are set to be shorter than the effective period of the video To achieve
The circuit scale and cost can be reduced.

[0026]

As described above, by using the blanking pulse of the present invention, the optimum clamping is guaranteed and the interruption of the image is prevented. For this reason, FBP
No adjustment is required for each pulse device. Further, a circuit having less than the types of video signals or a circuit independent of the types of video signals can be realized, and the circuit scale can be reduced and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a video signal processing unit of a video display device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a blanking pulse generation circuit showing one embodiment of the present invention.

FIG. 3 is a timing chart for FIG. 2;

FIG. 4 is a diagram showing an example in which an AFC circuit is applied to the horizontal synchronization signal generation circuit 1.

FIG. 5 is a configuration diagram of various detection inhibition pulse generation circuits showing one embodiment of the present invention.

FIG. 6 is a timing chart for FIG. 5;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Horizontal synchronizing signal generation circuit, 2 ... Clamp pulse generation circuit Synchronization separation processing circuit, 3 ... Video signal processing circuit, 4 ... A
/ D converter, 5: video signal control circuit, 6: inverter circuit, 7: flip-flop circuit, 8: AND circuit, 9 ...
Horizontal sync separation circuit, 10 AFC circuit, 11 integration circuit, 12 horizontal oscillation circuit, 13 countdown circuit,
14: one-shot multivibrator, 15: switch.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/14 H04N 5/14 Z (72) Inventor Atsushi Kaneko 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Yokohama (72) Noboru Sakata, Inventor No. 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 5C020 AA04 AA19 BA04 5C021 PA45 PA83 PA89 SA02 SA17 XA58 5C080 AA05 AA06 AA10 BB05 DD21 DD27 GG08 JJ02 JJ04 5C082 AA02 BB03 CA81 MM02 MM07

Claims (4)

[Claims] In a video signal processing circuit section of a pixel display device, a circuit which requires a pulse corresponding to a video display period or a retrace period, a horizontal synchronization signal generating circuit for generating a horizontal synchronization signal from a video signal, and A blanking pulse generating circuit having a clamp pulse generating circuit for generating a clamp pulse from a video signal and generating a blanking pulse (pseudo flyback pulse) using the output of the horizontal synchronizing signal generating circuit and the clamp pulse generating circuit; A pseudo flyback pulse generation method characterized by comprising: 2. The blanking pulse generation circuit according to claim 1, wherein a blanking is performed based on a start timing of an output pulse of the horizontal synchronization signal generation circuit and an end timing of an output pulse of the clamp pulse generation circuit. A pseudo flyback pulse generation method characterized by generating a pulse. 3. The horizontal synchronizing signal generation circuit according to claim 1, wherein a horizontal synchronizing separation circuit for separating a horizontal synchronizing signal from a video signal, an AFC circuit, an integrating circuit,
A horizontal oscillation circuit, a countdown circuit for dividing the output of the horizontal oscillation circuit, or a circuit corresponding thereto,
Creating a pseudo flyback pulse by shifting the output timing of the horizontal synchronizing signal generation circuit by using a function of shifting the phase of the horizontal synchronizing signal of the video signal, thereby varying the start timing of the blanking pulse. method. 4. A circuit system according to claim 1, further comprising a circuit capable of limiting a period (pulse width), and individually or collectively specifying various input video signals to define an end position of a pseudo flyback pulse. A pseudo flyback pulse generation method.