JP2002023715A - Display control method, display device and method, information processor and method for controlling the display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a display device to cope with various video-signal formats and to perform display with high accuracy even when dot clocks are of a high frequency. SOLUTION: A video signal and horizontal and vertical synchronizing signals are supplied from a computer 2 to a monitor 1 with a video cable 3. The video signal is subjected to an A/C conversion and written in a memory 5. The frequencies of the horizontal and vertical synchronizing signals are measured in a measuring part 11. The number of dots × the number of lines is estimated by referring to the table stored in an EEPROM(electrically erasable and programmable ROM) 18 on the basis of measured results. Signal format data including the dot clocks of the video signal and the size information of an active section which are transmitted from the computer 2 to the monitor 1 with a communication cable 4 are received at a communication part 12. The PLL(phase-locked loop) at the time of the A/D conversion is set by the dot clocks. The write timing of the video signal to the memory 15 is set according to the number of dots × the number of lines and the size information of the active section. Then, the display of the monitor 2 is controlled by a signal format to be supplied from the computer 1 and thus display having high accuracy is performed by the monitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control method, a display device and a method, an information processing device, and a display device for transmitting detailed information of display data to a display device so as to perform more accurate display. It relates to a control method.

[0002]

2. Description of the Related Art In recent years, for example, a display device used by being connected to a computer has been adapted to various display formats. Such a display device compatible with various display formats is called a multi-sync monitor. The multi-sync monitor supports a plurality of display formats such as a plurality of display resolutions and refresh rates (vertical synchronization frequencies). Display devices include CRT (Cathode Ray Tube) and LCD (Liq
uid Crystal Display).

FIG. 8 shows an example of the configuration of a conventional multi-sync monitor. The display device 100 is, for example, an LC
D is used as a display device. The display device 100 and the computer device 101 are connected by a video cable 102. From the computer device 101, for example, an analog R
A video signal 103 composed of a GB signal and a horizontal synchronization signal 1
04 and the vertical synchronization signal 105 are supplied to the display device 100.

[0004] Of these signals, the video signal 103
Is supplied to the A / D converter 106, and the digital RGB
The signal is converted into a digital video signal. The digital video signal is supplied to the resolution conversion unit 107 and to the video signal detection unit 108. The horizontal synchronization signal 104 and the vertical synchronization signal 105 are supplied to a resolution conversion unit 107, a video signal detection unit 108, and a frequency measurement unit 109. The horizontal synchronization signal 104
Is also supplied to the A / D converter 106.

[0005] The digital video signal supplied to the resolution conversion unit 107 is temporarily stored in the memory 110 under the control of the writing timing by the CPU 112 described later. The digital video signal read from the memory 110 is subjected to processing such as thinning-out or interpolation by the resolution conversion unit 107 to be converted into a signal having a desired resolution, and is supplied to the LCD display unit 111 for display.

On the other hand, the video signal detection unit 108 uses the horizontal synchronization signal 104 and the vertical synchronization signal 105 to
The start and end positions of the active section of the supplied digital video signal are detected. The detection result is the CPU (Cen
(Tral Processing Unit) 112. Further, the frequency measuring section 109 supplies the supplied horizontal synchronizing signal 104
And the frequency of the vertical synchronization signal 105 are measured. The frequency information of the measurement result is supplied to the CPU 112.

[0007] The CPU 112 sends the P / P to the A / D converter 106 based on the information supplied as described above.
LL dot clock information is set. The dot clock is a clock for displaying one dot of the video signal, and corresponds to a display period of one dot. Also, C
The PU 112 sets timing information for capturing the supplied digital video signal into the memory 110 in the resolution conversion unit 107 based on the supplied information. Further, the CPU 112 can calculate the approximate number of lines of the input video signal 103 based on the supplied frequency information.
3 format.

The display device is provided with, for example, an operation unit 113 on the front surface for manually performing various settings.
A control signal corresponding to the operation of the operation unit 113 is transmitted to the CPU 112.
Supplied to In addition, an EEPROM (Electrically Eras
In an programmable programmable read only memory (114), factory adjustment values are stored in advance, and, for example, user preset values set by the operation unit 113 are stored.
The EEPROM 114 further stores the input video signal 10
A correspondence table between the frequency information No. 3 and the numbers of horizontal and vertical dots is stored in advance.

FIG. 9 shows the above-mentioned input video signal 103,
An example of the horizontal synchronization signal 104 and the vertical synchronization signal 105 is schematically shown. In this manner, the vertical active section V _act , which is a section corresponding to the line on which the image is included in the input video signal 103 and the image is actually displayed, is the number of lines counted from the position of the synchronization pulse of the vertical synchronization signal 105. Starting from L1, the number of lines L2 from the position of the synchronization pulse
End at position

FIG. 10 shows one horizontal synchronization section indicated by the horizontal synchronization signal 104 in FIG. 9 in an enlarged manner. A horizontal synchronization section of the input video signal 103, that is, a horizontal active section H _act , which is a section in which image data is included in one line and corresponds to a dot where an image is actually displayed, is
The operation starts after a lapse of time T1 from the position of the synchronization pulse of the horizontal synchronization signal 104, and ends after a lapse of time T2 from the position of the synchronization pulse. That is, the horizontal active section H
_{The act} is terminated before the position of the next horizontal synchronization pulse. These times T1 and T2 can be associated with dots on the display screen, and are the numbers of dots N1 and N2, respectively, from the left end of the screen.

In recent years, video signals output from computer devices have many variations in resolution, horizontal and vertical frequencies, video signal dot clocks, and the like, and the format of video signals has been diversified. In the multi-sync monitor, the A / D converter 106 converts the input video signal 103 into an A / D signal so that the video signals of these various formats can be accurately displayed on the screen.
Accurately grasps phase information between the dot clock of the input video signal 103 and the clock of the apparatus for the / D conversion, and timing information for taking only the active section of the digitally converted video signal into the memory 110. There is a need.

Conventionally, the frequency measurement unit 10
9, the setting of the dot clock of the A / D converter 106 and the timing to the resolution converter 107 based on the horizontal and vertical frequencies obtained from Step 9 and the start position and end position information of the active section obtained from the video signal detector 108 Had been set.

FIG. 11 is a flowchart showing an example of a process for setting the A / D converter 106 and the resolution converter 107. First, in the first step S100, the horizontal and vertical frequencies of the input video signal 103 are measured by the frequency measurement unit 109, and the measurement results are transmitted to the CPU 112.
Supplied to In the next step S101, based on the measured frequency information, the CPU 112
Reference is made to the above-described table stored in the 114, and the number of horizontal dots of the video signal 103 (the horizontal active section H
_act ) and the number of vertical lines (vertical active section V
_act ) is estimated.

In step S102, the video signal detector 108 detects the times T1, T
2, L1 and L2 are measured. Measurement results are stored in the CPU
112. In the next step S103, A / D
A dot clock to be set in the PLL of the conversion unit 106 is calculated. For example, when the times T1 and T2 are defined as shown in FIG. 10 described above, the dot clock f _dot
Is determined as _{f dot = H ac t / (} T2-T1).

The obtained dot clock f _dot is A /
This is set for the PLL of the D conversion unit 106 (step S104). Then, timing information for taking the digital video signal into the memory 110 is set in the resolution conversion unit 107. The capture position in the horizontal direction is counted by the number of dots, and the start position is the number of dots N1 = f _do
t × T1, and the end position is the number of bits N2 = _fdot × T2. As for the vertical position, for example, as shown in FIG. 9 described above, the number of lines L1 from the synchronization pulse of the vertical synchronization signal 105 to the start of the vertical active period, and the end of the vertical active period from the synchronization pulse of the vertical synchronization signal 105 The number of lines L2 before the operation is set (step S105).

[0016]

However, in recent years,
Some video signals output from computer devices have a dot clock exceeding 300 MHz. In order to detect a signal of such a frequency by the above-described conventional method, the signal detection circuit needs to have at least 300 MHz.
It needs to operate faster than z.

However, such a detection circuit that operates at a high speed is very expensive and cannot be used in a computer device, especially a personal computer device intended for personal use. Therefore, in practice, a detection circuit operating at a frequency of about 100 MHz is used for detecting a video signal, and accurate video detection cannot be performed. Therefore, the dot display may be shifted due to an error in the dot clock, or the time T1, T2
2. The image size and the image position may be shifted due to an error between the lines L1 and L2. To fix this,
The user must manually adjust the image capture position (display position) using the operation unit 113, which is inconvenient.

Conventionally, in order to solve such a problem, the format data of an existing video signal is stored in the EEPROM 114 in advance to solve the problem. That is, the frequency and time T of the video signal detected by the detection circuit
The format corresponding to the values of 1, T2 and lines L1 and L2 is obtained by referring to the data stored in the EEPROM 114. However, the format data of existing video signals is enormous, and all data is EEP.
To store the data in the ROM 114, the EEPROM 114
There is a problem that it is necessary to increase the capacity of the device, which leads to an increase in cost.

Writing of data to the EEPROM 114 is performed, for example, on an adjustment line of a display device production factory in which the EEPROM 114 is incorporated. As described above, in order to write a huge amount of format data into the EEPROM 114, there is a problem that a tact time is lengthened by a time required for the writing, which causes an increase in production cost.

Further, in a state in which a white window is displayed on a black background as shown in an example in FIG. 12, the video detection unit 108 does not operate normally and the setting is erroneously performed, and the image is not displayed. There was a problem that it could not be displayed correctly.

Accordingly, an object of the present invention is to provide a display control method, a display device and a method, and an information processing device which can support a wide variety of video signal formats and can perform display with high accuracy even when the dot clock has a high frequency. ,
Another object of the present invention is to provide a display device control method.

[0022]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a display control method for a display device capable of displaying video signals of a plurality of signal formats. This is a display control method, wherein information indicating a signal format is notified to a display device, and the display device controls display of a video signal based on the notified information indicating the signal format.

According to the present invention, in a display device capable of displaying video signals of a plurality of signal formats, a display means for displaying an input video signal and a communication means for receiving information indicating a signal format of the video signal are provided. And a display control means for controlling display by the display means based on information indicating a signal format obtained by the communication means.

According to the present invention, in a display method capable of displaying video signals of a plurality of signal formats, a display step of displaying an input video signal and a communication of receiving information indicating a signal format of the video signal are provided. And a display control step of controlling display in the display step based on information indicating a signal format obtained in the communication step.

According to another aspect of the present invention, in an information processing apparatus capable of outputting a video signal, a signal format obtaining means for obtaining information indicating a signal format of the output video signal from inside, A communication unit for notifying the display device on which the video signal is displayed of the information indicating the signal format.

According to the present invention, in a display device control method for controlling a display device on which an output video signal is displayed, a signal format obtaining step for obtaining information indicating the signal format of the output video signal from inside. And a communication step of notifying the display device on which the video signal is displayed of information indicating the signal format acquired in the signal format acquisition step.

As described above, according to the first aspect of the present invention, the information indicating the signal format of the video signal supplied to the display device is notified to the display device, and the display device displays the information indicating the notified signal format. The display device controls the display of the video signal based on the video signal. Therefore, the display device can easily cope with a plurality of video signal formats, and even if a video signal with a high dot clock frequency is input, the display device can accurately display the video signal. Good display.

According to a fifth aspect of the present invention, there is provided a display for receiving information indicating a signal format of a video signal and displaying the input video signal based on the information indicating the received signal format. Since the means is controlled, it is possible to easily cope with the formats of a plurality of video signals, and to perform accurate display even when a video signal having a high dot clock frequency is input.

According to the present invention, the information indicating the signal format of the output video signal is acquired from the inside, and the information indicating the acquired signal format is displayed on the video signal. Display device, the display device side can easily cope with the format of a plurality of video signals, and has high accuracy even when a video signal with a high dot clock frequency is input. Can be displayed.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of an example of a monitor device 1 according to the first embodiment. This is an LCD (Liquid Crystal Displa) as a display device.
5 is an example of an LCD monitor using y). The monitor device 1 and the computer device 2 are connected by a video cable 3 and a communication cable 4, respectively. A video signal composed of, for example, an analog RGB signal output from the computer device 2 is transmitted to the monitor device 1 via the video cable 3. At the same time, the horizontal and vertical synchronizing signals of the video signal are output from the computer device 2 and supplied to the monitor device 1 via the video cable 3.

Further, in the first embodiment of the present invention, signal format data corresponding to a video signal supplied to the monitor device 1 via the video cable 3 is output from the computer device 2 and transmitted via the communication cable 4. Transmitted to the monitor device 1. The monitor device 1 uses the signal format data to generate the dot clock f in the video signal supplied from the computer device 2.
_dot and the number of dots N indicating the start position of the active section
1 and N2, and the number of lines L1 indicating the end position
And L2.

The dot clock f _dot and the start position and end position N1, N2, L1 and L2 of the active section are used in the description of the prior art as shown in FIGS.
0, respectively. That is, the dot clock f _dot indicates a clock frequency for displaying one _dot of the video signal. Also, the start position and the end position N1, N2, L1, and L of the active section
2 is an effective display area in the display area,
The number of dots N1 at the horizontal start position from the left end of the display area,
The number N2 of dots at the end position, the number L1 of lines at the start position in the vertical direction from the upper end of the display area, and the number L2 of lines at the end position are shown.

The video signal supplied to the monitor device 1 is
The signal is supplied to the A / D converter 10. Further, the horizontal and vertical synchronization signals input to the monitor device 1 are supplied to a frequency measurement unit 11 and a resolution conversion unit 13, respectively. The horizontal synchronization signal is also supplied to the A / D converter 10. The frequency measurement unit 11 measures the horizontal and vertical frequencies, respectively, and the measurement result is transmitted to a CPU that controls the entire monitor device 1.
(Central Processing Unit) 14.

The CPU 14 has an EEPROM (Electrically Erasable Programmabl) which is a rewritable memory.
e Read Only Memory) 18 is connected. EEPROM
18 stores in advance factory adjustment values, user preset values of various setting values of the monitor device 1, and the like. Also, EEP
The ROM 18, the number of horizontal dots of the active period _{H a
An} internal table that associates _ct and the number of vertical lines _Vact with the horizontal frequency and the vertical frequency of the video signal is stored in advance.

The CPU 14 refers to this internal table based on the measurement result of the frequency measurement unit 11 and estimates the number of horizontal dots H _act and the number of vertical lines V _act in the active section of the input video signal.

On the other hand, the signal format data transmitted from the computer device 2 is, for example, a USB (Universal S
serial bus) as a communication interface, received by the communication unit 12 via the communication cable 4,
It is supplied to PU14. As described above, the signal format data includes the dot clock f _dot of the video signal output from the computer device 2, the start and end dot numbers N1 and N2 of the horizontal active section, the start and end line numbers L1 and L1 of the vertical active section. L2.

The dot clock f _dot is supplied to the A / D converter 10 and the PLL of the A / D converter 10 is set. The video signal input to the A / D converter 10 is converted into a digital video signal based on the dot clock f _dot and the above-mentioned horizontal synchronizing signal.
Supplied to the memory 15 and connected to the resolution conversion unit 13.
Is written once. At this time, the CPU 14 sets the timing of writing the digital video signal supplied from the A / D converter 10 to the resolution converter 13 to the memory 15 based on the received signal format data. Is done.

The resolution converter 13 reads the video signal written in the memory 15, converts the video signal into a desired resolution, and outputs the converted signal. The resolution conversion is performed by, for example, thinning out a video signal written in the memory and reading the video signal, or by appropriately interpolating the read video signal. The resolution conversion is performed in this manner, and the resolution conversion unit 13
The digital video signal output from is supplied to a display unit 17 composed of an LCD and displayed.

The monitor 1 is provided with, for example, an operation unit 16 on a front panel so that various settings for the monitor 1 can be made by a user. For example, the resolution at the time of displaying the video signal on the display unit 17 can be set by operating the operation unit 16. The setting of the display position of the video signal on the display unit 17 can be set by operating the operation unit 16.

That is, as described above, the setting of the PLL for the A / D converter 10 and the setting of the timing of writing the video signal to the memory 15 for the resolution converter 13 are performed as described above. This is performed based on the signal format data received by the communication unit 12 and also by operating the operation unit 16.

FIG. 2 schematically shows an example of the configuration of the computer device 2. The CPU 21 is a computer bus 20
Communication I / F 24, graphic controller 2
5 and a hard disk drive (HDD) 23. Further, the CPU 21 and the memory 22
It is connected via a PU bus 26. Although not shown, input devices such as a keyboard and a mouse, and external storage devices such as a floppy (registered trademark) disk drive (FDD), a magneto-optical disk drive, and a CD-ROM drive are connected to the computer bus 20.

The communication I / F 24 is, for example, a USB communication interface corresponding to the above-described monitor device 1 and is connected to the monitor device 1 by the above-described communication cable 4. The transmission of the signal format data from the computer device 2 to the monitor device 1 is performed by the communication I / F.
24. Graphic controller 2
5 has a graphic control chip and a video memory,
A video signal is generated based on a display control signal supplied from the CPU 21 via the bus 20. The generated video signal is supplied to the monitor device 1 via the video cable 3. At the same time, the horizontal and vertical synchronizing signals are also supplied to the monitor device 1 via the video cable 3, respectively. The communication I / F 24 and the graphic controller 25 are controlled by the CPU 21 executing the program data read into the memory 22.

In such a configuration, when the format of the video signal is determined by the graphic controller 25, detailed information of the signal format exists in a register on the graphic controller 25. Therefore, first, the contents of the register on the graphic controller 25 are read by the CPU 21, and the signal format of the output video signal is obtained. The acquired signal format data is temporarily stored in the memory 22. Thereafter, the communication I / F 24 is controlled by the CPU 21, and the signal format data stored in the memory 22 is transmitted from the communication I / F 24 to the monitor device 1.

When the format of the output video signal is determined by the program executed by the CPU 21, there is no need to read the signal format data from the register on the graphic controller 25. In this case, the signal format data stored in the memory 22 when the CPU 21 executes the program may be directly supplied to the communication I / F 24 and transmitted.

FIG. 3 is a flowchart of an example of a display setting process according to the first embodiment. The processing according to this flowchart is executed, for example, when the monitor device 1 is activated or when the signal format of the video signal supplied from the computer device 2 is changed. First, in the first step S10, the frequencies of the horizontal and vertical synchronization signals supplied from the computer device 2 via the video cable 3 are measured by the frequency measurement unit 11.

In the next step S11, step S10
EEP connected to CPU 14 based on the measurement result at
Horizontal dots of active section stored in ROM18
Number H _actAnd the number of vertical lines V_actAnd frequency measurement
Refer to the internal table that associates the measurement results with the unit 11
Of the video signal input through the video cable 3
Horizontal dot number H_actAnd the number of vertical lines V_actIs C
Estimated by PU14.

For example, a predetermined range of threshold values is provided for the values of the internal table, and the value corresponding to the range corresponding to the measurement result is set to the number of horizontal dots H of the video signal.
_act and the number of vertical lines _Vact . Estimated number of horizontal dots H _act and number of vertical lines V _act
Is supplied to the resolution conversion unit 13.

In step S12, the computer 2
The communication unit 12 receives the signal format data transmitted from the communication unit 4 via the communication cable 4. Based on the received signal format data, the above-described dot clock f _dot , the number of dots N1 which is the horizontal start position of the active section, and the end of the video signal input to the monitor device 1 via the video cable 3 The number of dots N2 as a position, the number of lines L1 as a start position in the vertical direction of the active section, and the number of lines L2 as an end position in the active section are obtained, respectively.

Then, in the next step S13, the dot clock f _dot obtained in step S12 is set in the PLL of the A / D converter 10, and the start position and end position N1, N2, L1 and L2 of the active section are set. This is set in the resolution conversion unit 13. In the A / D converter 10, the video signal input as an analog signal is converted into a digital video signal based on the set dot clock f _dot . Further, the resolution conversion unit 13, and the number of horizontal dots _{H act} and the number of vertical lines _{V a ct} described above,
The start position and end position N1, N2,
The timing of writing the supplied video signal to the memory 15 is controlled based on L1 and L2.

The frequency information of the video signal output from the computer device 2 can be transmitted from the computer device 2 to the communication cable 4. in this case,
In the monitor device 1, if this frequency information is obtained via the communication unit 12, the frequency measurement unit 11 can be omitted.

Also, H _total and V
_{Even if the total} is transmitted from the computer device 2 to the monitor device 1 via the communication cable 4 together with the dot clock f _dot , the frequency measurement unit 11 can be omitted. Incidentally, V _{tota l} corresponded to 1 cycle of the vertical synchronizing signal V, indicating the total number of lines in the vertical direction of the display area of the display unit 32. In this case, the horizontal frequency f
_H = _f dot _{/ H total,} vertical frequency _f V _{= f} H /
V _total can be obtained.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 shows a configuration of an example of a monitor device 200 according to the second embodiment. In the second embodiment, the monitor 200
(Cathode Ray Tube) is used as a display device in the display unit 32. With the use of a CRT for the display unit 32, a video amplifier 30, a deflection yoke DY31, and a deflection circuit 33 for inputting a video signal to the CRT and controlling deflection of an electron beam in the CRT are provided. In FIG. 4, the same reference numerals are given to the same parts as those in FIG. 1 described above, and detailed description will be omitted.

The video signal output from the computer device 2 and input to the monitor device 200 via the video cable 3 is supplied to the A / D converter 10. Further, the horizontal and vertical synchronization signals are input from the computer device 2 to the monitor device 200 via the video cable 3. These horizontal and vertical synchronization signals are supplied to a frequency measurement unit 11 and a resolution conversion unit 13, and
It is also supplied to the deflection circuit 33. Note that the deflection circuit 33 is
It shall include horizontal and vertical deflection circuits. The horizontal synchronization signal is supplied to the A / D converter 10. Frequency measurement unit 11
Then, the frequencies of the supplied horizontal and vertical synchronization signals are respectively measured, and the measurement results are supplied to the CPU 14.

On the other hand, the signal format data transmitted from the computer device 2 is supplied to the monitor device 200 via the communication cable 4 and received by the communication unit 12. The received signal format data is transmitted from the communication unit 12 to C
It is supplied to PU14.

As described in the first embodiment, the internal table stored in the EEPROM 18 is referred to by the CPU 14 based on the measurement result of the frequency measurement unit 11, and the horizontal dot number H _{act in the} active section is referred to.
× The number of vertical lines V _act is estimated. Communication unit 1
2, the start and end positions N1, N2, L1, and L2 of the dot clock f _dot active section are obtained from the signal format data received in step 2. CPU1
4, the frequency measurement unit 11 and the communication unit 12
Of the dot clock f _dot for the PLL of the A / D converter 10 and the timing of writing the video signal to the memory 15 for the resolution converter 13 based on the information supplied from the control unit 16 and the control signal supplied from the operation unit 16. Is set.

In the second embodiment, the CPU
Based on the information supplied from the frequency measurement unit 11 and the communication unit 12 and the control signal supplied from the operation unit 16, setting of synchronization data for the deflection circuit 33, image distortion, image size, image position, etc. Of the deflection correction data is performed.

The video signal supplied to the A / D converter 10 is a dot clock f _dot set for the PLL.
Is converted into a digital video signal based on This digital video signal is supplied to the resolution conversion unit 13 and
The write timing is controlled in a predetermined manner based on the information supplied from the PU 14, and is written into the memory 15. The digital video signal is read from the memory 15 under the control of the resolution converter 13, converted to a desired resolution by the resolution converter 13, and converted into an analog video signal by a D / A converter (not shown). You.

The video signal output from the resolution conversion unit 13 is amplified in a predetermined manner by the video amplifier 30, and the balance and strength of, for example, RGB signals are adjusted by the display adjustment signal supplied from the CPU 14. The display is adjusted. The video signal output from the video amplifier 30 is supplied to a display unit 32 including a CRT.

On the other hand, the horizontal and vertical synchronization signals input from the computer device 2 via the video cable 3 are as follows:
The signal is supplied to the A / D conversion unit 10, the frequency measurement unit 11, and the resolution conversion unit 13, and is also supplied to the deflection circuit 33. The deflection circuit 33 generates horizontal and vertical deflection signals from the supplied horizontal and vertical synchronization signals, respectively. At this time, under the control of the CPU 14, the horizontal and vertical deflection signals are deflection-corrected in a predetermined manner. The horizontal and vertical deflection signals output from the deflection circuit 33 are supplied to a deflection yoke DY31, which deflects the electron beam based on the above-mentioned video signal in a predetermined manner to obtain a display screen on the display unit 32.

Incidentally, also in the second embodiment,
As in the first embodiment, the computer device 2
By transmitting the frequency information of the video signal output from the computer device 2 to the communication cable 4, the frequency measurement unit 11 can be omitted in the monitor device 200.

Further, H _total and V
_{Even if the total} is transmitted from the computer device 2 to the monitor device 200 via the communication cable 4 together with the dot clock f _dot , the frequency measurement unit 1
1 can be omitted. In this case, the horizontal and vertical frequencies can be obtained in the same manner as in the method described in the first embodiment.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 5 shows the third embodiment.
1 shows a configuration of an example of a monitor device 201 according to the embodiment. In the third embodiment, a CRT is used as a display device of the display unit 32 as in the above-described second embodiment. On the other hand, the analog video signal supplied from the computer device 2 is directly supplied to the video amplifier 30 and supplied to the display unit 32. Therefore, in the third embodiment, display control on the display unit 32 is performed by controlling the deflection circuit 33 by the CPU 14. In FIG. 5, the same parts as those in FIGS. 1 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The video signal output from the computer device 2 is input to the monitor device 201 via the video cable 3 and supplied to the video amplifier 30. In the video amplifier 30, a video signal whose display has been adjusted under the control of the CPU 14 is transmitted to a display unit 32 composed of a CRT.
Supplied to

The horizontal and vertical synchronizing signals output together with the video signals from the computer device 2 are supplied to the frequency measuring section 11 and also to the deflection circuit 33 including horizontal and vertical deflection circuits. Frequency measurement unit 1
The measurement results of the frequencies of the horizontal and vertical synchronizing signals according to No. 1 are supplied to the CPU 14, respectively. The CPU 14 executes EEPRO based on the measurement result of the frequency measurement unit 11.
The internal table stored in M18 is referred to, and the number of horizontal dots _Hact × the number of vertical lines V in the active section is referred to.
_act is estimated.

On the other hand, the signal format data transmitted from the computer device 2 is supplied to the monitor device 201 via the communication cable 4 and received by the communication unit 12. The received signal format data is transmitted to the communication unit 12.
Is supplied to the CPU 14. From the signal format data, the start and end positions N1, N2, L1, and L2 of the dot clock f _dot active section are obtained.

Further, a control signal corresponding to an operation on the operation unit 16 is supplied from the operation unit 16 to the CPU 14.

Based on the information or control signals supplied from the frequency measurement unit 11, the communication unit 12, and the operation unit 16, the CPU 14 sets synchronization data for the deflection circuit 33, and performs image distortion, image size, and image position. The deflection correction data is set as follows.

FIG. 6 is a principle diagram showing a method of controlling the image size and image position displayed on the display unit 32. In the CRT, the image size and the image position of the displayed image are controlled by the horizontal and vertical outputs output from the deflection circuit 33 so that the image is displayed at the center of the screen. Here, in the standard state, deflection control is performed so that one cycle of the horizontal synchronization signal is equal to the horizontal width of the screen.

As shown in FIG. 6A, the total number of dots of the width of the displayable area (referred to as display area) of the display unit 32, which is equal to one cycle of the horizontal synchronizing signal H, is H.
the _{tota l.} On the other hand, the number of dots in the active section of the video signal is H _act, and the start position of the horizontal synchronization signal, that is, the number of dots from the left end of the display area of the display unit 32 to the center of the active section is H _cent . In the example of FIG. 6A, the active section of the video signal is smaller than the display area of the display unit 32, and is displayed shifted rightward from the center position of the display area.

This is shown in FIG. 6B as an example.
It is desirable that the active section of the video signal is substantially full in width with respect to the display area of the display unit 32, and that an image based on the video signal is displayed in the center. Therefore, in the third embodiment, the total number of dots H _total in the horizontal direction of the display area, the number of dots H _{act in} the active section of the video signal, and the number of dots in the center of the active section from the left end of the display area are described above. H _cent is transmitted from the computer device 2 and received by the communication unit 12 of the monitor device 201 via the communication cable 4. By using these received data, it is possible to display the active section of the video signal in the center of the display area and the full area width, as shown in an example in FIG. 6B.

The display control process according to the third embodiment will be described with reference to the flowchart of FIG.
Prior to the processing of this flowchart, in the computer device 2, the above-described dot numbers H _total , H _act, and H _cent regarding the video signal to be output are set.
Is obtained.

For example, referring to the configuration shown in FIG.
In the case determined by 5, the CPU 21 reads the format information of the video signal stored in the register on the graphic controller 25. Based on the read format information, the CPU 21
The number of dots H _total , H _act, and H _cent are obtained. The obtained data is supplied to the communication I / F 24 as signal format data and transmitted.

When the format of the output video signal is determined by the program executed by the CPU 21, the CPU 21 directly converts the signal format data stored in the memory 22 at the time of execution of the program into the communication I / O. It is supplied to F24 and transmitted.

Returning to the description of the flowchart of FIG. 7, in step S 20, the signal format data transmitted from the computer device 2 is supplied to the monitor device 201 via the communication cable 4 and received by the communication unit 12. The received signal format data is transmitted from the communication unit 12 to the CPU.
Is supplied to the 14, the CPU 14, the number of each dot _{H t
total} , H _act and H _cent are obtained.

In step S21, the image size in the horizontal direction is adjusted. As can be seen from FIG. 6 described above, the ratio of the active section of the video signal to one horizontal cycle is:
A _{H a ct} / H _total. Thus, standard time not performed resized, for example, the image size in the case of FIG. 6A When H _{SIZE 0,} obtains image size H _SI
ZE is H _SIZE = H _SIZE 0 × (H _total /
H _act ) is determined in this way. The required image size H _SIZE
Is set in the deflection circuit 33. That is, the deflection circuit 33
, The scan width by the horizontal output signal is the image size H
It is set to be _SIZE .

In the next step S22, the image position is adjusted. The rate of deviation between the center position of one horizontal cycle and the center position of the active section of the video signal is represented by 1 / 2- (H _cent / H _total ) with reference to FIG. Therefore, if the image position is shifted by this amount, the image position where the image based on the video signal is displayed on the display unit 32 can be set at the center of the screen.

[0077] Here, the data for controlling the image position in the horizontal direction and _{H PHASE, H PHASE} 0 the view position when the standard time, for example, FIG. 6A not performed to adjust the image position
Further, the moving amount of the image position per one step is set to p% of one horizontal cycle. In this case, the desired image position H
_PHASE is _{calculated as} follows: H _PHASE = H _PHASE 0+ [1 / 2− (H
_cent / H _total )] × (100 / p) Obtained image position control data H
_PHASE is set in the deflection circuit 33. That is, in the deflection circuit 33, the image position control data _{H P
The HASE} is set so that scanning using the horizontal output signal is performed at substantially the center of the screen.

Although only the processing in the horizontal direction has been described above, the processing in the vertical direction can be similarly performed. For example, regarding the video signal output from the computer device 2, the total number of lines V _total in the display area of the display unit 32, the number of lines V in the active section,
_The number of lines V _cent from the start position of the _act and the vertical synchronization signal to the center position of the active section is transmitted via the communication cable 4 together with the above-described data in the horizontal direction as signal format data. The monitor device 201 receives these data in the vertical direction, and performs processing in the same manner as described with reference to FIG. 7 to display an image in the vertical direction so as to fill the entire display area of the screen. it can.

In the third embodiment, as in the first and second embodiments, the frequency information of the video signal output from the computer device 2 is transmitted from the computer device 2 to the communication cable 4. By transmitting, the frequency measurement unit 11 can be omitted in the monitor device 201.

Further, H _total and V
_{Even if the total} is transmitted from the computer device 2 to the monitor device 201 via the communication cable 4 together with the dot clock f _dot , the frequency measurement unit 1
1 can be omitted. In this case, the horizontal and vertical frequencies can be obtained in the same manner as in the method described in the first and second embodiments.

In the first, second, and third embodiments, the interface for transmitting the signal format data is described as the USB (Universal Serial Bus), but this is not limited to this example. Not done. The communication interface used here is the monitor device 1
Any interface can be used as long as the (or the monitor devices 200 and 201) can obtain desired signal format information from the computer device 2. For example, a serial interface such as RS-232C, and a DDC (Display Data Channel) which is an interface for transmitting display information.
l), IrDA (Infrared Data Assoc) using infrared signal
iation) and various interfaces can be used.

The content of the signal format data transmitted from the computer device 2 to the monitor device 1, 200 or 201 via the communication cable 4 is not limited to the data described above. That is, other information may be transmitted from the computer device 2 as long as the information can be used for display control on the monitor device 1, 200, or 201 side.

For example, the number of dots H _act and the number of lines L _{act in} the active section of the video signal are directly transmitted from the computer device 2 to the monitor device 1, 200 or 201.
May be transmitted. Further, for example, the synchronization signal and the width of the front porch and the back porch may be transmitted from the computer device 2.

Further, the notification frequency of the signal format data from the computer device 2 to the monitor device 1, 200 or 201 is displayed on the computer device 2 when the power of the computer device 2 or the monitor device 1, 200 or 201 is turned on, for example. This can be done only when notification is required, such as when the resolution is changed. The present invention is not limited to this, and it is also possible to always output from the computer device 2. Further, the monitor device 1, 200, or 201 may request the computer device 2 for signal format data via the communication cable 4.

The video signal input to the monitor device is not limited to an analog RGB signal, but may be a digital video signal such as an LVDS signal. In this case, the A / D converter 11 in the first and second embodiments can be omitted. In the third embodiment, the monitoring device 201
, It is necessary to provide a D / A converter.

Further, in the above-described flowcharts shown in FIGS. 3 and 7, the order of processing may be different as long as desired display control is possible.

[0087]

As described above, according to the present invention, signal format information of a video signal is transmitted from a computer device to a monitor device, and the monitor device receives the transmitted signal format information, The display size and display position of the video signal are controlled based on the received signal format information. Therefore, in the monitor device, an expensive video detection circuit or a large-capacity EEPRO
M and the like, and no matter what kind of signal format the video signal is supplied from the computer device to the monitor device, the image based on the video signal supplied from the computer device is always substantially at the center of the screen, substantially. There is an effect that it can be displayed in a full size.

According to the first and second embodiments of the present invention, an LC using an LCD as a display device
An analog video signal input from a D monitor
In a monitor device that performs D conversion, there is an effect that a dot shift due to a mismatch between dot clocks does not occur.

Further, even when a white window is displayed on a black background, there is an effect that a screen can be displayed with an accurate image size and image position.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an example of a monitor device according to a first embodiment.

FIG. 2 is a block diagram schematically illustrating a configuration of an example of a computer device.

FIG. 3 is a flowchart of an example of a display setting process according to the first embodiment;

FIG. 4 is a block diagram illustrating a configuration of an example of a monitor device according to a second embodiment;

FIG. 5 is a block diagram illustrating a configuration of an example of a monitor device according to a third embodiment.

FIG. 6 is a principle diagram illustrating a method of controlling an image size and an image position displayed on a display unit.

FIG. 7 is a flowchart illustrating an example of a display control process according to a third embodiment;

FIG. 8 is a block diagram illustrating a configuration of an example of a conventional multi-sync monitor.

FIG. 9 is a schematic diagram schematically illustrating an example of an input video signal, a horizontal synchronization signal, and a vertical synchronization signal.

FIG. 10 is an enlarged schematic diagram showing one horizontal synchronization section indicated by a horizontal synchronization signal.

FIG. 11 is a flowchart of an example of a process for setting an A / D converter and a resolution converter.

FIG. 12 is a schematic diagram illustrating an example of a screen on which a video detection unit does not operate normally.

[Explanation of symbols]

1, 200, 201 monitor device, 2 computer device, 10 A / D converter, 11 frequency converter, 12 communication unit, 13 resolution conversion Unit, 14 CPU, 15 memory, 16
Operation unit, 17 ... LCD display unit, 18 ... E
EPROM, 30 ... Video amplifier, 31 ... Deflection yoke DY, 32 ... Display unit by CRT, 33 ...
・ Deflection circuit

Claims (16)

[Claims] 1. A display control method for a display device capable of displaying video signals of a plurality of signal formats, wherein information indicating a signal format of a video signal supplied to the display device is notified to the display device. A display control method for controlling the display of the video signal based on the notified information indicating the signal format. 2. The display control method according to claim 1, wherein the information indicating the signal format is display position information of the video signal with respect to a horizontal synchronization signal. 3. The display control method according to claim 1, wherein the information indicating the signal format is dot clock information of the video signal. 4. The display control method according to claim 1, wherein the information indicating the signal format is information indicating a display size of the video signal. 5. A display device capable of displaying video signals of a plurality of signal formats, a display means for displaying an input video signal, a communication means for receiving information indicating a signal format of the video signal, and the communication means A display control means for controlling display by the display means based on information indicating the signal format obtained by the means. 6. The display device according to claim 5, wherein the information indicating the signal format is display position information of the video signal with respect to a horizontal synchronization signal. 7. The display device according to claim 5, wherein the information indicating the signal format is dot clock information of the video signal. 8. The display device according to claim 5, wherein the information indicating the signal format is information indicating a display size of the video signal. 9. The display device according to claim 5, wherein said communication means uses a USB as an interface. 10. A display method capable of displaying video signals of a plurality of signal formats, a display step of displaying an input video signal, a communication step of receiving information indicating a signal format of the video signal, A display control step of controlling display in the display step based on information indicating the signal format obtained in the communication step. 11. An information processing apparatus capable of outputting a video signal, comprising: a signal format acquisition unit for acquiring information indicating a signal format of a video signal to be output from the inside; A communication means for notifying a display device on which the video signal is displayed of information indicating a signal format. 12. The information processing apparatus according to claim 11, wherein the information indicating the signal format is display position information of the video signal with respect to a horizontal synchronization signal. 13. The information processing apparatus according to claim 11, wherein the information indicating the signal format is dot clock information of the video signal. 14. The information processing apparatus according to claim 11, wherein the information indicating the signal format is information indicating a display size of the video signal. 15. The information processing apparatus according to claim 11, wherein said communication means uses a USB as an interface. 16. A display device control method for controlling a display device on which an output video signal is displayed, wherein a signal format obtaining step for obtaining information indicating a signal format of the output video signal from the inside, A communication step of notifying the information indicating the signal format acquired in the format acquisition step to a display device on which the video signal is displayed.