JP2002022800A - Lsi testing device and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain accurate information for the internal condition of an LSI. SOLUTION: This LSI testing device having a built-in internal scanning circuit for outputting an internal register value via a scanning path to the outside comprises system clock generating means for generating a system clock to be supplied to the LSI, fetching means for fetching the internal register value via the scanning path with the supply of the system clock, collecting means for collecting an external pin value for the LSI with the supply of the system clock, setting means for setting the stopping conditions of a test for the LSI, and control means for controlling the system clock generating means, the fetching means and the collecting means in accordance with the stopping conditions set by the setting means to control the operation of the internal scanning circuit and obtain information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI test apparatus having an internal scan circuit for outputting an internal register value to the outside via a scan path, and a method therefor.

[0002]

2. Description of the Related Art Conventionally, in the development of an LSI, in order to eliminate a bug and obtain a high-quality LSI, a computer simulation is performed to thoroughly check a function and a timing is verified. In order to run a test pattern.

[0003] As described above, for failure detection, although techniques for ensuring sufficient quality, such as scan tests, are in place, there are cases where failures due to mistakes in logic synthesis cannot be found in functional tests. There is a problem that an inspection error and an inspection omission occur due to a manual operation of a person involved.

On the other hand, when investigating a defect that has occurred in an actual device, it is necessary to know the internal state of the LSI at the time when the defect has occurred. When there is a register, a method of determining the internal state from the register is adopted.

[0005]

However, in the related art, information that can be obtained by investigating the internal state of the LSI in elucidating the cause due to the occurrence of a defect in the LSI is limited, and the cause cannot be properly elucidated. There was a problem.

The present invention relates to a conventional LSI as described above.
It is an object of the present invention to provide an LSI test apparatus and method capable of appropriately obtaining information on the internal state of the LSI from the LSI.

[0007]

An LSI test apparatus according to the present invention is an LSI test apparatus having an internal scan circuit for outputting an internal register value to the outside via a scan path. System clock generating means for generating a clock, extracting means for extracting the internal register value via the scan path in response to the supply of the system clock, and collecting external pin values of the LSI in response to the supply of the system clock Collecting means for setting, a setting means for setting test conditions relating to the LSI, and controlling the system clock generating means, the extracting means and the collecting means based on the test conditions set by the setting means to perform the internal scan. Control means for controlling the operation of the circuit to obtain information. . This makes it possible to collect the internal register value and the external pin value of the LSI in accordance with the supply of the system clock.

[0008] An LSI test apparatus according to the present invention is characterized in that it comprises storage means for storing a predetermined amount of information obtained by the control means. This eliminates the need for a huge information file.

An LSI test apparatus according to the present invention includes a preset unit for presetting the LSI based on an internal register value obtained by the control unit. Thus, it is possible to test the LSI from the preset state.

An LSI test method according to the present invention is directed to an LSI test method including an internal scan circuit for outputting an internal register value to an external device via a scan path.
Setting a test condition for the LSI, generating a system clock to be supplied to the LSI, and changing the internal register value according to the supply of the system clock until the set test condition is satisfied. A second step of extracting via a scan path and collecting external pin values of the LSI. As a result, it is possible to obtain the internal register value and the external pin value of the LSI according to the supply of the system clock.

The method for testing an LSI according to the present invention is characterized in that it comprises a step of storing only a predetermined amount of information obtained in the second step. As a result, information can be obtained without requiring a huge information file.

An LSI test method according to the present invention has a second
Of internal register value and LS in step
Collecting the external pin value of I at every predetermined system clock, and presetting the LSI based on the already obtained internal register value when a set condition is reached; It is characterized in that a value is taken out and an external pin value of the LSI is collected for each system clock. This shortens the time required to reach the file output stop condition,
It is possible to obtain information in a state before the stop condition from the preset state for each system clock.

An LSI test method according to the present invention comprises:
In this step, a plurality of test conditions are set, and the process is repeated until each test condition is satisfied. Thereby, information can be obtained by setting a plurality of test conditions.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An LSI test apparatus and method according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same components are denoted by the same reference numerals, and redundant description will be omitted. FIG. 1 shows a configuration of a test apparatus 9 for testing an LSI 1 including a two-phase clock type internal scan circuit that outputs an internal register value to the outside via a scan path.

The test apparatus 9 switches from the normal mode to the scan mode for each system clock of the LSI 1 and reads out the values of the registers in the LSI 1 to the outside via the scan path. The internal scan circuit of the LSI 1 is a circuit often used for detecting a failure test. The scan test using the internal scan circuit includes a parallel mode and a serial mode. Here, a serial mode in which each register value is sequentially shifted through a scan path is used.

After switching the LSI 1 to the scan mode, the test apparatus 9 supplies the same number of scan clocks as the number of registers to be read out contained in the LSI 1 from the scan clock generator 15 to the LSI 1, and the scan output terminal 7 The value output from the data buffer 11
Are sequentially stored. The read values are sequentially returned to the scan input terminal 5, and when all the values of the registers extracted from the LSII have been completely returned, the mode is returned from the scan mode to the normal mode. At the same time, the state (value) of the pin is taken out from the input / output pin 4 of the LSI 1 and stored in the buffer 11. The information obtained in the data buffer 11 is stored in the VCD file 8 every system clock cycle.

An external circuit 2 necessary for operating in the normal mode is connected to the LSI 1. The test device 9 includes
A system clock generator 13 for generating a system clock 3 applied to the LSI 1 is provided. In this example, the system clock generator 13 is provided in the test device 9, but may be provided outside the test device 9.

In addition to the system clock generator 13, a controller 10 for controlling each unit,
The circuit includes signal detectors / outputters 12 and 14 for detecting signals and outputting signals between the data buffer 11 for storing data, the LSI 1, and the like, and further includes a scan clock generator 15.

The data in the data buffer 11 is output to the VCD file 8 and further taken into the computer 27. Between the external circuit 2 and the input / output pin 4 of the LSI 1,
A connection state switch 16 for connecting or disconnecting the external circuit 2 to the input / output pin 4 is provided.

The controller 10 of the test apparatus 9 controls the conditions (for example, the state of the internal register of the LSI 1, the state of the input / output pin 4,
Control is performed so that data is obtained from the LSI 1 until the number of elapsed clocks of the system clock 3) is satisfied. The test apparatus 9 has a first mode in which the data buffered in the data buffer 11 is transmitted as data 19 as it is. The operation when the first mode is selected will be described below.

Since the LSI 1 transitions to the next state every time the system clock 3 advances by one clock, the controller 10 temporarily stops the system clock generator 13 by the control signal 20. Then, the controller 10
In order to operate the SI1 in the scan mode, the scan clock generator 15 is controlled by the control signal 21 and the scan clock 6 is supplied to the LSI1.

In the above description, the number of clocks of the scan clock 6 given to the LSI 1 is the same as the number of registers connected to the scan path of the LSI 1. During the scan operation, the value of each register is output as the scan output 7 every clock cycle in which the scan clock 6 is sequentially advanced.

The signal detector / output unit 14 sends the value of each register relating to the above-mentioned scan output 7 to the controller 10 as data 25 and also outputs L as the scan input 5
Return to SI1. Accordingly, the state of the internal register of the LSI 1 is restored to the state before the shift operation is performed when the shift operation by the clock corresponding to each register number is completed.

The signal detector / outputter 12 captures the state of an external pin, which is the value of the input / output pin 4 of the LSI 1, for each system clock, and sends this to the controller 10 as data 23. The controller 10 accumulates the value sent from the signal detection / output unit 12 and the value sent from the signal detection / output unit 14 as data 18 in the data buffer 11 for each system clock. In the first mode, as described above, the data stored in the data buffer 11 is the data 1 as it is.
9 is sent to the VCD file 8.

The controller 10 determines the state of the internal register of the LSI 1, the state of the input / output pin 4, and the number of elapsed clocks of the system clock 3 every system clock cycle.
It is detected whether the stop condition matches the stop condition set by the user. If the stop condition is matched, the supply of the scan clock 6 is stopped to stop the test operation, and the output to the VCD file 8 is stopped.

The computer 27 takes in the data of the VCD file 8 and confirms the data and checks the contents.
The evaluation of I1 is performed.

According to the first mode, when the operation for a long time is performed until the condition for stopping the output to the VCD file 8 is reached, the data of the VCD file 8 becomes enormous. That is, a VCD file 8 having a large capacity is required. Therefore, the test apparatus 9 has a second mode for erasing data in the data buffer 11 after a predetermined period.

The setting of the second mode and the setting of the predetermined period (the number of system clocks or the time) can be set by the computer 27, for example. The controller 10 receiving these settings performs a scan operation while erasing data in the data buffer 11 after a predetermined period set by the control signal 17. In the other parts, while continuing the operation in the same manner as the first mode, when the timing of the stop condition comes, the controller 10
Sends the data in the data buffer 11 to the VCD file 8 by the control signal 17. Other parts are the first
Mode.

The test apparatus 9 is set to perform an operation of switching from the normal mode to the scan mode and reading the information on the internal state of the LSI 1 in order to shorten the time until the stop condition of the output to the VCD file 8 is reached. And a third mode that is performed only for each system clock. This mode is to execute together with the second mode. The setting of the third mode, the setting of the data erasing period of the data buffer 8, and the setting of the sampling period of the system clock can be performed by the computer 27, for example.

According to the third mode, while the operation of switching from the normal mode to the scan mode and reading out the information of the internal state of the LSI 1 is continued only at every set system clock, when the stop condition is satisfied, In the buffer 11, data from several previous system clocks remains.

The controller 10 reads out the data stored in the data buffer 11 from the oldest data as the data 18 using the control signal 17, and reproduces the internal state of the LSI 1 at the system clock.

That is, the controller 10 detects the signal
By controlling the output unit 14 and the scan clock generator 15,
A preset is performed to return the past register values obtained above from the scan input 5 of the LSI 1 via the scan path to the LSI 1.

When the preset is completed, the operation in the first mode is performed until the preset stop condition is satisfied, and the value sent from the signal detection / output unit 12 and the Signal detection / output unit 14
Is stored in the data buffer 11 as data 18.

At this time, since the external circuit 2 cannot reproduce the past state, the controller 10 detects the signal
The connection state switch 16 is controlled from the control signal 26 via the output unit 12, the external circuit 2 is disconnected from the input / output pin 4, and the signal detection / output unit 12 is set to L via the input / output pin 4.
A past external pin value (information) is supplied to SI1 for each system clock. Other operations are the same as in the second mode.

Further, the test apparatus 9 has a fourth mode. The fourth mode is basically the same as the second mode, but a plurality of stop conditions can be set. Thus, once the stop condition is satisfied, the output to the VCD file 8 is performed, and then the LSI test is further performed.
When the next stop condition is satisfied, output to the VCD file 8 is performed. Hereinafter, the LSI test is similarly executed until all the stop conditions are satisfied.

Further, a plurality of stop conditions can be set for the third mode. In this way, the third mode is repeated a plurality of times for each stop condition,
It is possible to obtain the data of the file 8 and perform the analysis.

Next, FIG. 2 shows a configuration of a test apparatus 9A for testing an LSI 1A having a built-in one-phase clock type internal scan circuit for outputting an internal register value to the outside via a scan path.

In the test apparatus 9A, an enable signal generator 15A is provided instead of the scan clock generator 15 of the test apparatus 9 shown in FIG. Controller 1
0 controls the enable signal generator 15A with the control signal 21 to operate the LSI 1A in the scan mode, and supplies the enable signal 6A to the LSI 1. Then, the internal register value can be output by setting the number of clocks of the system lock 3 given to the LSI 1A to be the same as the number of registers connected to the scan path of the LSI 1A. Other configurations are the same as those of the test device 9.

That is, the test device 9A stops the advance of the system clock 3 and scans with the scan clock 7, whereas the test device 9A outputs the enable signal 6A.
Is used to set the scan mode, and scanning is performed by the system clock 3 step by step.

The test apparatus 9A can appropriately obtain data for analyzing the LSI 1A having a built-in one-phase clock type internal scan circuit.

As described above, when investigating the internal state of the LSI, it is possible to obtain a VCD file output from the LSI itself as an effective means for confirming the operation in computer simulation. This makes it possible to check the state inside the LSI with good visibility as in the case of computer simulation.
The time required to investigate one operation can be reduced. Also, L
Even when the SI needs to operate for a long time, it is possible to complete the test in a short time and with few resources by efficiently outputting the VCD file.

[0042]

As described above, according to the LSI test apparatus of the present invention, it is possible to collect the internal register value and the external pin value of the LSI in accordance with the supply of the system clock, and to efficiently develop the LSI. Can proceed.

Further, according to the LSI test apparatus of the present invention, since the storage means for storing a predetermined amount of information obtained by the control means is provided, an enormous information file is not required.

Further, according to the LSI test apparatus of the present invention, the LSI test is performed based on the internal register value obtained by the control means.
Is provided, the LSI can be tested from the preset state.

According to the LSI test method of the present invention, the internal register value and the external pin value of the LSI can be obtained according to the supply of the system clock.
I can proceed efficiently.

According to the LSI test method of the present invention, since only a predetermined amount of the obtained information is stored, it is possible to obtain information without requiring a huge information file.

According to the LSI test method of the present invention, the step of presetting the LSI based on the already obtained internal register value, and after this preset, extracting the internal register value and setting the external pin value of the LSI. Since the collection is performed for each system clock, the time until the stop condition is reached is reduced, and information in a state before the stop condition is obtained can be obtained for each system clock from the preset state. It is possible to collect information.

According to the LSI test method of the present invention, a plurality of test conditions are set in the first step, and the process is repeated until each test condition is satisfied.
Information can be obtained by setting a plurality of stop conditions.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an LSI test apparatus according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an LSI test apparatus according to a second embodiment of the present invention.

[Explanation of symbols]

1, 1A LSI 2 External circuit 8 VCD file 9, 9A Test device 10 Controller 11 Data buffer 12, 14 Signal detection / output unit 13 System clock generator 15 Scan clock generator 15A enable signal generator 16 Connection state switch

Claims (7)

[Claims] 1. An LSI test apparatus having an internal scan circuit for outputting an internal register value to an external device via a scan path, comprising: a system clock generating means for generating a system clock to be supplied to the LSI; Extraction means for extracting the internal register value via the scan path in response to the supply, collection means for collecting the external pin value of the LSI in response to the supply of the system clock, and setting for setting test conditions for the LSI Means for controlling the system clock generating means, the extracting means, and the collecting means to control the operation of the internal scan circuit to obtain information based on the test conditions set by the setting means; and An LSI test apparatus comprising: 2. The LSI test apparatus according to claim 1, further comprising storage means for storing a predetermined amount of information obtained by said control means. 3. The LS according to claim 1, further comprising a preset unit that presets the LSI based on an internal register value obtained by the control unit.
I test equipment. 4. A test method for an LSI having an internal scan circuit that outputs an internal register value to the outside via a scan path, wherein: a first step of setting test conditions for the LSI; and a system for supplying the LSI with the test condition. A second step of generating a clock, extracting the internal register value via the scan path in accordance with the supply of the system clock, and collecting external pin values of the LSI until the set test condition is satisfied; An LSI test method, comprising: 5. The LSI test method according to claim 4, further comprising the step of storing only a predetermined amount of information obtained in said second step. 6. The internal register value is fetched in a second step and the external pin value of the LSI is collected at every predetermined system clock. When a set condition is reached, the internal register value is obtained based on the already obtained internal register value. 5. The LIS test method according to claim 4, wherein: the step of presetting the LSI; and, after the presetting, extracting the internal register value and collecting the external pin value of the LSI for each system clock. 7. The LSI test method according to claim 5, wherein a plurality of test conditions are set in the first step, and the process is repeated until each test condition is satisfied.