JP2002018705A - Method of double-face simultaneous polishing for semiconductor wafer - Google Patents

Method of double-face simultaneous polishing for semiconductor wafer

Info

Publication number
JP2002018705A
JP2002018705A JP2000211951A JP2000211951A JP2002018705A JP 2002018705 A JP2002018705 A JP 2002018705A JP 2000211951 A JP2000211951 A JP 2000211951A JP 2000211951 A JP2000211951 A JP 2000211951A JP 2002018705 A JP2002018705 A JP 2002018705A
Authority
JP
Japan
Prior art keywords
polishing
semiconductor wafer
abrasive grains
double
mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000211951A
Other languages
Japanese (ja)
Inventor
Chikafumi Komata
慎史 小又
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2000211951A priority Critical patent/JP2002018705A/en
Publication of JP2002018705A publication Critical patent/JP2002018705A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method of double-face simultaneous polishing for a semiconductor wafer, considerably shortening working time for polishing the semiconductor wafer and remarkably improving the quality, yield and productivity of the semiconductor wafer polished into a mirror finished surface obtained by the polishing. SOLUTION: In this method for double-face simultaneous polishing of the semiconductor wafer, the semiconductor wafer is set between an upper surface table and a lower surface table of a mirror finished surface polishing device provided with the upper surface table with abrasive cloth bonded to the lower face side, and the lower surface table with abrasive cloth bonded to the upper face side, and the upper surface table and the lower surface table are rotated reversely to each other while supplying the semiconductor wafer with a polishing solution containing abrasive grains, to simultaneously polish both faces of the semiconductor wafer. Double-face simultaneous polishing is performed being divided in the former half double-face simultaneous polishing performed with a polishing solution containing abrasive grains large in grain diameter and the latter half double-face simultaneous polishing performed with a polishing solution containing abrasive grains small in grain diameter.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体ウエーハの両
面同時ポリッシュ方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simultaneously polishing both surfaces of a semiconductor wafer.

【0002】[0002]

【従来の技術】半導体デバイスはベースの半導体ウエー
ハの表面に微細な回路パータンを施して成るものであ
る。
2. Description of the Related Art A semiconductor device is obtained by applying a fine circuit pattern to a surface of a base semiconductor wafer.

【0003】この半導体デバイスの集積度は年々上がる
傾向にあり、且つその回路配線も益々細線化の傾向にあ
る。
The degree of integration of this semiconductor device is increasing year by year, and its circuit wiring is also becoming thinner.

【0004】半導体ウエーハの表面に高度に微細化した
回路パータンを施すためにはその表面が高度な平坦度を
持ち、且つ高度な鏡面を持つものでなければならない。
In order to apply a highly miniaturized circuit pattern to the surface of a semiconductor wafer, the surface must have a high degree of flatness and a high degree of mirror surface.

【0005】さて、半導体ウエーハの平坦度を上げ、且
つ鏡面とするポリッシュ方法として2段階ポリッシュ方
法が行われている。この2段階ポリッシュ方法とは1次
ポリッシュと2次ポリッシュとの2段階に行うポリッシ
ュ方法である。
[0005] A two-stage polishing method has been used as a polishing method for increasing the flatness of a semiconductor wafer and making it a mirror surface. The two-stage polishing method is a polishing method performed in two stages of a primary polishing and a secondary polishing.

【0006】即ち、1次ポリッシュでは半導体ウエーハ
を高度な平坦度にするためにメカノケミカル研磨する。
また、2次ポリッシュでは半導体ウエーハの表面を高品
質鏡面とするためケミカル研磨する。
That is, in the first polishing, the semiconductor wafer is subjected to mechanochemical polishing in order to obtain a high degree of flatness.
In the second polishing, chemical polishing is performed to make the surface of the semiconductor wafer a high quality mirror surface.

【0007】(1次ポリッシュ)まず、1次ポリッシュ
について説明する。
(Primary polishing) First, the primary polishing will be described.

【0008】1次ポリッシュでは半導体ウエーハの平坦
度を上げるためにその半導体ウエーハの両面を同時にメ
カノケミカルポリッシュする。
In the first polishing, both surfaces of the semiconductor wafer are simultaneously subjected to mechanochemical polishing in order to increase the flatness of the semiconductor wafer.

【0009】図1は鏡面研磨装置に半導体ウエハを装着
し、その両面を同時にメカノケミカルポリッシュする様
子を示した部分模式断面説明図である。
FIG. 1 is a partial schematic cross-sectional explanatory view showing a state in which a semiconductor wafer is mounted on a mirror polishing apparatus and both surfaces thereof are simultaneously subjected to mechanochemical polishing.

【0010】図1において1は上定盤、2は下定盤、3
は研磨布、4はキャリア、5は研磨する半導体ウエー
ハ、6はサンギア、7はインターナルギア、8は研磨液
供給孔である。
In FIG. 1, 1 is an upper surface plate, 2 is a lower surface plate, and 3 is an upper surface plate.
Is a polishing cloth, 4 is a carrier, 5 is a semiconductor wafer to be polished, 6 is a sun gear, 7 is an internal gear, and 8 is a polishing liquid supply hole.

【0011】図1から分かるように鏡面研磨装置はその
上側に上定盤1、また下側に下定盤2が設置されてい
る。この上定盤1の下面側には研磨布3が接着されてお
り、また下定盤2の上面側にも研磨布3が接着されてい
る。上定盤1の下面側に接着されている研磨布3と下定
盤2の上面側に接着されている研磨布3との間には、キ
ャリア4と研磨する半導体ウエーハ5とが保持されてい
る。そして図示しない駆動機構により上定盤1と下定盤
2とはそれぞれ互いに逆方向に回転し、更にキャリア4
はサンギア6とインターナルギア7との回転数の違いに
より自公転(遊星運動)するように構成されている。半
導体ウエーハ5には上定盤1を通した研磨液供給孔8か
ら研磨液が供給されるようになっている。
As can be seen from FIG. 1, the mirror polishing apparatus has an upper surface plate 1 on the upper side and a lower surface plate 2 on the lower side. A polishing cloth 3 is bonded to the lower surface of the upper platen 1, and the polishing cloth 3 is bonded to an upper surface of the lower platen 2. A carrier 4 and a semiconductor wafer 5 to be polished are held between the polishing cloth 3 bonded to the lower surface of the upper platen 1 and the polishing cloth 3 bonded to the upper surface of the lower platen 2. . The upper platen 1 and the lower platen 2 rotate in directions opposite to each other by a driving mechanism (not shown).
Is configured to revolve on its own (planetary motion) due to the difference in the number of revolutions between the sun gear 6 and the internal gear 7. A polishing liquid is supplied to the semiconductor wafer 5 from a polishing liquid supply hole 8 passing through the upper platen 1.

【0012】1次ポリッシュでは半導体ウエーハ5の高
平坦度を上げるために研磨布として硬質不織布製研磨布
を用い、また研磨液として砥粒を含有した化学研磨液を
用い、それによってメカノケミカルポリシュするように
なっている。
In the first polishing, a hard non-woven cloth polishing cloth is used as a polishing cloth in order to increase the high flatness of the semiconductor wafer 5, and a chemical polishing liquid containing abrasive grains is used as a polishing liquid, thereby performing mechanochemical polishing. It has become.

【0013】(2次ポリッシュ)次に、2次ポリッシュ
について説明する。
(Secondary Polishing) Next, the secondary polishing will be described.

【0014】1次ポリッシュにより両面をメカノケミカ
ルポリッシュされた半導体ウエーハ5は、回路パータン
を施す側の片面側を高品質鏡面にするための2次ポリッ
シュを行うようになっている。
The semiconductor wafer 5, both surfaces of which are mechanochemically polished by the primary polishing, is subjected to a secondary polishing for making a high-quality mirror surface on one side on which a circuit pattern is applied.

【0015】この2次ポリッシュでは、まず1次ポリッ
シュにより両面をメカノケミカルポリシュされた半導体
ウエーハ5を図示しない研磨プーレートに接着させ、そ
れから片面方式のポリッシュを行うようになっている。
In this secondary polishing, first, a semiconductor wafer 5 whose both surfaces are mechanochemically polished by the primary polishing is adhered to a polishing plate (not shown), and then a single-side polishing is performed.

【0016】2次ポリッシュでは半導体ウエーハ5の片
面側を高品質鏡面にするために研磨布として発泡層を有
する軟質不織布製研磨布を用い、また研磨液として砥粒
を含有しない化学研磨液を用い、それによってケミカル
ポリッシュするようになっている。
In the second polishing, a polishing cloth made of a soft nonwoven fabric having a foamed layer is used as a polishing cloth in order to make one side of the semiconductor wafer 5 a high quality mirror surface, and a chemical polishing liquid containing no abrasive grains is used as a polishing liquid. , So that they are chemically polished.

【0017】この種のポリッシュ作業コストは半導体ウ
エーハ5の除去速度、ポリッシュ作業時間、研磨液の使
用量等が大きな因子となる。即ち、ポリッシュ作業コス
トは半導体ウエーハ5の除去速度が早く、ポリッシュ作
業時間が短く、且つ研磨液の使用量が少ない程低減する
ことができる。
The polishing operation cost of this type is largely affected by the removal speed of the semiconductor wafer 5, the polishing operation time, the amount of polishing liquid used, and the like. That is, the polishing operation cost can be reduced as the removal speed of the semiconductor wafer 5 is increased, the polishing operation time is shorter, and the amount of the polishing liquid used is smaller.

【0018】さて、1次ポリッシュにおいて半導体ウエ
ーハ5の除去速度を上げ、そのポリッシュ作業時間を短
縮するにはメカニカル研磨性を高めることが効果的であ
る。ここにおいて1次ポリッシュのメカニカル研磨性を
高めるには研磨液に含まれている砥粒を大径の砥粒とす
ることが効果的である。
In order to increase the removal speed of the semiconductor wafer 5 in the primary polishing and to shorten the polishing operation time, it is effective to enhance the mechanical polishing property. Here, in order to enhance the mechanical polishing property of the primary polish, it is effective to make the abrasive grains contained in the polishing liquid large abrasive grains.

【0019】[0019]

【発明が解決しようとする課題】しかしながら大径の砥
粒を含有する研磨液を用いて半導体ウエーハ5を1次ポ
リッシュしたときには目的通り半導体ウエーハの除去速
度が上がり、且つポリッシュ作業時間を大幅に短縮する
ことができるが、その半面半導体ウエーハ5にはスクラ
ッチ不良が多発すると共に潜在ダメージ要因が蓄積し、
その結果鏡面研磨半導体ウエーハの品質、歩留及び生産
性の低下を招くという難点があった。
However, when the semiconductor wafer 5 is primarily polished using a polishing liquid containing large-diameter abrasive grains, the removal speed of the semiconductor wafer is increased as intended, and the polishing operation time is greatly reduced. However, the semiconductor wafer 5 has a large number of scratch defects and a potential damage factor is accumulated in the semiconductor wafer 5,
As a result, there is a problem that the quality, yield and productivity of the mirror-polished semiconductor wafer are reduced.

【0020】本発明はかかる点に立って為されたもので
あって、その目的とするところは前記した従来技術の欠
点を解消し、半導体ウエーハのポリッシュ作業時間を大
幅に短縮することができ、しかもそのポリッシュにより
得られる鏡面研磨半導体ウエーハの品質、歩留及び生産
性を顕著に向上することができる半導体ウエハの両面同
時ポリッシュ方法を提供することにある。
The present invention has been made in view of such a point, and an object of the present invention is to solve the above-mentioned disadvantages of the prior art and to greatly reduce the polishing time of the semiconductor wafer. Moreover, it is an object of the present invention to provide a method for simultaneously polishing both surfaces of a semiconductor wafer, which can significantly improve the quality, yield and productivity of a mirror-polished semiconductor wafer obtained by the polishing.

【0021】[0021]

【課題を解決するための手段】本発明の要旨とするとこ
ろは、下面側に研磨布が接着されている上定盤と上面側
に研磨布が接着されている下定盤とを具備した鏡面研磨
装置の前記上定盤と前記下定盤との間に半導体ウエーハ
をセットし、且つ該半導体ウエーハへ砥粒を含有した研
磨液を供給しながら前記上定盤と前記下定盤とを互いに
逆回転させることにより前記半導体ウエーハの両面を同
時にポリッシュする半導体ウエーハの両面同時ポリッシ
ュ方法において、該両面同時ポリッシュを粒径が大きい
砥粒を含有した研磨液で行う前半両面同時ポリシュと、
粒径が小さい砥粒を含有した研磨液で行う後半両面同時
ポリッシュとに別けて行うことを特徴とする半導体ウエ
ーハの両面同時ポリッシュ方法にある。
SUMMARY OF THE INVENTION The gist of the present invention is to provide a mirror polishing machine comprising an upper surface plate having a polishing cloth adhered to a lower surface and a lower surface plate having a polishing cloth adhered to an upper surface. A semiconductor wafer is set between the upper stool and the lower stool of the apparatus, and the upper stool and the lower stool are rotated in opposite directions while supplying a polishing liquid containing abrasive grains to the semiconductor wafer. In the method for simultaneously polishing both surfaces of the semiconductor wafer by simultaneously polishing both surfaces of the semiconductor wafer, the first half simultaneous double polishing in which the double-side simultaneous polishing is performed with a polishing liquid containing abrasive grains having a large particle diameter,
The present invention provides a method for simultaneously polishing both surfaces of a semiconductor wafer, wherein the polishing is performed separately from the latter half simultaneous polishing performed with a polishing liquid containing abrasive grains having a small particle diameter.

【0022】本発明において前半両面同時ポリッシュに
用いる研磨液に含有する砥粒の粒径をa(μm)、後半
両面同時ポリッシュに用いる研磨液に含有する砥粒の粒
径をb(μm)としたとき、前記前半両面同時ポリッシ
ュに用いる研磨液に含有する砥粒は、 3b≦a≦6b…………(1式) を満足する粒径の砥粒であることが好ましい。
In the present invention, the particle size of the abrasive grains contained in the polishing liquid used for the first half simultaneous polishing is a (μm), and the particle diameter of the abrasive grains contained in the polishing liquid used for the second half simultaneous polishing is b (μm). In this case, it is preferable that the abrasive particles contained in the polishing liquid used for the first-half double-sided simultaneous polishing be abrasive particles having a particle diameter satisfying 3b ≦ a ≦ 6b (1).

【0023】これは、3b≦aのときにはポリッシュ時
間の顕著なる短縮ができなく、逆に、a≦6bのときに
はスクラッチ不良が急激に多発するようになるからであ
る。
This is because the polishing time cannot be remarkably shortened when 3b ≦ a, and on the other hand, when a ≦ 6b, scratch failures occur rapidly and frequently.

【0024】[0024]

【発明の実施の形態】次に、本発明の半導体ウエーハの
両面同時ポリッシュ方法の一実施例を図面より説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for simultaneously polishing both surfaces of a semiconductor wafer according to the present invention will be described with reference to the drawings.

【0025】この本発明の半導体ウエーハの両面同時ポ
リッシュ方法の一実施例に用いた研磨装置、素材、研磨
条件は下記の通りである。
The polishing apparatus, materials and polishing conditions used in one embodiment of the method for simultaneously polishing both surfaces of a semiconductor wafer according to the present invention are as follows.

【0026】a.鏡面研磨装置………16B型鏡面研磨
装置(キャリア径φ40mm) b.半導体ウエーハ……外径φ4インチのGaAsウエ
ーハ c.ウエーハ除去量……50μm d.研磨液の砥粒………比較例に用いた砥粒;0.02
μmの砥粒 実施例に用いた砥粒;0.10μmの砥粒(比較例の砥
粒の5倍) (比較例1) まず、16B型鏡面研磨装置に40枚のGaAsウエー
ハをセットした。
A. Mirror surface polishing device ... 16B type mirror surface polishing device (carrier diameter φ40 mm) b. Semiconductor wafer: GaAs wafer having an outer diameter of 4 inches c. Wafer removal amount: 50 μm d. Abrasive grains of polishing liquid: abrasive grains used in comparative example: 0.02
Abrasive particles of μm Abrasive particles used in Examples; Abrasive particles of 0.10 μm (5 times as large as abrasive particles of Comparative Example) (Comparative Example 1) First, 40 GaAs wafers were set in a 16B type mirror polishing machine.

【0027】次に、粒径φ0.02μmの砥粒が含有す
る化学研磨液と硬質不織布製研磨布とを用い、16B型
鏡面研磨装置にセットしてある40枚のGaAsウエー
ハの両面除去量分50μmを1次ポリッシュした。
Next, using a chemical polishing solution containing abrasive grains having a particle size of 0.02 μm and a polishing cloth made of hard non-woven fabric, the amount of both-side removal of 40 GaAs wafers set in a 16B mirror polishing machine was measured. 50 μm was first polished.

【0028】その除去速度は0.5μm/分であった。The removal rate was 0.5 μm / min.

【0029】また、ポリッシュ時間は100分であっ
た。
The polishing time was 100 minutes.

【0030】次に、この両面ポリッシュした半導体ウエ
ーハ5の片面側を高品質鏡面にするために研磨布として
発泡層を有する軟質不織布製研磨布を用い、また研磨液
として砥粒を含有しない化学研磨液を用い、それによっ
て2次ポリッシュ(ケミカルポリッシュ)した。
Next, in order to obtain a high-quality mirror surface on one side of the double-side polished semiconductor wafer 5, a polishing cloth made of a soft non-woven fabric having a foamed layer is used as a polishing cloth, and a polishing liquid containing no abrasive grains is used. The solution was used for secondary polishing (chemical polishing).

【0031】次に、脱脂処理、洗浄処理、超純水洗浄、
乾燥処理することにより、比較例1鏡面研磨GaAsウ
エーハを得た。
Next, degreasing treatment, washing treatment, ultrapure water washing,
By performing a drying treatment, a mirror-polished GaAs wafer of Comparative Example 1 was obtained.

【0032】(比較例2)まず、16B型鏡面研磨装置
に40枚のGaAsウエーハをセットした。
(Comparative Example 2) First, 40 GaAs wafers were set in a 16B type mirror polishing apparatus.

【0033】次に、粒径φ0.10μmの砥粒が含有す
る化学研磨液と硬質不織布製研磨布とを用い、16B型
鏡面研磨装置にセットしてある40枚のGaAsウエー
ハの両面除去量分50μmを1次ポリッシュした。
Next, using a chemical polishing solution containing abrasive grains having a particle diameter of φ0.10 μm and a polishing cloth made of hard non-woven fabric, the amount of removal of both sides of 40 GaAs wafers set in a 16B mirror polishing machine was measured. 50 μm was first polished.

【0034】その除去速度は0.5μm/分であった。The removal rate was 0.5 μm / min.

【0035】また、ポリッシュ時間は100分であっ
た。
The polishing time was 100 minutes.

【0036】次に、この両面ポリッシュした半導体ウエ
ーハ5の片面側を高品質鏡面にするために研磨布として
発泡層を有する軟質不織布製研磨布を用い、また研磨液
として砥粒を含有しない化学研磨液を用い、それによっ
て2次ポリッシュ(ケミカルポリッシュ)した。
Next, a polishing cloth made of a soft non-woven fabric having a foamed layer is used as a polishing cloth in order to make one side of the semiconductor wafer 5 which has been polished on both sides a high quality mirror surface, and a chemical polishing which does not contain abrasive grains is used as a polishing liquid. The solution was used for secondary polishing (chemical polishing).

【0037】次に、脱脂処理、洗浄処理、超純水洗浄、
乾燥処理することにより、比較例2鏡面研磨GaAsウ
エーハを得た。
Next, degreasing treatment, washing treatment, ultrapure water washing,
By performing the drying treatment, a mirror-polished GaAs wafer of Comparative Example 2 was obtained.

【0038】(実施例1)まず、16B型鏡面研磨装置
に40枚のGaAsウエーハをセットした。
(Example 1) First, 40 GaAs wafers were set in a 16B type mirror polishing apparatus.

【0039】次に、粒径φ0.10μmの砥粒が含有す
る化学研磨液と硬質不織布製研磨布とを用い、GaAs
ウエーハの両面の前半除去量分25μmを両面をポリッ
シュした。
Next, using a chemical polishing solution containing abrasive grains having a particle diameter of 0.10 μm and a polishing cloth made of hard nonwoven fabric, GaAs
The both sides of the wafer were polished on both sides for the first half removal amount of 25 μm.

【0040】このときの除去速度は1.0μm/分であ
った。
The removal rate at this time was 1.0 μm / min.

【0041】次に、粒径φ0.02μmの粒径の砥粒が
含有する化学研磨液と硬質不織布製研磨布とを用い、G
aAsウエーハの後半両面除去量分25μmを一次ポリ
ッシュした。
Next, using a chemical polishing liquid containing abrasive grains having a particle diameter of 0.02 μm and a hard nonwoven polishing cloth,
A 25 μm portion of the aAs wafer, which was removed in the latter half on both sides, was subjected to primary polishing.

【0042】その除去速度は0.5μm/分である。The removal rate is 0.5 μm / min.

【0043】前半ポリッシュと後半ポリッシュとの合計
ポリッシュ時間は75分であった。この合計ポリッシュ
時間75分は比較例1のポリッシュ時間より25分短縮
された。
The total polish time of the first half polish and the second half polish was 75 minutes. This total polishing time of 75 minutes was reduced by 25 minutes from the polishing time of Comparative Example 1.

【0044】次に、この両面ポリッシュした半導体ウエ
ーハ5の片面側を高品質鏡面にするために研磨布として
発泡層を有する軟質不織布製研磨布を用い、また研磨液
として砥粒を含有しない化学研磨液を用い、それによっ
て2次ポリッシュ(ケミカルポリッシュ)した。
Next, in order to make one side of the semiconductor wafer 5 which has been polished on both sides a high quality mirror surface, a polishing cloth made of a soft non-woven fabric having a foam layer is used as a polishing cloth, and a chemical polishing containing no abrasive grains is used as a polishing liquid. The solution was used for secondary polishing (chemical polishing).

【0045】次に、脱脂処理、洗浄処理、超純水洗浄、
乾燥処理することにより、実施例1鏡面研磨GaAsウ
エーハを得た。
Next, degreasing treatment, washing treatment, ultrapure water washing,
By performing a drying treatment, a mirror-polished GaAs wafer of Example 1 was obtained.

【0046】(試験方法及び試験結果)次に、かくして
得られた比較例1の半導体ウエーハの両面同時ポリッシ
ュ方法で得られた鏡面研磨GaAsウエーハの40枚、
比較例2の半導体ウエーハの両面同時ポリッシュ方法で
得られた鏡面研磨GaAsウエーハの40枚、実施例1
の半導体ウエーハの両面同時ポリッシュ方法で得られた
鏡面研磨GaAsウエーハの40枚について、それぞれ
ポリッシュ時間の測定及び10万ルクス集光器でのスク
ラッチ有無検査とを行った。
(Test Method and Test Results) Next, forty semiconductor mirror-polished GaAs wafers obtained by the double-sided simultaneous polishing method of the semiconductor wafer of Comparative Example 1 thus obtained,
Example 1 40 mirror-polished GaAs wafers obtained by the double-sided simultaneous polishing method for the semiconductor wafer of Comparative Example 2
For 40 mirror-polished GaAs wafers obtained by the double-sided simultaneous polishing method for the semiconductor wafers, the polishing time was measured and the presence / absence of scratches was measured with a 100,000 lux collector.

【0047】比較例1の半導体ウエーハの両面同時ポリ
ッシュ方法で得られた鏡面研磨GaAsウエーハ40枚
には、スクラッチ不良が1枚も発見されなかったが、そ
の半面ポリッシュ時間が100分もかかった。
No scratch defect was found on 40 mirror-polished GaAs wafers obtained by the double-sided simultaneous polishing method of the semiconductor wafer of Comparative Example 1, but the half-side polishing time required 100 minutes.

【0048】比較例2の半導体ウエーハの両面同時ポリ
ッシュ方法で得られた鏡面研磨GaAsウエーハ40枚
の内の10枚がスクラッチ不良(不良率25%)となっ
た。しかもポリッシュ時間は100分もかかった。
Out of 40 mirror-polished GaAs wafers obtained by the double-sided simultaneous polishing method of the semiconductor wafer of Comparative Example 2, 10 of the polished GaAs wafers had defective scratches (defective rate: 25%). Moreover, the polishing time took 100 minutes.

【0049】これに対して本発明の実施例1の半導体ウ
エーハの両面同時ポリッシュ方法で得られた鏡面研磨G
aAsウエーハ40枚にはスクラッチ不良が1枚も発見
されなく、且つポリッシュ時間も75分と短かった。
On the other hand, the mirror polishing G obtained by the double-sided simultaneous polishing method for the semiconductor wafer according to the first embodiment of the present invention.
No scratch defects were found on 40 aAs wafers, and the polishing time was as short as 75 minutes.

【0050】[0050]

【発明の効果】本発明の半導体ウエーハの両面同時ポリ
ッシュ方法によれば、ポリッシュ時間を顕著に短縮でき
ると共に最終的に得られる鏡面研磨半導体ウエーハの品
質、歩留及び生産性を顕著に向上することができるもの
であり、工業上有用である。
According to the method for simultaneously polishing both surfaces of a semiconductor wafer of the present invention, the polishing time can be remarkably reduced, and the quality, yield and productivity of the mirror-polished semiconductor wafer finally obtained can be remarkably improved. And is industrially useful.

【図面の簡単な説明】[Brief description of the drawings]

【図1】鏡面研磨装置に半導体ウエーハを装着し、その
両面を同時にメカノケミカルポリッシュする様子を示し
た部分模式断面説明図である。
FIG. 1 is a partial schematic cross-sectional explanatory view showing a state where a semiconductor wafer is mounted on a mirror polishing apparatus and both surfaces thereof are simultaneously subjected to mechanochemical polishing.

【符号の説明】[Explanation of symbols]

1 上定盤 2 下定盤 3 研磨布 4 キャリア 5 研磨する半導体ウエーハ 6 サンギア 7 インターナルギア 8 研磨液供給孔 DESCRIPTION OF SYMBOLS 1 Upper surface plate 2 Lower surface plate 3 Polishing cloth 4 Carrier 5 Semiconductor wafer to be polished 6 Sun gear 7 Internal gear 8 Polishing liquid supply hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】下面側に研磨布が接着されている上定盤と
上面側に研磨布が接着されている下定盤とを具備した鏡
面研磨装置の前記上定盤と前記下定盤との間に半導体ウ
エーハをセットし、且つ該半導体ウエーハへ砥粒を含有
した研磨液を供給しながら前記上定盤と前記下定盤とを
互いに逆回転させることにより前記半導体ウエーハの両
面を同時にポリッシュする半導体ウエーハの両面同時ポ
リッシュ方法において、該両面同時ポリッシュを粒径が
大きい砥粒を含有した研磨液で行う前半両面同時ポリッ
シュと、粒径が小さい砥粒を含有した研磨液で行う後半
両面同時ポリシュとに別けて行うことを特徴とする半導
体ウエーハの両面同時ポリッシュ方法。
1. A mirror polishing apparatus comprising: an upper surface plate having a polishing cloth adhered to a lower surface thereof; and a lower surface plate having a polishing cloth adhered to an upper surface thereof. A semiconductor wafer for simultaneously polishing both surfaces of the semiconductor wafer by rotating the upper platen and the lower platen in opposite directions while setting a semiconductor wafer on the semiconductor wafer and supplying a polishing liquid containing abrasive grains to the semiconductor wafer. In the double-sided simultaneous polishing method, the two-sided simultaneous polishing in which the two-sided simultaneous polishing is performed with a polishing liquid containing abrasive grains having a large particle diameter, and the second-half simultaneous polishing in which the two-sided simultaneous polishing is performed with a polishing liquid containing abrasive particles having a small particle diameter A method for simultaneously polishing both surfaces of a semiconductor wafer, which is performed separately.
【請求項2】前半両面同時ポリッシュに用いる研磨液に
含有する砥粒の粒径をa(μm)、後半両面同時ポリッ
シュに用いる研磨液に含有する砥粒の粒径をb(μm)
としたとき、前記前半両面同時ポリッシュに用いる研磨
液に含有する砥粒は、 3b≦a≦6b…………(1式) を満足する粒径の砥粒であることを特徴とする請求項1
記載の半導体ウエーハの両面同時ポリッシュ方法。
2. The particle size of the abrasive grains contained in the polishing liquid used for the first half simultaneous polishing is a (μm), and the particle size of the abrasive grains contained in the polishing liquid used for the second half simultaneous polishing is b (μm).
Wherein the abrasive grains contained in the polishing liquid used for the first half simultaneous polishing are abrasive grains having a particle diameter satisfying 3b ≦ a ≦ 6b (1 formula). 1
A method for simultaneously polishing both surfaces of a semiconductor wafer as described in the above.
JP2000211951A 2000-07-07 2000-07-07 Method of double-face simultaneous polishing for semiconductor wafer Withdrawn JP2002018705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000211951A JP2002018705A (en) 2000-07-07 2000-07-07 Method of double-face simultaneous polishing for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000211951A JP2002018705A (en) 2000-07-07 2000-07-07 Method of double-face simultaneous polishing for semiconductor wafer

Publications (1)

Publication Number Publication Date
JP2002018705A true JP2002018705A (en) 2002-01-22

Family

ID=18707947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000211951A Withdrawn JP2002018705A (en) 2000-07-07 2000-07-07 Method of double-face simultaneous polishing for semiconductor wafer

Country Status (1)

Country Link
JP (1) JP2002018705A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008004441A1 (en) 2007-02-09 2008-08-14 Sumitomo Electric Industries, Ltd. Mechano-chemical polishing process for GaAs wafers
JP2010010621A (en) * 2008-06-30 2010-01-14 Sumco Corp Method and apparatus for manufacturing semiconductor wafer
US8318042B2 (en) 2009-01-15 2012-11-27 Axt Inc. Systems, methods and solutions for chemical polishing of GaAs wafers
CN105226084A (en) * 2015-09-25 2016-01-06 江苏中科晶元信息材料有限公司 Semi-insulating twin polishing microwave wafer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008004441A1 (en) 2007-02-09 2008-08-14 Sumitomo Electric Industries, Ltd. Mechano-chemical polishing process for GaAs wafers
JP2010010621A (en) * 2008-06-30 2010-01-14 Sumco Corp Method and apparatus for manufacturing semiconductor wafer
US8318042B2 (en) 2009-01-15 2012-11-27 Axt Inc. Systems, methods and solutions for chemical polishing of GaAs wafers
CN105226084A (en) * 2015-09-25 2016-01-06 江苏中科晶元信息材料有限公司 Semi-insulating twin polishing microwave wafer

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