JP2002016208A - Integrated circuit device and its manufacturing method - Google Patents

Integrated circuit device and its manufacturing method

Info

Publication number
JP2002016208A
JP2002016208A JP2000194283A JP2000194283A JP2002016208A JP 2002016208 A JP2002016208 A JP 2002016208A JP 2000194283 A JP2000194283 A JP 2000194283A JP 2000194283 A JP2000194283 A JP 2000194283A JP 2002016208 A JP2002016208 A JP 2002016208A
Authority
JP
Japan
Prior art keywords
leads
semiconductor element
integrated circuit
wiring board
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000194283A
Other languages
Japanese (ja)
Inventor
数弥 ▲高▼崎
Kazuya Takasaki
Hiroyuki Shirakawa
裕之 白川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Denso Electronics Corp
Original Assignee
Denso Corp
Anden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp, Anden Co Ltd filed Critical Denso Corp
Priority to JP2000194283A priority Critical patent/JP2002016208A/en
Publication of JP2002016208A publication Critical patent/JP2002016208A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit device, which is adjacent to and between leads of a semiconductor element mounted on a circuit board, and can easily detect foreign matters which cause defects in condition due to a short circuit, and to provide its manufacturing method. SOLUTION: In a region E including an intermediate layer 3aM or reverse surface 3a2 of a wiring board 3 present across between the leads 2a of the semiconductor element 2 electrically connected to a circuit electrode 31 of the wiring board 3, the element 4 and circuit electrode 31 which are mounted are not present, so that the foreign matter γ can easily be detected, which is located adjacent between the leads 2a and fixed to or stuck on the circuit board 3. Furthermore, the element 4 and circuit electrode 31 are arranged on the intermediate layer 3aM or on reverse surface 3a2 in a region F of the wiring board 3 directly below the leads 2a to integrate the integrated circuit device to high density and also easily detected the foreign matters, etc., which can possibly short-circuits by optically seeing through between the leads 2a.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、集積回路装置およ
びその製造方法に関し、例えば、多層配線基板の表面、
裏面にICチップ等の半導体素子を電気的に接続して構
成する集積回路装置およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device and a method of manufacturing the same.
The present invention relates to an integrated circuit device configured by electrically connecting a semiconductor element such as an IC chip to a back surface and a method of manufacturing the same.

【0002】[0002]

【従来の技術】例えば、はんだ付け等によりICチップ
等の半導体素子と、抵抗チップ等の素子を配線基板の表
面、裏面に実装した集積回路装置がある。
2. Description of the Related Art For example, there is an integrated circuit device in which a semiconductor element such as an IC chip and an element such as a resistance chip are mounted on the front and back surfaces of a wiring board by soldering or the like.

【0003】近年、高密度高集積化により半導体のチッ
プサイズが小型化し、また端子、例えばQFP型のIC
チップのリード数が増加して、そのリードピッチは狭ピ
ッチ化が進んでいる。これにより、この種の集積回路装
置においては、狭ピッチ化したリード間を導電性材料の
異物が架橋する等による短絡に起因した導通不良が発生
する場合がある。
In recent years, semiconductor chips have been reduced in size due to high density and high integration, and terminals, for example, QFP type ICs
As the number of leads of a chip has increased, the lead pitch has been narrowed. As a result, in this type of integrated circuit device, a conduction failure may occur due to a short circuit due to a foreign material of a conductive material bridging between the narrowed leads.

【0004】このため、製造工程のはんだ付け後に配線
検査、特に半導体素子のリード間の短絡に起因する導通
不良を防止するため、目視または画像処理にてリード間
に隣接する異物の有無を検出して異物混入検査を行って
いる。この画像処理等で異物を検出するのに、被検出物
に照明光を当てて、被検出物の反射光の状態を判定して
いる。
For this reason, after soldering in the manufacturing process, in order to prevent a wiring defect, particularly a conduction failure caused by a short circuit between the leads of the semiconductor element, the presence or absence of foreign matter adjacent between the leads is detected by visual observation or image processing. Foreign matter contamination inspection. To detect a foreign object by this image processing or the like, the object is irradiated with illumination light to determine the state of the reflected light from the object.

【0005】[0005]

【発明が解決しようとする課題】従来の集積回路装置お
よびその製造方法では、異物の反射光と周囲物の反射光
とが、照明光の効果により光源色系の類似した色とな
り、異物認識の誤判定を生じる場合がある。
In the conventional integrated circuit device and the method of manufacturing the same, the reflected light of the foreign matter and the reflected light of the surrounding object have a similar color in the light source color system due to the effect of the illumination light, and the foreign matter is recognized. An erroneous determination may occur.

【0006】また、この種の集積回路装置は、高密度化
高密度化して小型化するだけでなく、最小限のコストに
抑えて低コスト化することが要求されている。このた
め、付加価値が付いた製造工程の後半段階での不良を最
小限に抑えて、製造工程の下流では不良を発生させない
ようにできる集積回路装置およびその製造方法が望まれ
ている。
[0006] In addition, it is required that this type of integrated circuit device not only has a high density and a high density but also has a small size, but also has a minimum cost and a low cost. Therefore, there is a demand for an integrated circuit device and a manufacturing method thereof capable of minimizing defects in the latter half of a value-added manufacturing process and preventing defects from occurring downstream of the manufacturing process.

【0007】本発明は、このような事情を考慮してなさ
れたものであり、その目的は、配線基板に実装される半
導体素子のリード間に隣接し、短絡による導通不良を生
じさせる異物を検出し易い構成を備えた集積回路装置お
よびその製造方法を提供することにある。
The present invention has been made in view of such circumstances, and has as its object to detect a foreign substance which is adjacent between leads of a semiconductor element mounted on a wiring board and which causes conduction failure due to a short circuit. An object of the present invention is to provide an integrated circuit device having a configuration that is easy to perform and a method of manufacturing the same.

【0008】[0008]

【課題を解決するための手段】本発明の請求項1および
請求項2によると、複数のリードを有する半導体素子
と、複数のリードと電気的に接続される回路電極を有
し、半導体素子を基板表面に搭載する配線基板とを備え
た集積回路装置であって、半導体素子から延びるリード
間を横切る領域を除く、配線基板の中間層および基板裏
面を含む領域に、搭載部品および導体部材を配置するよ
うにしたので、リード間に隣接し、配線基板に固着また
は付着していてる異物を容易に検出することが可能であ
る。
According to the first and second aspects of the present invention, a semiconductor device having a plurality of leads and a circuit electrode electrically connected to the plurality of leads is provided. An integrated circuit device comprising: a wiring substrate mounted on a surface of a substrate, wherein a mounted component and a conductor member are arranged in a region including an intermediate layer of the wiring substrate and a back surface of the substrate, excluding a region crossing between leads extending from the semiconductor element. Therefore, it is possible to easily detect a foreign substance that is adjacent to between the leads and that is fixed or adhered to the wiring board.

【0009】なお、複数のリードの直下となる配線基板
の中間層および基板裏面を含む領域に、搭載部品または
導体部材を配置するようにすれば、集積回路装置を高密
度高集積化することと、リード間を光学的に透視し易い
構成を備えることで、例えばリード間を架橋して短絡し
うる異物等の検出を容易にすることとが両立可能となり
望ましい。
[0009] If the mounted components or the conductor members are arranged in the region including the intermediate layer of the wiring substrate and the back surface of the wiring substrate immediately below the plurality of leads, the integrated circuit device can be integrated with high density and high integration. It is desirable to provide a structure that makes it easy to optically see through the leads, for example, because it is possible to easily detect foreign substances or the like that can short-circuit by bridging the leads.

【0010】本発明の請求項3および請求項4による
と、請求項1に記載した集積回路装置の製造方法であっ
て、この製造方法は、配線基板の回路電極に予めはんだ
ペーストを塗布する工程と、半導体素子の複数のリード
と回路電極とをはんだ付けにて電気的に接続する工程
と、半導体素子を実装した配線基板に防湿材を塗布する
工程と、半導体素子を実装した配線基板の回路電極の配
線状態および回路機能を検査する工程を含んだ工程を備
えており、しかも上述の検査工程には、半導体素子から
延びるリード間を架橋しうる異物を、周囲物との色差に
より判別する工程を有するので、半導体素子および搭載
部品である標準素子等をはんだ付けにて回路電極に電気
的に接続して形成された電子回路の外観および機能検査
をする工程の初期段階で容易に検出でき、例えば色差を
目視により判別して異物検出することも可能である。
According to the third and fourth aspects of the present invention, there is provided a method of manufacturing an integrated circuit device according to the first aspect, wherein the manufacturing method includes a step of applying a solder paste to circuit electrodes of a wiring board in advance. A step of electrically connecting a plurality of leads of the semiconductor element to the circuit electrodes by soldering; a step of applying a moisture-proof material to the wiring board on which the semiconductor element is mounted; and a circuit of the wiring board on which the semiconductor element is mounted. A step of inspecting a wiring state and a circuit function of the electrode; and a step of discriminating a foreign substance capable of bridging between leads extending from the semiconductor element by a color difference from a surrounding object. The initial stage of the process of inspecting the appearance and function of an electronic circuit formed by electrically connecting a semiconductor element and a standard element which is a mounted component to a circuit electrode by soldering Easily detectable, it is also possible to foreign object detection to determine visually the color difference.

【0011】なお、半導体素子が固定される配線基板の
裏側から透過照明光を当てることによる被検出物の影像
の濃淡を判定することで異物と周囲物との色差を判別
し、しかも透過照明光により透視される、リード間の基
板の影像とリード間を架橋しうる異物の影像との光量差
または明暗により判別するならば、安価な判別装置、例
えば目視により、リード間に導電性の異物が架橋する等
による短絡に起因した導通不良を防止することが可能と
なるので望ましい。
The color difference between the foreign object and the surrounding object is determined by determining the density of the image of the object to be detected by applying the transmitted illumination light from the back side of the wiring board on which the semiconductor element is fixed. If the discrimination is made based on the light amount difference or the lightness or darkness between the image of the substrate between the leads and the image of the foreign matter that can bridge between the leads, the conductive foreign matter can be seen between the leads by visual inspection. This is preferable because it is possible to prevent a conduction failure due to a short circuit due to crosslinking or the like.

【0012】本発明の請求項5および請求項6によれ
ば、色差で判別する、半導体素子のリード間を架橋しう
る異物の対象としては、まず、配線基板に固着している
ものだけでなく付着している金属性異物であって、しか
も、色差で異物と周囲物を判別する検査工程時では、こ
のリード間を架橋しているものだけでなく、防湿材を塗
布する工程で半導体素子を電気的に接続した配線基板に
塗布した防湿材が硬化する過程で、例えば異物が変移す
る等によりリード間を架橋しうる異物の大きさを有する
ものを異常として判別するので、外観および機能検査を
する工程の初期段階で検出でき、後工程の詳細な外観検
査および機能検査をする無駄を省くことができる。
According to the fifth and sixth aspects of the present invention, the foreign objects that can be cross-linked between the leads of the semiconductor element, which are determined based on the color difference, are not limited to those that are fixed to the wiring board. At the time of the inspection process in which the metallic foreign matter is adhered and the foreign matter is distinguished from the surrounding matter based on the color difference, not only the bridge between the leads but also the semiconductor element is applied in the process of applying a moisture-proof material. In the process of curing the moisture-proof material applied to the electrically connected wiring board, a substance having a size of a foreign substance that can bridge between leads due to, for example, a change of the foreign substance is determined as abnormal, so that the appearance and the function test are performed. This can be detected at an early stage of the process, and waste of performing detailed appearance inspection and function inspection in the subsequent process can be eliminated.

【0013】なお、工場出荷時には防湿材が確実に硬化
している程度、例えば最終検査工程までに、この色差に
よる異物判別を行う時期を設定するならば、配線基板に
付着していた異物を硬化した防湿材で集積回路装置をパ
ッケージングするので、異物による短絡等の導通不良を
防止することができるので望ましい。
If the time at which the moisture-proof material is securely cured at the time of shipment from the factory, for example, the time for performing the foreign matter determination based on the color difference before the final inspection process is set, the foreign matter adhering to the wiring board is cured. Since the integrated circuit device is packaged with the moisture-proof material, conduction failure such as a short circuit due to foreign matter can be prevented, which is desirable.

【0014】[0014]

【発明の実施の形態】以下、本発明の集積回路装置およ
びその製造方法を、QFP(Quad Flat Pa
ckage)タイプの4方向にリードが出ている半導体
素子を備えた多層配線基板に実装する集積回路装置に具
体化した実施形態を図面に従って説明する。なお、集積
回路装置の配線基板に実装する半導体素子は、QFPタ
イプに限らず、半導体素子からリードが延びるものであ
ればPGAタイプ等でもよい。図1は、本発明の実施形
態の集積回路装置の概略分解斜視図である。図2は、図
1中のII−II線に沿う模式的断面図である。また、
図3は、本発明の実施形態の製造方法の概略ブロック図
であり、図4は、図3中の検査工程における外観検査の
うち、半導体素子のリード間に隣接する異物を検出する
工程を表すブロック図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an integrated circuit device and a method of manufacturing the same according to the present invention will be described by using a QFP (Quad Flat Pad).
An embodiment embodied in an integrated circuit device to be mounted on a multilayer wiring board having semiconductor elements having leads in four directions of a package type will be described with reference to the drawings. The semiconductor element mounted on the wiring board of the integrated circuit device is not limited to the QFP type, and may be a PGA type or the like as long as the lead extends from the semiconductor element. FIG. 1 is a schematic exploded perspective view of an integrated circuit device according to an embodiment of the present invention. FIG. 2 is a schematic sectional view taken along line II-II in FIG. Also,
FIG. 3 is a schematic block diagram of a manufacturing method according to the embodiment of the present invention. FIG. 4 shows a step of detecting foreign matter adjacent between leads of a semiconductor element in the appearance inspection in the inspection step in FIG. It is a block diagram.

【0015】図1に示すように、集積回路装置1は、半
導体素子2と、配線基板3と、実装される部品(以下、
標準素子、または素子と呼ぶ)4とを含んで構成されて
いる。
As shown in FIG. 1, an integrated circuit device 1 includes a semiconductor element 2, a wiring board 3, and components to be mounted (hereinafter, referred to as a component).
4).

【0016】半導体素子1は、図1に示すように、4方
向にリードが設けられており、リードの端部2aは、後
述の配線基板3の回路電極31に電気的に接続できるす
るよう、はんだ付け可能な表面が形成されている。な
お、このリード2aは、図1では模式的に16ピンで説
明するが、44、100、或いは300ピン等いずれで
もよい。
As shown in FIG. 1, the semiconductor element 1 is provided with leads in four directions, and the ends 2a of the leads are electrically connected to circuit electrodes 31 of the wiring board 3, which will be described later. A solderable surface is formed. Although the leads 2a are schematically described with 16 pins in FIG. 1, they may have any of 44, 100, or 300 pins.

【0017】配線基板3は、多層配線されている基板で
あって、基板3の表面、裏面、中間層に、配線層である
回路電極31が多層化されている。この回路電極31
は、銅箔または銅合金、アルミニウム等の導体部材で形
成されている。図2に示すように、半導体素子2が固定
される側の基板面(以下、表面と呼ぶ)3a1、半導体
素子が固定される側とは反対面(以下、裏面と呼ぶ)3
a2、基板3内部(以下、中間層と呼ぶ)3aMには、
夫々回路電極31a、31b、31cが配置されてい
る。図2に示すように半導体素子2、標準素子4に電気
的に接続する回路電極31の端部(以下、ランドと呼
ぶ)31rには、後述の製造方法で説明するはんだペー
スト(図示せず)が塗布または印刷される。
The wiring substrate 3 is a substrate on which multilayer wiring is performed. The circuit electrodes 31 as wiring layers are formed on the front surface, the back surface, and the intermediate layer of the substrate 3. This circuit electrode 31
Is formed of a conductor member such as copper foil, a copper alloy, and aluminum. As shown in FIG. 2, a substrate surface (hereinafter, referred to as a front surface) 3a1 on a side to which the semiconductor element 2 is fixed, and a surface (hereinafter, referred to as a rear surface) 3 opposite to the side to which the semiconductor element is fixed.
a2, the inside of the substrate 3 (hereinafter referred to as an intermediate layer) 3aM includes:
Circuit electrodes 31a, 31b, 31c are arranged respectively. As shown in FIG. 2, an end portion (hereinafter, referred to as a land) 31r of a circuit electrode 31 electrically connected to the semiconductor element 2 and the standard element 4 has a solder paste (not shown) to be described later in a manufacturing method. Is applied or printed.

【0018】なお、中間層3aMに配置される回路電極
31cは、本実施形態では1層で説明するが、2層以上
に多層化または積層されていてもよい。この配線基板3
は、厚膜印刷、グリーンシート積層、或いはグリーンシ
ート印刷等の製造方法にて形成されている。
Although the circuit electrode 31c disposed on the intermediate layer 3aM is described as a single layer in the present embodiment, it may be formed as a multilayer or a laminate of two or more layers. This wiring board 3
Are formed by a manufacturing method such as thick film printing, green sheet lamination, or green sheet printing.

【0019】標準素子4は、抵抗器、コンデンサ、或い
は水晶振動子、リレー、センサ等の配線基板3に実装さ
れる部品であって、図1に示すような角型の平板状等が
はんだ付けにより回路基板31に電気的に接続されて固
定されている。
The standard element 4 is a component mounted on the wiring board 3 such as a resistor, a capacitor, or a quartz oscillator, a relay, a sensor, etc., and a square flat plate as shown in FIG. And is electrically connected to and fixed to the circuit board 31.

【0020】ここで、半導体素子2、標準素子4は、配
線基板3の回路電極3aに印刷されたはんだペーストに
より、配線基板3上に面実装されれば、電気的接続が容
易である。
Here, if the semiconductor element 2 and the standard element 4 are surface-mounted on the wiring board 3 with the solder paste printed on the circuit electrodes 3a of the wiring board 3, electrical connection is easy.

【0021】なお、半導体素子2と配線基板3の回路電
極31、および標準素子4とを実装する配置の詳細につ
いては後述する。
The arrangement for mounting the semiconductor element 2, the circuit electrode 31 of the wiring board 3, and the standard element 4 will be described later in detail.

【0022】上述の構成を有する集積回路装置1の製造
方法は、図3に示すように、配線基板3を供給する第1
工程P1と、はんだペーストを回路電極31に塗布また
は印刷する第2工程P2と、抵抗器等の標準素子4を配
線基板3に装着する第3工程P3と、半導体素子2を配
線基板3に装着する第4工程P4と、はんだ付けをする
第5工程P5と、半導体素子2、標準素子4を実装した
配線基板3に防湿材を塗布する第6工程P6と、はんだ
付けにより回路電極31に電気的に接続して固定された
標準素子4および半導体素子2の外観および機能検査を
する第7工程P7と、集積回路装置を形成する配線基板
3を収容する第8工程P8とを含んで構成されている。
In the method of manufacturing the integrated circuit device 1 having the above-described structure, as shown in FIG.
Step P1, a second step P2 of applying or printing a solder paste to the circuit electrodes 31, a third step P3 of mounting a standard element 4 such as a resistor on the wiring board 3, and mounting the semiconductor element 2 on the wiring board 3. A fourth step P4 for performing soldering, a fifth step P5 for performing soldering, a sixth step P6 for applying a moisture-proof material to the wiring board 3 on which the semiconductor element 2 and the standard element 4 are mounted, and applying electric power to the circuit electrodes 31 by soldering. A seventh step P7 for inspecting the appearance and the function of the standard element 4 and the semiconductor element 2 fixedly connected and fixed, and an eighth step P8 for accommodating the wiring board 3 forming the integrated circuit device. ing.

【0023】第1工程P1は、積み重ねられた配線基板
3を次工程へ供給する工程であって、配線基板3が薄膜
状の基板の場合は、マガジン等に保持されてから、配線
基板3が逐次送り出される。また、配線基板3に実装す
る半導体素子2から延びるリード2a間の間隔が、微細
ピッチの場合には配線基板3の表面3a1、裏面3a2
に付着する塵埃を洗浄してから次工程へ送ることが望ま
しい。
The first step P1 is a step of supplying the stacked wiring boards 3 to the next step. When the wiring board 3 is a thin-film board, the wiring board 3 is held in a magazine or the like before the wiring board 3 is held. Sent out sequentially. When the spacing between the leads 2a extending from the semiconductor element 2 mounted on the wiring substrate 3 is a fine pitch, the front surface 3a1 and the rear surface 3a2 of the wiring substrate 3
It is desirable that the dust adhering to the surface be washed and then sent to the next step.

【0024】第2工程P2は、半導体素子2、標準素子
4を、配線基板3上に配置された回路電極31のランド
31rに電気的に接続して固定するため、ランド31r
にはんだペーストを塗布または印刷する工程であって、
例えば、ランド31rに合せたスクリーンマスクにより
はんだペーストを印刷する。
In the second step P2, the semiconductor element 2 and the standard element 4 are electrically connected to and fixed to the lands 31r of the circuit electrodes 31 arranged on the wiring board 3.
A step of applying or printing a solder paste on the
For example, the solder paste is printed using a screen mask that matches the land 31r.

【0025】第3工程P3は、部品点数の多い抵抗器、
コンデンサ等の標準素子4を回路電極31のランド31
r上に装着する工程であって、例えば画像認識により自
動的に配線基板3と標準素子4の位置を補正した後、自
動搭載することが望ましい。
The third step P3 includes a resistor having a large number of parts,
The standard element 4 such as a capacitor is connected to the land 31 of the circuit electrode 31.
In this step, it is desirable that the positions of the wiring board 3 and the standard element 4 are automatically corrected by, for example, image recognition, and then automatically mounted.

【0026】第4工程P4は、半導体素子2を回路電極
31のランド31r上に装着する工程であって、半導体
素子2から延びるリード2aを回路電極31の指定され
たランド31r順に搭載する。このため、画像認識によ
り半導体素子2およびリード2aと、ランド31rとの
位置を補正しながら、自動搭載することが望ましい。
In the fourth step P4, the semiconductor element 2 is mounted on the land 31r of the circuit electrode 31, and the leads 2a extending from the semiconductor element 2 are mounted in the specified land 31r of the circuit electrode 31. Therefore, it is desirable to automatically mount the semiconductor element 2 and the lead 2a and the land 31r while correcting the position by image recognition.

【0027】第5工程P5は、実装する配線基板3の種
類に応じて、熱風または赤外線により所定温度特性(例
えば、温度と時間の関係)に管理することにより、はん
だペーストを溶融させて自動はんだ付けする。
In the fifth step P5, according to the type of the wiring board 3 to be mounted, a predetermined temperature characteristic (for example, a relation between temperature and time) is controlled by hot air or infrared rays, thereby melting the solder paste and automatically soldering. Attach.

【0028】第6工程P6は、はんだ付けにより配線基
板3に電気的に接続されて固定された半導体素子2およ
び標準素子4に防湿材(図示せず)を塗布するパッケー
ジングの工程であって、湿気を含んだ空気中で動作させ
ることで生じるマイグレーション現象に起因した集積回
路装置の機能不良を防止するため、防湿材は、少なくと
も、はんだを可能にする表面を備えた導体部分であるリ
ード2a、ランド31r等を被覆する。
The sixth step P6 is a packaging step of applying a moisture proof material (not shown) to the semiconductor element 2 and the standard element 4 which are electrically connected and fixed to the wiring board 3 by soldering. In order to prevent the malfunction of the integrated circuit device caused by the migration phenomenon caused by the operation in the humid air, the moisture proof material is at least a lead 2a which is a conductor portion having a surface enabling soldering. , Land 31r and the like.

【0029】第7工程P7は、はんだ付けして配線基板
3に実装した半導体素子2、標準素子4の周りの外観お
よび機能検査をする工程であって、外観検査では、リー
ド浮きや回路電極31の配線状態等の構造的な検査項目
について、機能検査では、タイミングエラー、信号間干
渉による誤動作等の回路機能に係わる電気的な検査項目
についての不良の検出を行う。
The seventh step P7 is a step of inspecting the appearance and function of the semiconductor element 2 and the standard element 4 mounted on the wiring board 3 by soldering. In the functional inspection of the structural inspection items such as the wiring state, a failure is detected in an electrical inspection item related to a circuit function such as a timing error and a malfunction due to interference between signals.

【0030】なお、外観検査、特に半導体素子2のリー
ド2a周りに関する検査の詳細については後述する。
The details of the appearance inspection, particularly the inspection relating to the periphery of the lead 2a of the semiconductor element 2, will be described later.

【0031】第8工程P8は、全ての実装とパッケージ
ングと検査が完了し、集積回路装置をなす配線基板3を
収納する工程であって、例えば、配線基板3が薄膜状の
基板の場合は、マガジンから外されてから収容される。
The eighth step P8 is a step in which all mounting, packaging and inspection are completed and the wiring board 3 constituting the integrated circuit device is housed. For example, when the wiring board 3 is a thin-film board, , Is housed after being removed from the magazine.

【0032】なお、本実施形態のような多層配線基板3
の表面、裏面に半導体素子3、標準素子4を電気的に接
続して構成する集積回路装置では、まず、配線基板3の
片面側の実装を第2工程P2から第7工程P7まで実施
した後、さらに、配線基板3を反転させて、反対面の実
装を同様に第2工程P2から第7工程P7までを実施す
る。第7工程P7の検査うち、機能検査については両面
を実装した段階で実施してもよい。
The multilayer wiring board 3 according to the present embodiment is
In the integrated circuit device in which the semiconductor element 3 and the standard element 4 are electrically connected to the front and rear surfaces of the wiring board 3, first, the mounting on one side of the wiring board 3 is performed from the second step P2 to the seventh step P7. Further, the wiring board 3 is turned over, and the mounting on the opposite surface is similarly performed from the second step P2 to the seventh step P7. Of the inspection in the seventh step P7, the function inspection may be performed when both surfaces are mounted.

【0033】ここで、本発明の実施形態の特徴である半
導体素子2と、回路電極31、および標準素子4とを実
装する配置について、図1から図2を参照して説明す
る。
Here, an arrangement for mounting the semiconductor element 2, the circuit electrode 31, and the standard element 4, which is a feature of the embodiment of the present invention, will be described with reference to FIGS.

【0034】実装された半導体素子2のリード2aの間
には、その半導体素子2を固定する回路電極側31aの
基板表面3a1に対して、中間層、または裏面に実装さ
れる素子、所謂、半導体素子2、標準素子4等の部品、
または回路電極31を有しない配置を本実施形態の特徴
とする。
Between the leads 2a of the mounted semiconductor element 2, an element mounted on an intermediate layer or a back surface with respect to the substrate surface 3a1 on the circuit electrode side 31a for fixing the semiconductor element 2, that is, a so-called semiconductor Components such as element 2 and standard element 4,
Alternatively, an arrangement having no circuit electrode 31 is a feature of the present embodiment.

【0035】以下、図1および図2を用いて具体例で以
下説明する。まず、図1に示すように、半導体素子2か
ら延びるリードに対して、標準素子4(1)は、表面2
a1上で、離間されて配置されている。このため、リー
ド2a上に標準素子4が重なって配置されることはない
ので、リード間に隣接する異物を検出するのに、標準素
子4が邪魔になることはなく、容易に検出することが可
能である。
A specific example will be described below with reference to FIGS. 1 and 2. First, as shown in FIG. 1, a standard element 4 (1) is
On a1, they are spaced apart from each other. For this reason, since the standard element 4 does not overlap with the lead 2a, the standard element 4 does not hinder the detection of foreign matter adjacent between the leads and can be easily detected. It is possible.

【0036】次に、半導体素子2を実装された表面3a
1に対して、裏面3a2に設けられる回路電極31b
と、その回路電極31bに固定される標準素子4(2)
とは、図2の標準素子4(2)の如く、少なくとも、半
導体素子2から延びるリード2a間、つまり隣合うリー
ド2aに挟まれる(図2中の二点鎖線で囲まれる)領域
E、言い換えれば各リード2a間を横切る配線基板3の
中間層3aMおよび基板裏面3a2を含む領域Eには、
有しないように配置されている(以下、ケースΙの配置
と呼ぶ)。または、図2の回路電極31b(3)、31
b(4)の如く、リード31の表面の直下(図2中の二
点鎖線で囲まれる)領域F内に収まるように配置されて
いる(以下、ケースIIの配置と呼ぶ)。これにより、
ケースIまたはケースIIの配置にすることで、標準素
子4、リード2aが固定されている回路電極31aと異
なる回路電極31b、31cが邪魔になることはなく、
容易に検出することが可能であり、しかも、半導体素子
2、標準素子4を配線基板3の回路電極31上に密集さ
せて積層させることが可能である。しかたって、集積回
路装置1を高密度高集積化することと、後述の製造方法
で説明する検査工程P7にてリード2a間を光学的に透
視することによりリード2a間を架橋して短絡しうる異
物γ(図5参照)等の検出が容易にできることとが両立
可能となる。
Next, the surface 3a on which the semiconductor element 2 is mounted
1 with respect to the circuit electrode 31b provided on the back surface 3a2.
And a standard element 4 (2) fixed to the circuit electrode 31b
2 means at least a region E between the leads 2a extending from the semiconductor element 2, that is, a region E sandwiched between adjacent leads 2a (enclosed by a two-dot chain line in FIG. 2), like the standard element 4 (2) in FIG. For example, in a region E including the intermediate layer 3aM of the wiring board 3 and the back surface 3a2 of the wiring board 3 traversing between the leads 2a,
They are arranged so as not to have them (hereinafter, referred to as the arrangement of Case I). Alternatively, the circuit electrodes 31b (3), 31 of FIG.
As shown in b (4), it is arranged so as to fit in a region F immediately below the surface of the lead 31 (surrounded by a two-dot chain line in FIG. 2) (hereinafter, referred to as case II arrangement). This allows
By arranging the case I or the case II, the circuit electrodes 31b and 31c different from the circuit electrode 31a to which the standard element 4 and the lead 2a are fixed do not interfere.
Detection can be easily performed, and the semiconductor element 2 and the standard element 4 can be densely stacked on the circuit electrodes 31 of the wiring board 3. Therefore, the leads 2a can be bridged and short-circuited by making the leads 2a optically transparent in the inspection step P7 described in the later-described manufacturing method by making the integrated circuit device 1 highly dense and highly integrated. It is possible to easily detect foreign matter γ (see FIG. 5) and the like.

【0037】上述の構成を備えた集積回路装置1の製造
方法において、本発明の実施形態の特徴である第7工程
P7、特に外観検査をする工程を、図4および図5を参
照して以下説明する。図4は、外観検査のうち、半導体
素子2のリード2a間に隣接する異物を検出する工程を
示すブロック図であり、図5は、図4中のリード2aと
隣接する異物との関係を表す模式図である。また、図6
は、図3中の第7工程P7の検査順位を表すブロック図
である。
In the method of manufacturing the integrated circuit device 1 having the above-described configuration, the seventh step P7, which is a feature of the embodiment of the present invention, particularly the step of performing an appearance inspection will be described below with reference to FIGS. explain. FIG. 4 is a block diagram showing a step of detecting a foreign substance adjacent between the leads 2a of the semiconductor element 2 in the appearance inspection, and FIG. 5 shows a relationship between the lead 2a and the adjacent foreign substance in FIG. It is a schematic diagram. FIG.
FIG. 4 is a block diagram showing an inspection order in a seventh step P7 in FIG.

【0038】図4に示す半導体素子2のリード2a間に
隣接する異物γを検出する装置(以下、リード間異物検
出装置と呼ぶ)100は、集積回路装置1の半導体素子
2が固定されている表面3a1とは反対面、つまり裏面
3a2から透過照明光を当てるための光源Lと、半導体
素子2から延びるリード2aの周りを拡大する拡大鏡R
と、透過照明に照らされて生じる色差を拡大鏡Rを介し
て判別する異物判別装置Sとを含んで構成されている。
このリード間異物検出装置100において、異物判別装
置Sは、人の目による目視判別するものでもよいし、拡
大鏡Rと一体的に構成される画像処理判別装置ASであ
ってもよい。なお、図4中の集積回路装置1は、図2と
同じ模式的断面図であり、図中の符号は同じである。
In a device 100 for detecting foreign matter γ adjacent between leads 2a of semiconductor device 2 (hereinafter referred to as a foreign matter detecting device between leads) 100 shown in FIG. 4, semiconductor device 2 of integrated circuit device 1 is fixed. A light source L for applying transmitted illumination light from a surface opposite to the front surface 3a1, that is, a back surface 3a2, and a magnifying mirror R for enlarging around a lead 2a extending from the semiconductor element 2.
And a foreign matter discriminating device S for discriminating, through a magnifying glass R, a color difference generated by the transmitted illumination.
In the inter-lead foreign matter detection device 100, the foreign matter determination device S may be a device that performs a visual determination with human eyes, or may be an image processing determination device AS that is integrated with the magnifying glass R. Note that the integrated circuit device 1 in FIG. 4 is the same schematic cross-sectional view as FIG. 2, and the reference numerals in the drawing are the same.

【0039】光源Lは、太陽光に似た可視光線、或いは
偏光光線を発するものであれば何でもよい。なお、同じ
光量の場合、集積回路装置1を全体を照射する全体照射
光よりは、リード2a周りを照らすスポット光の方が電
力消費量が少なくでき望ましい。
The light source L may be any light source that emits visible light or polarized light similar to sunlight. In the case of the same light amount, a spot light illuminating around the lead 2a is preferably smaller in power consumption than a whole irradiation light irradiating the entire integrated circuit device 1.

【0040】拡大鏡Rは、リード2aに隣接する異物等
の被検出物と、リード2aとを上述の透過照明に照らさ
れて生じる色差により判別できる程度に拡大できればよ
い。
The magnifying glass R only needs to be able to enlarge an object to be detected, such as a foreign substance, adjacent to the lead 2a and the lead 2a to such an extent that the lead 2a can be distinguished by the color difference generated by the above-mentioned transmitted illumination.

【0041】異物判別装置Sは、被検出物に透過照明を
照らして、被検出物の影像の濃淡を判別する色差判別装
置であって、リード2a間にある基板3の影像と、異物
γの影像との透過光の光量差、または明暗により判別す
る。
The foreign matter discriminating device S is a color difference discriminating device for illuminating the object to be detected with transmitted illumination to determine the density of the image of the object to be detected. The determination is made based on the difference in the amount of transmitted light from the shadow image or the brightness.

【0042】上述の構成を有するリード間異物検出装置
100を用いた集積回路装置1の製造方法、特に外観検
査をする工程の特徴を以下説明する。リード間異物検出
装置100を用いた外観検査(以下、異物検出と呼ぶ)
工程P7aは、集積回路装置1のリード2a間を透過照
明する工程S1と、被検出物を透過照明を当てることで
生じた影像の色差を判別する工程S2と、リード2aに
架橋または架橋しうる異物を異常と判定する工程S1と
を含んで構成されている。
A method of manufacturing the integrated circuit device 1 using the inter-lead foreign matter detecting device 100 having the above-described configuration, and in particular, features of a process of performing an appearance inspection will be described below. Appearance inspection using foreign matter detection device 100 between leads (hereinafter referred to as foreign matter detection)
The process P7a includes a process S1 of illuminating between the leads 2a of the integrated circuit device 1, a process S2 of determining a color difference of a shadow image generated by illuminating the object with the transmitted illumination, and a process of bridging or bridging the lead 2a. And a step S1 of determining that the foreign matter is abnormal.

【0043】異物検出工程P7aは、集積回路装置1に
防湿材を塗布するパッケージングの工程P6の後、外観
および機能検査をする工程P7の初期段階に行い、リー
ド2aを架橋している異物γだけでなく、この異物検出
工程P7aを終了した後に異物γの変移等により架橋し
うる大きさを有するものを異常として判別する。これに
より、後工程で行う詳細な外観検査および機能検査を実
施する無駄を省くことができる。
The foreign substance detection step P7a is performed in the initial stage of the appearance and function inspection step P7 after the packaging step P6 of applying a moisture-proof material to the integrated circuit device 1, and the foreign substance γ bridging the lead 2a. In addition, after the foreign substance detection step P7a is completed, a substance having a size that can be crosslinked due to the displacement of the foreign substance γ or the like is determined to be abnormal. Thereby, it is possible to eliminate wastefulness of performing a detailed appearance inspection and a function inspection performed in a later process.

【0044】なお、異常と判別する方法について、図5
に従って以下説明する。図5(a)に示す半導体素子2
において、図5(b)に示すようにリード2aと異物γ
がリード2a間に異物γが架橋、すなわち接触せずに近
接して配置されている場合、異物γの最長方向の長さW
が、リード2a同士で挟まれる長さtと等しいリード2
aに接する内接円φより大きいとき、架橋しうる長さと
判断して、異常と判定する。また、異物検出工程P7a
において、少なくとも、長さWの異物γがリード2a間
に架橋しているものは、当然、異常な異物と判定する。
FIG. 5 shows a method of determining an abnormality.
Will be described below. Semiconductor element 2 shown in FIG.
In FIG. 5B, the lead 2a and the foreign matter .gamma.
When the foreign matter γ is bridged between the leads 2a, that is, when the foreign matter γ is arranged close to each other without contact, the length W of the foreign matter γ in the longest direction is
Is equal to the length t sandwiched between the leads 2a.
If it is larger than the inscribed circle φ that is in contact with a, it is determined that the length is such that it can be crosslinked, and it is determined that there is abnormality. In addition, the foreign matter detection process P7a
In the above, at least a foreign matter γ having a length W bridged between the leads 2a is determined to be an abnormal foreign matter.

【0045】ここで、異物検出工程P7aを、第6工程
P6にて塗布した防湿材が硬化する前であって、機能検
査をする第8工程の最終検査、または工場出荷までには
硬化するように、硬化前となる第8工程の初期段階に実
施することが望ましい(図6参照)。これにより、この
異物検出工程7aにて架橋し短絡しうる異物が排除する
ことが可能であり、しかも、防湿材が硬化後は、防湿材
により、異物γが集積回路装置1に固着するので、異物
による短絡等の導通不良を防止できる。このため、異物
γがパッケージングにより集積回路装置1に固着して存
在している可能性があるにもかかわらず、導通不良とな
らない異物として存在は許容できるので、集積回路装置
の製造において、製造空間の清浄度を極度に高めなくと
も安価に製造できる。
Here, the foreign matter detection step P7a is performed before the moisture-proof material applied in the sixth step P6 is cured and before the final inspection in the eighth step of performing a function test or before shipment from the factory. In addition, it is desirable to carry out at the initial stage of the eighth step before curing (see FIG. 6). Thereby, it is possible to eliminate the foreign matter which can be cross-linked and short-circuited in the foreign matter detection step 7a. Further, after the moisture-proof material is cured, the foreign matter γ is fixed to the integrated circuit device 1 by the moisture-proof material. It is possible to prevent conduction failure such as short circuit due to foreign matter. Therefore, although there is a possibility that the foreign matter γ may be fixedly attached to the integrated circuit device 1 due to packaging, the presence of foreign matter that does not cause a conduction failure is acceptable. It can be manufactured inexpensively without extremely increasing the cleanliness of the space.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態の集積回路装置の概略分解斜
視図である。
FIG. 1 is a schematic exploded perspective view of an integrated circuit device according to an embodiment of the present invention.

【図2】図1中のII−II線に沿う模式的断面図であ
る。
FIG. 2 is a schematic sectional view taken along line II-II in FIG.

【図3】本発明の実施形態の集積回路装置の製造方法の
概略を示すブロック図である。
FIG. 3 is a block diagram illustrating an outline of a method of manufacturing an integrated circuit device according to an embodiment of the present invention.

【図4】図3中の検査工程における外観検査のうち、半
導体素子のリード間に隣接する異物を検出する工程を示
すブロック図である。
FIG. 4 is a block diagram showing a step of detecting foreign matter adjacent between leads of a semiconductor element in the appearance inspection in the inspection step in FIG. 3;

【図5】図4中の配線基板に搭載され回路電極に電気的
に接続された集積回路装置のリードと隣接する異物との
関係を表す模式図である。
5 is a schematic diagram illustrating a relationship between a lead of the integrated circuit device mounted on the wiring board in FIG. 4 and electrically connected to a circuit electrode and an adjacent foreign substance.

【図6】図3中の第7工程の検査順位を表すブロック図
である。
FIG. 6 is a block diagram showing an inspection order in a seventh step in FIG.

【符号の説明】[Explanation of symbols]

1 集積回路装置 2 半導体素子 2a リード 3 配線基板 3a1、3a2、3aM 半導体素子2が固定される表
面、裏面、内部(中間層) 4 標準素子 31 回路電極 31a、31b、31c 表面、裏面、内部に対応する
回路電極 31r ランド(半導体素子2または素子4に電気的に
接続され固定される端部) 100 リード間異物検出装置 L 光源 R 拡大鏡 S 異物判別装置 P1〜P8 集積回路装置の製造方法の工程 P7a 異物検出する工程 S1 集積回路装置のリード間を透過照明する工程 S2 被検出物の色差を判別する工程 S3 架橋、または架橋しうる異物を異常と判定する工
程 γ 異物
Reference Signs List 1 integrated circuit device 2 semiconductor element 2a lead 3 wiring board 3a1, 3a2, 3aM front surface, back surface, inside (intermediate layer) to which semiconductor device 2 is fixed 4 standard device 31 circuit electrode 31a, 31b, 31c front surface, back surface, inside Corresponding circuit electrode 31r Land (end electrically connected to and fixed to semiconductor element 2 or element 4) 100 Foreign matter detecting device between leads L light source R Magnifying glass S Foreign matter discriminating device P1 to P8 Method of manufacturing integrated circuit device Step P7a Step of detecting foreign matter S1 Step of transmitting and illuminating between the leads of the integrated circuit device S2 Step of determining the color difference of the object to be detected S3 Step of determining that a crosslinked or crosslinkable foreign substance is abnormal γ Foreign matter

───────────────────────────────────────────────────── フロントページの続き (72)発明者 白川 裕之 愛知県安城市篠目町井山3番地 アンデン 株式会社内 Fターム(参考) 5E336 AA04 BB03 BC34 CC01  ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hiroyuki Shirakawa 3 Iyama, Shinomecho, Anjo-shi, Aichi Anden F-term (reference) 5E336 AA04 BB03 BC34 CC01

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 複数のリードを有する半導体素子と、 前記複数のリードと電気的に接続される回路電極を有
し、前記半導体素子を基板表面に搭載する配線基板とを
備えた集積回路装置であって、 前記半導体素子から延びる前記リード間を横切る領域を
除く、前記配線基板の中間層および基板裏面を含む領域
に、搭載部品および導体部材を配置するようにしたこと
を特徴とする集積回路装置。
1. An integrated circuit device comprising: a semiconductor element having a plurality of leads; and a wiring board having a circuit electrode electrically connected to the plurality of leads and mounting the semiconductor element on a substrate surface. Wherein the mounted component and the conductive member are arranged in a region including an intermediate layer of the wiring substrate and a back surface of the substrate except for a region crossing between the leads extending from the semiconductor element. .
【請求項2】 前記複数のリードの直下となる前記配線
基板の前記中間層および前記基板裏面を含む領域に、前
記搭載部品または前記導体部材を配置するようにしたこ
とを特徴とする請求項1に記載の集積回路装置。
2. The mounting component or the conductor member is arranged in a region including the intermediate layer and the back surface of the wiring board immediately below the plurality of leads. 3. The integrated circuit device according to claim 1.
【請求項3】 請求項1に記載した集積回路装置の製造
方法であって、 前記配線基板の前記回路電極に予めはんだペーストを塗
布する工程と、 前記半導体素子の前記複数のリードと前記回路電極とを
はんだ付けにて電気的に接続する工程と、 前記半導体素子を実装した前記配線基板に防湿材を塗布
する工程と、 前記半導体素子を実装した前記配線基板の前記回路電極
の配線状態および回路機能を検査する工程を含み、 該検査工程には、前記半導体素子から延びる前記リード
間を架橋しうる異物を、周囲物との色差により判別する
工程を有することを特徴とする集積回路装置の製造方
法。
3. The method of manufacturing an integrated circuit device according to claim 1, further comprising: applying a solder paste to the circuit electrodes of the wiring substrate in advance; and the plurality of leads of the semiconductor element and the circuit electrodes. Electrically connecting by soldering, applying a moisture-proof material to the wiring board on which the semiconductor element is mounted, wiring state and circuit of the circuit electrode of the wiring board on which the semiconductor element is mounted Manufacturing the integrated circuit device, including a step of inspecting a function, wherein the inspecting step includes a step of determining a foreign substance capable of bridging between the leads extending from the semiconductor element by a color difference from a surrounding object. Method.
【請求項4】 前記色差による判別は、前記半導体素子
が固定される前記回路電極側の前記基板表面に対して、
前記基板裏面から透過照明光を当てることによる被検出
物の影像の濃淡を判定する外観検査であって、 前記リード間の前記基板の前記影像と前記異物の前記影
像との、透過光の光量差または明暗により判別している
ことを特徴とする請求項3に記載の集積回路装置の製造
方法。
4. The method according to claim 1, wherein the color difference is determined with respect to the substrate surface on the circuit electrode side to which the semiconductor element is fixed.
It is an appearance inspection for determining the density of an image of an object to be detected by applying transmitted illumination light from the back surface of the substrate, and a light amount difference of transmitted light between the image of the substrate and the image of the foreign material between the leads. 4. The method for manufacturing an integrated circuit device according to claim 3, wherein the determination is made based on brightness.
【請求項5】 前記架橋しうる異物は、前記基板に固
着、または付着する金属性異物であって、 前記検査工程において、前記リード間を架橋している異
物、或いは前記防湿材の硬化過程で前記リード間を架橋
しうる大きさを有する異物を判別することを特徴とする
請求項3または請求項4に記載の集積回路装置の製造方
法。
5. The foreign matter that can be cross-linked is a metallic foreign matter that adheres or adheres to the substrate, and in the inspection step, a foreign substance that bridges between the leads or a curing process of the moisture-proof material. 5. The method for manufacturing an integrated circuit device according to claim 3, wherein a foreign substance having a size capable of bridging between the leads is determined.
【請求項6】 前記半導体素子のリード間を架橋しうる
異物を、周囲物との色差により判別する工程は、前記防
湿材を塗布する工程を終了した後、前記防湿材が、前記
配線状態および前記回路機能を検査する工程の最終検
査、または工場出荷までには硬化するように、硬化する
時間前に行うことを特徴とする請求項3から請求項5の
いずれか一項に記載の集積回路装置の製造方法。
6. The step of discriminating a foreign substance capable of bridging between leads of the semiconductor element by a color difference from a surrounding object, after the step of applying the moisture-proof material is completed, the moisture-proof material is in the wiring state and The integrated circuit according to any one of claims 3 to 5, wherein the process is performed before the curing time so that the circuit function is cured before the final inspection of the process or the factory shipment. Device manufacturing method.
JP2000194283A 2000-06-28 2000-06-28 Integrated circuit device and its manufacturing method Pending JP2002016208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000194283A JP2002016208A (en) 2000-06-28 2000-06-28 Integrated circuit device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000194283A JP2002016208A (en) 2000-06-28 2000-06-28 Integrated circuit device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2002016208A true JP2002016208A (en) 2002-01-18

Family

ID=18693137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000194283A Pending JP2002016208A (en) 2000-06-28 2000-06-28 Integrated circuit device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2002016208A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011171373A (en) * 2010-02-16 2011-09-01 Nitto Denko Corp Inspection method and manufacturing method of wiring circuit board
JP2012098261A (en) * 2010-11-05 2012-05-24 Denso Corp Foreign substance detection device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011171373A (en) * 2010-02-16 2011-09-01 Nitto Denko Corp Inspection method and manufacturing method of wiring circuit board
JP2012098261A (en) * 2010-11-05 2012-05-24 Denso Corp Foreign substance detection device

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