JP2002009296A - Thin film transistor array and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the manufacturing process without lowering its characteristics, and to realize stable LDD or an offset region with high r reproducibility independently of matching accuracy of a photolithography process for refinement, of the thin film transistor. SOLUTION: A source and drain electrodes, video signal wiring, a gate electrode and a part of scanning signal wiring connected with the gate electrode are simultaneously formed by the identical material and process, and the part of the video signal wiring where it crosses with the scanning signal wiring is formed by the identical material and process with which a pixel electrode or reflection electrode is formed. Moreover, a reaction product formed in a pattern sidewall part in self-alignment in dry etching of a metal film or a sidewall insulation film formed in self-alignment in an isotropic etching of a thick insulation film is used as a doping mask in the formation of an offset region or an LDD region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor array and a method for manufacturing the thin film transistor array.

[0002]

2. Description of the Related Art Thin-film transistors (TFTs) are used as switching elements in liquid crystal display devices and EL display devices.
Is widely used. In order to control display of a liquid crystal display device, an EL display device, or the like using a TFT, it is necessary to arrange a TFT for each pixel in a display portion. In recent years, T
As an FT semiconductor film, a polycrystalline silicon film manufactured using a technique of irradiating strong light such as excimer laser light to melt and crystallize an amorphous film has been developed. By using this polycrystalline silicon film, a drive circuit portion can be formed simultaneously on the same substrate on which the switching TFT of the display portion is formed, which was impossible with a conventional amorphous film. Several circuit configurations have been proposed, such as a method using an n-type semiconductor, a method using a p-type semiconductor, or a method using both n-type and p-type for a TFT for a driver circuit. However, a plurality of TFTs are arranged. In the present invention, the arrangement of a plurality of TFTs is collectively referred to as a thin film transistor array. The thin film transistor array mainly includes a single TFT and a signal wiring for connecting the TFTs.

A TF having a conventional top gate structure
The structure of the T array will be described with reference to FIG.

An undercoat film 602 and an amorphous silicon film are continuously formed on a substrate 601. After the amorphous silicon film is heat-treated in a vacuum or in an atmosphere in which an inert gas is replaced with an inert gas, the amorphous silicon film is irradiated with an excimer laser beam in a vacuum to form a polycrystalline silicon film 604. After forming the polycrystalline silicon film 604 in a predetermined pattern,
A gate insulating film 605 is formed on the entire surface of the substrate (FIG.
(A)).

Subsequently, a metal film is formed on the entire surface of the substrate and then processed into a predetermined pattern to form a gate electrode 606 and a scanning signal wiring. Next, n-type impurities are implanted into the substrate surface using the gate electrode 606 as a mask, and the polycrystalline silicon film 6 is formed.
04, a source region 604S and a drain 604D
Is formed (FIG. 6B).

Next, after forming a thickness interlayer insulating film 607,
Source region 604S and drain 6 of polycrystalline silicon film
A contact hole is formed in a predetermined area of 04D (FIG. 6C). A metal laminated film 608 made of a laminated film of Al / Ti is formed thereon, and is then etched and removed in a predetermined pattern to form a source electrode 608S and a drain electrode 608D.
Is formed (FIG. 6D).

Thereafter, a passivation film 60 is formed on the entire surface of the substrate.
9 is formed, and a part of the drain electrode is opened. Finally, after a transparent conductive film is formed on the entire surface of the substrate, it is etched and removed in a predetermined pattern to form a pixel electrode 610, thereby completing a TFT array (FIG. 6E).

As described above, in the prior art, the offset region (region with almost no impurity doping) or the L region for reducing the off current of the TFT and improving the reliability is used.
Even without DD (Lightly Doped Drain) area,
At least six photolithography steps and seven film formation steps were required. Further, when an offset region or an LDD region is required, an additional photolithography step is required.

[0009]

Liquid crystal display devices have already been widely and widely used for monitors for personal computers, portable terminals, and televisions, and competition in the market has intensified. It is essential to reduce the price. One means for realizing a low price is a simplification of the manufacturing process and a device structure for realizing the simplification. There is a demand for a device structure that can be manufactured in a simpler process without reducing at least the performance.

[0010]

According to a first aspect of the present invention, there is provided a thin film transistor array formed on a light-transmitting substrate and connected to at least one of a source / drain electrode and a source / drain electrode, A thin film transistor array including a pixel electrode connected to the other of the source / drain electrodes, a semiconductor film, a gate insulating film, a gate electrode, and a scanning signal line connected to the gate electrode, wherein the source / drain electrode and the video signal line and the gate electrode; And the scanning signal wiring connected to the gate electrode is formed simultaneously with the same material and in the same process, and the video signal wiring or the scanning signal wiring at the portion where the video signal wiring intersects with the scanning signal wiring is the same as the material forming the pixel electrode. It is characterized by being formed simultaneously in the same step. By having such a structure, the following advantages not available in the related art can be obtained.

First, the video signal wiring including the source / drain electrodes and the scanning signal wiring including the gate electrode, which have conventionally required different materials or processes, are simultaneously formed of the same material and in the same process. Reduction of material costs and reduction of film formation and photolithography processes can be realized.

Second, an interlayer insulating film for preventing a short circuit between the video signal wiring including the source / drain electrodes and the scanning signal wiring including the gate electrode, which has been conventionally required, is not required, thereby reducing the number of film forming steps. realizable.

Third, conventionally, when processing source / drain electrodes and gate electrodes in different steps, it is necessary to increase the distance between the electrodes by an amount that adds a dimensional margin depending on the alignment accuracy of the photolithography step. In the case of the present invention, since processing can be performed in the same photolithography process, the distance between both electrodes can be determined by an amount depending on the resolution of the photolithography process. As a result, miniaturization of the element can be realized, which can contribute to reduction in power consumption.

In a second thin film transistor array according to the present invention, a lower region of a side wall portion formed in a step of forming a source / drain electrode, a video signal wiring, a gate electrode, and a part of a scanning signal wiring connected to the gate electrode. The main feature is that a high-resistance semiconductor region is formed in the semiconductor device. By having such a structure, the following advantages not available in the related art can be obtained.

First, the formation of the offset region or the LDD region, which has conventionally required a dedicated photolithography process, is performed in a self-aligned manner at the time of forming the electrode pattern or at the next process after the formation of the electrode pattern. Since the portion is formed as a mask, the number of photolithography steps can be reduced.

Second, the side wall portion has a predetermined shape with good reproducibility under the processing conditions at the time of forming the electrode pattern or the conditions at the time of the next process after forming the electrode pattern. for that reason,
The offset length or the LDD length, which has conventionally been varied by several μm depending on the alignment accuracy of the photolithography process, can be formed with good reproducibility. As a result, it has become possible to stably produce a TFT with small characteristic variations with good reproducibility.

According to a first method of manufacturing a thin film transistor array according to the present invention, a step of forming a semiconductor film in a predetermined region on a light transmitting substrate and a step of forming a gate insulating film and forming an opening in a predetermined region are provided. And a step of injecting impurities into the semiconductor region of the source / drain electrode portion; and forming a source / drain electrode, a video signal wiring, a gate electrode, and a metal film to be a part of a scanning signal wiring connected to the gate electrode in a predetermined region. At least including a step of simultaneously forming a conductive film, a step of injecting impurities into a semiconductor region of a source / drain electrode portion using a metal film as a mask, and a step of simultaneously forming a conductive thin film for connecting a pixel electrode and a scanning signal wiring. It is characterized by. By using such a manufacturing method, the following advantages not available in the related art can be obtained.

First, since an impurity is implanted into the semiconductor surface of the source / drain electrode portion after the gate insulating film is formed and an opening is formed in a predetermined region, the impurity can be implanted with low energy. As a result, it is possible to reduce damage to the semiconductor surface and suppress implantation of impurities into the gate insulating film, which can contribute to improvement in reliability.

Second, since the video signal wiring including the source / drain electrodes and the scanning signal wiring including the gate electrode, which have conventionally required different materials or processes, are simultaneously formed of the same material and in the same process, Reduction of material costs and reduction of film formation and photolithography processes can be realized.

Third, since an interlayer insulating film for preventing a short circuit between the video signal wiring including the source / drain electrodes and the scanning signal wiring including the gate electrode, which is conventionally required, is not required, the number of film forming steps can be reduced. realizable.

Fourth, conventionally, when the source / drain electrode and the gate electrode are processed in different steps, it is necessary to increase the distance between the electrodes by an amount obtained by adding a dimensional margin depending on the alignment accuracy of the photolithography step. In the case of the present invention, since processing can be performed in the same photolithography process, the distance between both electrodes can be determined by an amount depending on the resolution of the photolithography process. As a result, miniaturization of the element can be realized, which can contribute to reduction in power consumption.

As a result, it has become possible to manufacture a TFT array at a lower cost than before, without impairing the performance.

In a second method of manufacturing a thin film transistor array according to the present invention, a step of simultaneously forming a source / drain electrode, a video signal wiring, a gate electrode, and a metal film to be a part of a scanning signal wiring connected to the gate electrode is performed. And processing the metal film into a predetermined shape with the deposit remaining on the side wall.
And a step of injecting an impurity into the semiconductor region of the drain electrode portion. By using such a manufacturing method, the following advantages not available in the related art can be obtained.

First, the formation of the offset region, which has conventionally required a dedicated photolithography process, is performed by masking the side wall portion formed in a self-aligning manner at the time of forming the electrode pattern or at the next process after forming the electrode pattern. Therefore, the number of photolithography steps can be reduced.

Second, the side wall portion has a predetermined shape with good reproducibility under the processing conditions at the time of forming the electrode pattern or the conditions at the time of the next process after forming the electrode pattern. For this reason, the offset length, in which a variation of several μm has conventionally occurred depending on the alignment accuracy of the photolithography process, can be formed with good reproducibility. As a result, it has become possible to stably produce a TFT with small characteristic variations with good reproducibility.

In a third method of manufacturing a thin film transistor array according to the present invention, a step of injecting impurities into a semiconductor region of a source / drain electrode portion, and connecting the source / drain electrode and video signal wiring to a gate electrode and a gate electrode. A step of simultaneously forming a metal film to be a part of the scanning signal wiring, a step of processing the metal film into a predetermined shape while leaving a deposit on a side wall, and masking the metal film containing the side wall deposit Implanting impurities into the semiconductor region of the source / drain electrode portion, removing the sidewall deposits, and implanting the impurity into the semiconductor region of the source / drain electrode portion, and connecting the pixel electrode and the scanning signal wiring. And forming a conductive thin film at the same time. By using such a manufacturing method, the following advantages not available in the related art can be obtained.

First, the formation of the LDD region, which has conventionally required a dedicated photolithography process, is now performed at the time of forming the electrode pattern.
Alternatively, since the side wall formed in a self-aligned manner at the time of the next process after the formation of the electrode pattern is formed as a mask,
The photolithography process can be reduced.

Second, the side wall portion has a predetermined shape with good reproducibility under the processing conditions at the time of forming the electrode pattern or the conditions at the time of the next process after forming the electrode pattern. for that reason,
The LDD length, which had conventionally varied by several μm depending on the alignment accuracy of the photolithography process, can now be formed with good reproducibility. As a result, it has become possible to stably produce a TFT with small characteristic variations with good reproducibility.

According to a fourth method of manufacturing a thin film transistor array according to the present invention, a source / drain electrode, a video signal wiring and a gate electrode, and a metal film to be a part of a scanning signal wiring connected to the gate electrode are simultaneously formed in a predetermined region. Forming, forming an insulating film on the entire surface of the substrate, and then anisotropically etching the insulating film to form an insulating film on the side wall of the metal film; and using the side wall insulating film and the metal film as a mask. And a step of injecting an impurity into the semiconductor region of the source / drain electrode portion. By using such a manufacturing method, the following advantages not available in the related art can be obtained.

First, the offset region, which has conventionally required a dedicated photolithography process, is formed by masking a side wall portion which is formed in a self-aligning manner at the time of forming an electrode pattern or at the next process after forming the electrode pattern. Therefore, the number of photolithography steps can be reduced.

Second, the side wall portion has a predetermined shape with good reproducibility under the processing conditions at the time of forming the electrode pattern or the conditions at the time of the next process after forming the electrode pattern. for that reason,
The offset length, which had conventionally varied by several μm depending on the alignment accuracy of the photolithography process, can now be formed with good reproducibility. As a result, TF with small characteristic variation
T can be manufactured stably with good reproducibility.

In a fifth method of manufacturing a thin film transistor array according to the present invention, a source / drain electrode, a video signal wiring and a gate electrode, and a metal film which is a part of a scanning signal wiring connected to the gate electrode are simultaneously formed in a predetermined region. Forming, implanting impurities into the semiconductor region of the source / drain electrode portion using the metal film as a mask, forming an insulating film over the entire surface of the substrate, and then anisotropically etching the insulating film to form the metal film. The main feature of the present invention is that it includes at least a step of forming an insulating film on the side wall of the semiconductor device, and a step of implanting impurities into the semiconductor region of the source / drain electrode using the side wall insulating film and the metal film as a mask. By using such a manufacturing method, the following advantages not available in the related art can be obtained.

First, the formation of the LDD region, which has conventionally required a dedicated photolithography process, is now performed at the time of forming the electrode pattern.
Alternatively, since the side wall formed in a self-aligned manner at the time of the next process after the formation of the electrode pattern is formed as a mask,
The photolithography process can be reduced.

Second, the side wall portion has a predetermined shape with good reproducibility under the processing conditions at the time of forming the electrode pattern or the conditions at the time of the next process after forming the electrode pattern. for that reason,
The LDD length, which had conventionally varied by several μm depending on the alignment accuracy of the photolithography process, can now be formed with good reproducibility. As a result, it has become possible to stably produce a TFT with small characteristic variations with good reproducibility.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A thin film transistor array and a method for manufacturing the thin film transistor array according to an embodiment of the present invention will be described with reference to FIGS.

The thickness 4 of the SiOx film on the substrate 101
A 00 nm undercoat film 102 and a 60 nm thick amorphous silicon film are continuously formed. 450 in an atmosphere in which amorphous silicon is replaced with a vacuum or an inert gas.
After heating at 2 ° C. for 2 hours, the amorphous silicon film is irradiated with excimer laser light in vacuum to form a polycrystalline silicon film 104.
To form After the polycrystalline silicon film 104 is formed in a predetermined pattern, a SiOx film having a thickness of 90
A gate insulating film 105 of nm is formed (FIGS. 1A, 2A, and 3A).

Next, a contact hole is formed in the gate insulating film 105 in a predetermined region on the polycrystalline silicon film 104. An n-type impurity is implanted into the entire surface of the substrate to form a source region 104S and a drain region 104D in the polycrystalline silicon film in the contact hole portion (FIGS. 1B and 2).
(B), FIG. 3 (b)).

Subsequently, a metal laminated film 106 composed of a laminated film of Ti / Al / Ti is formed. The thickness of each metal film is 30
nm / 300 nm / 80 nm. Metal laminated film 106
Is removed by etching in a predetermined pattern, and the gate electrode 10 is removed.
6G, a source electrode 106S, a drain electrode 106D, a scanning signal wiring 106GL, and a video signal wiring 106SL are formed. Thereafter, a 200 nm SiNx film and 20
A passivation film 107 made of a stacked film of a 0 nm SiOx film is formed (FIGS. 1C, 2C, and 3).
(C)).

A predetermined area of the passivation film 107 is removed by etching to open a part of the scanning signal wiring 106GL and a part of the drain electrode 106D (FIGS. 1D and 2).
(D), FIG. 3 (d)).

Thickness 1 made of indium-doped tin oxide film
After a transparent conductive film 108 of 00 nm is formed on the entire surface of the substrate, it is removed by etching in a predetermined pattern to form a pixel electrode 108P and a scanning signal wiring 108GL serving as a jumper.
The T array is completed (FIGS. 1 (e), 2 (e), 3)
(E)).

The TFT array and the method of manufacturing the same according to the present embodiment have the following unconventional features.

First, the video signal wiring including the source / drain electrodes and the scanning signal wiring including the gate electrode, which have conventionally required different materials or processes, are simultaneously formed of the same material and in the same process. Reduction of material costs and reduction of film formation and photolithography processes can be realized.

Second, an interlayer insulating film for preventing a short circuit between the video signal wiring including the source / drain electrodes and the scanning signal wiring including the gate electrode, which has been required in the past, becomes unnecessary, so that the number of film forming steps can be reduced. I realized it.

Third, when the source / drain electrode and the gate electrode are conventionally processed in different steps, it is necessary to increase the distance between the electrodes by an amount obtained by adding a dimensional margin depending on the alignment accuracy of the photolithography step. In the case of the present invention, since processing can be performed in the same photolithography process, the distance between both electrodes can be determined by an amount depending on the resolution of the photolithography process. As a result, the element can be miniaturized, which contributes to the reduction in power consumption.

In this embodiment, as shown in FIG. 1E, the video signal wiring 106S and the scanning signal wiring 106G
Crosses the scanning signal wiring with the transparent conductive film 108.
Is connected by a jumper (scanning signal wiring 108GL), but the video signal wiring may be connected by a jumper by the transparent conductive film 108.

In this embodiment, the gate electrode, the source / drain electrode, and the Ti / Al
A / Ti laminated film and an indium-doped tin oxide film were used as a part of the pixel electrode and the scanning signal wiring, but the materials are not limited to these. For example, Ti
Instead of the / Al / Ti laminated film, a Mo / Al / Mo laminated film, a Ta / Cu / Ta laminated film or a MoW film, a Cr film,
A Ta film or the like can be used. Further, instead of the indium-added tin oxide film, a different kind of transparent conductive film such as an Al-added zinc oxide film can be used. Further, when a reflective display is used instead of a transmissive display, a metal film having a high reflectance such as an Al / Ti laminated film or an AgPaCu alloy film can be used instead of the transparent conductive film. .

(Second Embodiment) A thin film transistor array and a method of manufacturing the thin film transistor array according to an embodiment of the present invention will be described with reference to FIG.

On a substrate 401, an undercoat film 402 composed of a laminated film of a 200 nm SiOx film and a 100 nm SiNx film and an amorphous silicon film having a thickness of 60 nm are successively formed. After performing heat treatment at 450 ° C. for 2 hours in an atmosphere in which amorphous silicon is replaced with an inert gas in a vacuum, the amorphous silicon film is irradiated with excimer laser light in a hydrogen atmosphere to form a polycrystalline silicon film 404. I do. After forming the polycrystalline silicon film 404 in a predetermined pattern,
A 90-nm-thick gate insulating film 405 made of a SiOx film is formed on the entire surface of the substrate (FIG. 4A).

Next, a contact hole is formed in the gate insulating film 405 in a predetermined region on the polycrystalline silicon film 404. An n-type impurity is implanted into the entire surface of the substrate to lower the resistance of the polycrystalline silicon film in the contact hole (FIG. 4).
(B)).

Subsequently, a metal laminated film 406 made of an Al / Ti laminated film is formed (FIG. 4C). The thickness of each metal film was 300 nm / 80 nm. A predetermined photoresist pattern 410 is formed on the metal laminated film 406, and a BC
The metal stacked film 406 is etched by a dry etching method using a mixed gas of l3 and Cl2. At this time, a reaction product 406SW formed at the time of etching is deposited on the side wall of the metal laminated film 406 to a thickness of about 0.5 μm to 1 μm. By implanting n-type impurities over the entire surface of the substrate while leaving the photoresist 410, a source region 404S and a drain region 404D are formed in a part of the polycrystalline silicon film 404. At this time, the reaction product 406SW formed on the side wall of the metal laminated film 406 serves as a mask for impurity implantation, and the semiconductor film portion located below the metal laminated film side wall is lightly doped. Accordingly, an offset or LDD region 404L having a higher resistance than the source region 404S and the drain region 404D is formed at the end of the gate electrode in a self-aligned manner, and the TF having excellent reliability and off-characteristics is formed.
T is obtained (FIG. 4D).

After removing the photoresist and the reaction product 406SW formed on the side wall of the metal laminated film 406, a passivation film 407 made of a 300 nm SiOx film is formed on the entire surface of the substrate. A predetermined region of the passivation film 407 is removed by etching and the scanning signal wiring 406G is removed.
Part of the L and drain electrodes 406D is opened (partly not shown because it conforms to the first embodiment). After a metal laminated film 408 made of an Al / Ti laminated film is formed on the entire surface of the substrate, it is removed by etching in a predetermined pattern, and the reflective electrode 408P and a scanning signal wiring 408GL serving as a jumper (not shown because it conforms to the first embodiment) ) To complete the TFT array (FIG. 4E).

The TFT array and the method of manufacturing the same according to this embodiment have the following features in addition to the features described in the first embodiment. That is, the reaction product formed on the side wall during the dry etching of the metal laminated film 406 is:
0.5μm by controlling dry etching conditions
It can be controlled to a constant thickness of about 1 μm. Since this value is extremely superior to the alignment accuracy of the conventional photolithography process, the use of this reaction product as a mask during the implantation of impurities makes it possible to obtain a stable and reproducible process without the need for a special photolithography process. It is possible to form the offset region. As a result, a very reliable TF
T can be manufactured.

In this embodiment, a laminated film of Al / Ti is used for the gate electrode, source / drain electrode, and video signal wiring, and Al is used as a part of the pixel electrode and the scanning signal wiring.
Although a laminated film of / Ti was used, each material is not limited to these. For example, instead of the Al / Ti laminated film, an Al / Mo laminated film, a Ta / Cu / Ta laminated film or a MoW film, a Cr film, a Ta film, or the like can be used.
In addition to the material of the above-described embodiment, Ag was used as the reflective electrode film.
It is also possible to use a metal film having a high reflectance such as a PaCu alloy film.

In place of the reflective electrode film, a transparent conductive film such as an indium-doped tin oxide film or an Al-doped zinc oxide film can be used. In this case, a local battery is formed depending on the combination of the transparent conductive film and the metal film, and in some cases, corrosion due to an oxidation-reduction reaction may occur. Therefore, it is necessary to pay attention to the combination of materials that come into direct contact. For example, a combination in which Al and the indium-doped tin oxide film are in direct contact with each other should be avoided.

(Third Embodiment) A thin film transistor array and a method of manufacturing the thin film transistor array according to an embodiment of the present invention will be described with reference to FIG.

A 400 nm SiO film is formed on a transparent substrate 501.
Undercoat film 502 made of x film and thickness of 50 nm
Is continuously formed. 45 in an atmosphere in which amorphous silicon is replaced with a vacuum or an inert gas.
After heat treatment at 0 ° C. for 2 hours, the amorphous silicon film is irradiated with excimer laser light in a hydrogen atmosphere to form a polycrystalline silicon film 504. To form the N-channel region 504N and the P-channel region 504P, the polycrystalline silicon film 504 is etched into a predetermined pattern, and then a 90-nm-thick gate insulating film 505 made of a SiOx film is formed on the entire surface of the substrate. (FIG. 5A).

Next, the polycrystalline silicon films 504N, 504
A contact hole is formed in the gate insulating film 505 in a predetermined region on P. The PH3 gas diluted with H2 is plasma-decomposed and implanted on the substrate surface to lower the resistance of the polycrystalline silicon film in the contact hole (FIG. 5B).

Subsequently, a metal laminated film 506 made of an Al / Ti laminated film is formed and formed in a predetermined pattern.
An insulating film 507 made of a SiO2 film having a thickness of 600 nm is formed on the entire surface of the substrate by using the VD method (FIG. 5C).

Thereafter, the insulating film 507 is anisotropically etched by a dry etching method using a mixed gas of CHF3 and Ar, and the insulating film on the plane parallel to the substrate is removed, leaving the side wall insulating film 507SW. This sidewall insulating film 507SW
Has a thickness of about 0.5 μm to 1 μm (FIG. 5).
(D)).

Next, the PH3 gas diluted with H2 is plasma-decomposed and phosphorous is implanted over the entire surface of the substrate to obtain N2.
A source region 504NS and a drain region 504ND are formed in part of the polycrystalline silicon film 504N in the channel region. At this time, the sidewall insulating film 507SW serves as a mask for impurity implantation, and has an offset or LDD having a higher resistance than the source region 504NS and the drain region 504ND.
The region 504NL is formed (FIG. 5D). continue,
The photoresist 508 is used only for the N-channel TFT region.
Then, the source region 504PS and the drain region 504PD are formed in a part of the polycrystalline silicon film 504P in the P channel region by plasma decomposing the B2H6 gas diluted with H2 and implanting boron over the entire surface of the substrate (FIG. 5 (e)).

After removing the photoresist 508, a passivation film 509 made of a 200-nm-thick SiNx film is formed on the entire surface of the substrate, and a predetermined region of the passivation film 509 is removed by etching to form the scanning signal wiring 506G.
L and a part of the drain electrode 506D are opened (partly not shown because it conforms to the first embodiment). After forming a transparent conductive film having a thickness of 100 nm made of an indium-doped tin oxide film on the entire surface of the substrate, the film is etched and removed in a predetermined pattern to form a pixel electrode and a scanning signal wiring serving as a jumper.
The array is completed (FIG. 5 (f)).

By using the TFT array and the method of manufacturing the same according to this embodiment, the following non-conventional features are added to the features described in the first embodiment. That is, the sidewall insulating film 507E can be controlled to a constant thickness of about 0.5 to 1 μm by controlling dry etching conditions. Since this value is extremely superior to the alignment accuracy of the conventional photolithography process, by using this sidewall insulating film as a mask when implanting impurities, it is stable with good reproducibility without the need for a special photolithography process. An offset or LDD region can be formed in an appropriate manner. as a result,
It has become possible to manufacture a highly reliable TFT.

[0063]

According to the thin film transistor and the method of manufacturing the same of the present invention, (1) the video signal wiring including the source / drain electrodes and the scanning signal wiring including the gate electrode, which have conventionally required different materials or processes, are the same. , And are formed simultaneously in the same process, so that reduction in material cost and reduction in film formation and photolithography processes can be realized.

(2) Since an interlayer insulating film for preventing a short circuit between a video signal line including source / drain electrodes and a scanning signal line including a gate electrode, which has been conventionally required, is not required,
The number of film forming steps can be reduced.

(3) Conventionally, when the source / drain electrode and the gate electrode are processed in different steps, it is necessary to increase the distance between the electrodes by an amount obtained by adding a dimensional margin depending on the alignment accuracy of the photolithography step. In the case of the present invention, since processing can be performed in the same photolithography process, the distance between both electrodes can be determined by an amount depending on the resolution of the photolithography process. As a result, miniaturization of the element can be realized, which can contribute to reduction in power consumption.

(4) The side wall portion which is formed in a self-aligned manner at the time of forming the electrode pattern or at the next process after the formation of the electrode pattern, in which the formation of the offset region or the LDD region, which has conventionally required a dedicated photolithography process, Is used as a mask, so that the number of photolithography steps can be reduced.
The side wall portion has a predetermined shape with good reproducibility under the processing conditions at the time of forming the electrode pattern or the conditions at the time of the next process after forming the electrode pattern. Therefore, the offset length or the LDD length, in which the variation of several μm has conventionally occurred depending on the alignment accuracy of the photolithography process, can be formed with good reproducibility.

By using the above effects independently or in combination according to the functions required of the device, a TFT with small characteristic variations can be stably manufactured with good reproducibility.

[Brief description of the drawings]

FIG. 1 is a top view showing a configuration of a thin film transistor according to a first embodiment of the present invention and a method for manufacturing the thin film transistor.

FIG. 2 is a cross-sectional structural view showing a configuration of a thin film transistor according to a first embodiment of the present invention and a method of manufacturing the thin film transistor.

FIG. 3 is a sectional structural view showing a configuration of a thin film transistor according to a first embodiment of the present invention and a method of manufacturing the thin film transistor.

FIG. 4 is a cross-sectional structural view showing a configuration of a thin film transistor according to a second embodiment of the present invention and a method for manufacturing the thin film transistor.

FIG. 5 is a cross-sectional structural view showing a configuration of a thin film transistor according to a third embodiment of the present invention and a method for manufacturing the thin film transistor.

FIG. 6 is a cross-sectional structural view showing a configuration of a conventional thin film transistor and a method for manufacturing the thin film transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Substrate 102 Undercoat film 104 Polycrystalline silicon film 105 Gate insulating film 106 Metal laminated film 106G Gate electrode 106S Source electrode 106D Drain electrode 106GL Scan signal wiring 106SL Video signal wiring 107 Passivation film 108 Transparent conductive film 108P Pixel electrode 108GL Scan signal wiring

Continued on the front page F-term (reference) 2H092 JA25 JA29 JA33 JA35 JA38 JA39 JA40 JA42 JA43 JA44 JA46 JA47 JB13 JB23 JB24 JB27 JB32 JB33 JB36 JB38 JB52 JB57 JB63 JB69 KA04 KA07 KA12 KA16 KA18 MA17 MA17 MA41 NA24 NA25 NA27 5C094 AA03 AA22 AA43 AA44 BA03 BA43 CA19 EA04 EA07 EB05 FB14 GB10 HA08 JA08 5F110 AA09 AA16 BB01 BB04 CC02 DD13 DD14 DD17 EE02 EE03 EE04 EE06 EE14 EE15 NN03 HL13 NN12 FF12 GG03 NN72 PP03 PP35 QQ08 QQ10 QQ11

Claims (7)

[Claims] 1. A semiconductor device comprising: a source / drain electrode formed on a substrate; a video signal line connected to one of the source / drain electrodes; a pixel electrode connected to the other of the source / drain electrodes; A thin film transistor array including a film, a gate insulating film, a gate electrode, and a scanning signal wiring connected to the gate electrode and substantially orthogonal to the video signal wiring, wherein the source / drain electrodes, the video signal wiring, The gate electrode and the scanning signal wiring connected to the gate electrode are formed of the same material and at the same level, and a video signal wiring or a scan at a portion where the video signal wiring and the scanning signal wiring cross each other. A thin film transistor array, wherein the signal wiring is formed of the same material as the material forming the pixel electrode and at the same level. 2. A high-resistance semiconductor region is formed in a lower region of a side wall portion of each pattern of the source / drain electrode, the video signal wiring, the gate electrode, and the scanning signal wiring connected to the gate electrode. Claim 1 characterized by the following:
3. The thin film transistor array according to item 1. 3. A step of forming a semiconductor film in a predetermined region on a substrate, a step of forming a gate insulating film and forming an opening in a predetermined region, and implanting impurities into a semiconductor region of a source / drain electrode portion. Forming a metal film pattern to be a scanning signal wiring connected to the source / drain electrodes, the video signal wiring and the gate electrode, and the gate electrode at the same level in a predetermined region with the same material at the same level. ,
Using the metal film pattern as a mask to inject impurities into a semiconductor region of a source / drain electrode portion, and to provide a video signal wiring or a scanning signal wiring at a portion where the video signal wiring and the scanning signal wiring intersect, and a pixel electrode. Forming a conductive thin film of the same material at the same level at the same time. 4. A step of forming a semiconductor film in a predetermined region on a substrate, a step of forming a gate insulating film and forming an opening in a predetermined region, and implanting an impurity into a semiconductor region of a source / drain electrode portion. And simultaneously forming the source / drain electrodes, the video signal wiring and the gate electrode, and the metal film pattern to be the scanning signal wiring connected to the gate electrode at the same level with the same material, Processing the film pattern into a predetermined shape with deposits left on the side walls, and implanting impurities into the semiconductor regions of the source / drain electrode portions using the metal film pattern containing the sidewall deposits as a mask, The video signal wiring or the scanning signal wiring at the intersection of the video signal wiring and the scanning signal wiring, and the conductive thin film serving as the pixel electrode are made of the same material at the same level. Method of manufacturing a thin film transistor array including at least a step of forming a. 5. A step of forming a semiconductor film in a predetermined region on a substrate, a step of forming a gate insulating film and forming an opening in a predetermined region, and implanting an impurity into a semiconductor region of a source / drain electrode portion. And simultaneously forming a metal film serving as a scanning signal wiring connected to the source / drain electrodes and the video signal wiring and the gate electrode, and the gate electrode,
Processing the metal film into a predetermined shape with deposits left on the side walls; and implanting impurities into the semiconductor region of the source / drain electrode portion using the metal film containing the sidewall deposits as a mask; Removing the sidewall deposits, injecting an impurity into a semiconductor region of a source / drain electrode portion, a video signal wiring or a scanning signal wiring at a portion where the video signal wiring and the scanning signal wiring intersect, and a pixel electrode. Forming a conductive thin film of the same material at the same level at the same time. 6. A step of forming a semiconductor film in a predetermined region on a substrate, a step of forming a gate insulating film and forming an opening in a predetermined region, and implanting impurities into a semiconductor region of a source / drain electrode portion. And simultaneously forming a metal film pattern serving as a scanning signal wiring connected to the source / drain electrodes and the video signal wiring and the gate electrode, and the gate electrode in a predetermined region at the same level with the same material, Forming an insulating film on the entire surface of the substrate and then anisotropically etching the insulating film to form a sidewall insulating film on a side wall of the metal film pattern; and forming the sidewall insulating film and the metal film pattern as a mask. A step of injecting impurities into the semiconductor region of the source / drain electrode portion, and a video signal wiring or a scanning signal wiring at a portion where the video signal wiring and the scanning signal wiring intersect, and Method for producing at least including a thin film transistor array and the step of simultaneously forming the conductive thin film to be the pixel electrode at the same level of the same material. 7. The method of manufacturing a thin film transistor array according to claim 6, further comprising, after the step of forming the metal film pattern, a step of implanting an impurity into a semiconductor region of a source / drain electrode portion using the metal film pattern as a mask. Method.