JP2002009280A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a highly reliable insulated gate transistor with small dispersion, excellent in transistor characteristic even in a short-gate PMOS transistor. SOLUTION: This semiconductor device includes nitrogen in a gate insulation film 205 of an insulated gate field effect transistor formed in a region of width less than 1.5 μm in the length direction of the gate, and in the interface between a semiconductor substrate 201 and the gate insulation film 205. The concentration of nitrogen included in the interface of the gate insulation film 205 is more than 1×1020 (/cm3), and it also includes a halogen element. Nitrogen in the interface between the semiconductor substrate 201 and the gate insulation film 205 prevents diffusion of boron from source and drain part 208 to suppress abnormal diffusion of boron, and simultaneously, the halogen element in the gate insulation film 205 serves to prevent the degradation of the characteristic of the interface of a channel and gate insulation film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a gate insulating film in an insulated gate transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, transistors have been increasingly miniaturized in accordance with the conventional trend. For this reason, there is a need to suppress variations in threshold voltage of the transistor and the short channel effect.

For this reason, in the case of NMOS, a CMOS having a dual gate structure using a surface channel type transistor using a gate containing an N-type impurity has been developed. In the case of PMOS, a CMOS having a dual gate structure using a surface channel type transistor using a gate containing a P-type impurity has been developed. This is the case, for example, with the International Electron Devices Meeting.
Electron Devices Meeting, 1996, p555-558.

[0004]

However, the present inventors have found that when a CMOS having a dual gate structure is formed using the above surface channel type transistors, the following problems exist as the transistors are miniaturized. To
It was found from the results of the experiment.

That is, as the element formation region becomes smaller, the effect of the change in the substrate plane orientation of the element formation region and the stress of the element isolation region becomes greater. It has been found that if the channel length of the transistor is smaller than 0.3 μm, there arises a problem that boron diffuses from the source / drain portions.

[0006] This phenomenon is caused by the previously reported P
This is not a phenomenon of penetration of boron from a gate electrode in a MOS transistor.

[0007] This phenomenon is that when the element isolation region and the gate electrode are close to each other, boron contained in the source / drain portion locally diffuses abnormally in the channel direction, and the effective channel length becomes short locally. Due to the occurrence of an area. As a result, a phenomenon occurs in which the S-coefficient in the PMOS transistor characteristics greatly varies with the local shortening of the transistor channel. As a result, the off-leak current of the transistor increases, which is a major factor that hinders the reduction of the transistor gate length.

In particular, as the trend of LSIs using MOSFETs, miniaturization will be more and more advanced in the future. When the minimum processing dimension of the miniaturization rule is defined as F,
The gate length L of the logic gate is generally processed with a minimum processing dimension F. At this time, a direction perpendicular to the longitudinal direction of the gate electrode (W direction of the transistor) (gate length direction)
In (2), the margin between the gate and the element isolation (generally, the width of each of the source and drain regions) was formed to have a width of 2.5F to 3F. This is because it is necessary to secure a region for providing a contact hole for connecting to the upper wiring in the source and drain regions.

That is, the active region 10 shown in FIG.
1. In the relationship between the gate 102 and the contact 103, the gate-to-element separation margin is determined by the sum (Za + Zb + Zc) of the contact-to-gate margin Za, the contact diameter Zb, and the contact-to-element separation margin Zc. Was.

However, in recent years, with the development of the contact etching technique, a self-aligned contact technique has been used. As shown in FIG. 11B, the width of the source / drain region in the active region 101 is reduced to 2.5.
It has become possible to greatly reduce the size of F to 3F. By reducing the width of the source and drain regions, the junction parasitic capacitance of the source and drain regions decreases,
It leads to high speed and low power consumption. For this reason, the width of the source and drain regions will be reduced in the future.

However, the element formation region length is 1.5 μm.
We have found that, when it is less than m, in the case of a PMOS transistor, a phenomenon occurs in which boron locally diffuses abnormally from the source and drain regions. This phenomenon seems to be caused by the stress of the element isolation region and the stress of the gate electrode.

When a PMOS transistor in such an element formation region is formed, when the gate length L is smaller than 0.3 μm, a region where the channel length is partially reduced occurs, and the local short channel effect is reduced. The occurrence increases the S coefficient. As a result, the off-leak current of the PMOS transistor increases, so that a transistor with a small gate length cannot be formed, which is a major obstacle to miniaturization of the transistor.

Further, it has been found that the above phenomenon (boron diffusion) is more likely to occur as the impurity concentration in the source and drain regions immediately below the gate end is higher. In other words, in recent years, the low-energy ion implantation technology has progressed, and the impurity concentration in the lower part of the gate end tends to increase. However, as the concentration in this part increases, the diffusion of the impurity into the channel region becomes more remarkable. And it becomes more difficult to form a fine transistor, which is a major problem.

An object of the present invention is to reduce the deterioration of transistor characteristics and the increase in characteristic variations due to the diffusion of boron from the source / drain portions. It was done.

[0015]

In order to achieve the above object, a semiconductor device according to the present invention includes an insulated gate field effect transistor and is formed on a semiconductor substrate having an element isolation region and an element formation region. An apparatus, comprising: a gate insulating film of the insulated gate field effect transistor formed in a region having a width in a gate longitudinal direction of 1.5 μm or less, and including nitrogen at an interface between the semiconductor substrate and the gate insulating film. Features.

According to the present invention, nitrogen at the interface between the semiconductor substrate and the gate insulating film suppresses abnormal diffusion of boron. Therefore, diffusion of boron from the source / drain portions as described above is prevented, and deterioration of transistor characteristics and characteristics are prevented. Variation increase can be reduced.

The present inventors have found that even in a MOSFET in which the distance between the gate and the element isolation is smaller than the normal 2.5F to 3F, nitrogen at the interface between the semiconductor substrate and the gate insulating film suppresses abnormal diffusion of boron. Was confirmed by experiment.

In one embodiment of the present invention, the source / drain impurity concentration in the lower portion of the gate end of the insulated gate transistor is 1 × 10 ¹⁹ / cm ³ or more.

In this embodiment, in an insulated gate transistor having a source / drain impurity concentration of 1 × 10 ¹⁹ / cm ³ or more below the gate end, diffusion of boron from the source / drain can be suppressed, and the transistor characteristics deteriorate. And variation in characteristics can be suppressed.

A semiconductor device according to another embodiment is characterized in that the concentration of nitrogen at the interface between the semiconductor and the gate insulating film in the insulated gate transistor is 1 × 10 ²⁰ cm ⁻³ or more.

In this embodiment, diffusion of boron from the source / drain can be suppressed by setting the nitrogen concentration at the interface between the semiconductor and the gate insulating film in the insulated gate transistor to 1 × 10 ²⁰ cm ⁻³ or more. As a result, deterioration in transistor characteristics and characteristic variations were suppressed.

In one embodiment of the present invention, the gate length of the insulated gate transistor is 0.3 μm.
It is as follows.

In this embodiment, by setting the nitrogen concentration at the interface of the gate insulating film to 1 × 10 ²⁰ cm ⁻³ or more, in an insulated gate transistor having a gate length of 0.3 μm or less, the amount of boron from the source and drain is reduced. Can control the spread,
Deterioration of transistor characteristics and characteristic variations could be suppressed. The nitrogen concentration at the gate insulating film interface is 1 × 10 ²⁰ c
In the case of m ⁻³ or less, in the insulated gate transistor having a gate length of 0.3 μm or less, abnormal diffusion of boron from the source / drain becomes remarkable.

In another embodiment of the present invention, the gate insulating film in the insulated gate transistor contains a halogen element.

In this embodiment, since the gate insulating film contains a halogen element, good characteristics can be obtained without deteriorating the channel-gate insulating film interface characteristics of the transistor despite the high peak nitrogen concentration in the gate insulating film. And, in addition, a transistor excellent in reliability can be obtained.

In one embodiment of the present invention, in the insulated gate transistor, the halogen element contained in the gate insulating film is fluorine.

In this embodiment, since the halogen element in the gate insulating film is fluorine, a stable Si—F bond having a large binding energy is formed, and an insulated gate transistor having a good interface and high reliability is provided. Can be formed.

In a semiconductor device according to another embodiment, the source and drain regions of the insulated gate field effect transistor are stacked up above the channel portion and cover the element isolation region.

In this embodiment, the source and drain regions of the insulated gate field effect transistor are stacked above the channel portion and cover the element isolation region. Therefore, according to the present invention, a contact hole for connecting the source / drain region and the upper wiring may be formed on the source / drain region (stacked layer) which has been stacked up on the element isolation region, and the active region may be formed. There is no need to form on top. Therefore, the width of the source and drain regions can be reduced to the processing limit.

For example, in the case of a semiconductor device which can tolerate a minimum processing dimension F, the alignment margin of photolithography of the upper pattern with respect to the base is generally 1 /.
It is about 3F. Therefore, the margin width between the gate and the element isolation is set to such an extent that the source and drain regions are secured on the active region even when the alignment is shifted to the maximum (that is, 2).
/ 3F to F). Therefore, assuming that the gate length is F, the distance from element isolation to element isolation is 7 / 3F
~ 3F.

As described above, when the element isolation is very close to the gate electrode, the influence of the abnormal diffusion of boron in the channel direction becomes more remarkable due to the stress between the gate electrode and the element isolation. . However, according to the present invention, the interface nitrogen concentration in the gate insulating film is reduced to 1 × 10 ²⁰ c
m ^{- 3} By the above, it is possible to suppress the diffusion of boron from the source and drain portions.

Therefore, even if the element isolation is close to the gate electrode as in the structure of the present invention, the margin between the gate and the element isolation is 2.5F to 3F by suppressing the diffusion of boron. Compared with the element of the normal structure formed with the width of
The deterioration of the coefficient can be suppressed, the increase in off-leak current or the like can be prevented, and the deterioration of transistor characteristics can be prevented.

In one embodiment of the present invention, in a method of manufacturing a semiconductor device, a step of forming a gate insulating film containing nitrogen at an interface between a semiconductor and a gate insulating film in the insulated gate transistor of the semiconductor device includes the step of forming a silicon oxide film. After formation, nitrogen is introduced into the interface between the semiconductor and the gate insulating film using ammonia gas.

In the manufacturing method of this embodiment, after a silicon oxide film is formed as a gate insulating film, nitrogen is introduced into the interface between the semiconductor and the gate insulating film using an ammonia gas. An appropriate amount of nitrogen can be supplied to the interface. Therefore, the amount of nitrogen at the interface between the semiconductor and the gate insulating film can be easily controlled.

In a method of manufacturing a semiconductor device according to another embodiment, the step of forming a gate insulating film containing nitrogen at the interface between the semiconductor and the gate insulating film in the insulated gate transistor of the semiconductor device includes the steps of: Alternatively, after forming a silicon oxide film containing nitrogen using a nitrogen monoxide gas, nitrogen is introduced into an interface between the semiconductor and the gate insulating film using an ammonia gas.

In the manufacturing method of this embodiment, the gate insulating film is first formed using nitrous oxide gas or nitric oxide gas, so that the thickness of the gate insulating film can be easily controlled even in the thin film region. Further, since the nitriding treatment using the gate ammonia gas is subsequently performed, a sufficient amount of nitrogen can be supplied to the interface, and the amount of nitrogen at the interface between the semiconductor and the gate insulating film can be easily controlled.

In one embodiment of the present invention, in the method of manufacturing a semiconductor device, the step of forming a gate insulating film containing nitrogen at the interface between the semiconductor and the gate insulating film in the insulated gate transistor of the semiconductor device uses a nitrogen monoxide gas. Then, a gate insulating film containing nitrogen is formed at the interface between the semiconductor and the gate insulating film.

In the manufacturing method of this embodiment, the gate insulating film containing nitrogen is formed at the interface between the semiconductor and the gate insulating film by using nitric oxide gas, so that a sufficient amount of nitrogen can be introduced into the interface of the gate insulating film. In addition, the step of forming the gate insulating film can be simplified.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings.

[First Embodiment] FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. This semiconductor device
It has a PMOS transistor as a CMOS type insulated gate transistor.

In this semiconductor device, an n-well 202, a p-well 222 and an element isolation region 203 are formed on a semiconductor substrate 201. Here, the element formation region length D
₂₀₄ is the length of the portion indicated by 204.

On the other hand, on the n-well 202 where the PMOS transistor is formed, the interface nitrogen concentration is 1 × 1.
A gate insulating film 205 made of a oxynitride film of 0 ²⁰ cm ⁻³ is formed, and ap ⁺ polycrystalline gate electrode 206 is formed on the gate insulating film 205. On both sides of the polycrystalline gate electrode 206, sidewall spacers 209,
209 are formed, and the side wall spacers 20 are formed.
9 and 209, silicide films 211 and 211 are formed. On the silicide films 211, 211, injection protection films 207, 207 are formed, and below the silicide films 211, 211, a shallow p-type diffusion layer 208 and a deep p-type diffusion layer 210 are formed. Further, metal wirings 213, 213 are formed on the injection protection films 207, 207.

Here, the element forming region lengths D ₂₀₄ and D ₂₀₀ were set to 1.0 μm. In this embodiment,
The impurity concentration in the shallow p-type diffusion layer 208 and the shallow n-type diffusion layer 228 is set to a high concentration of about 1 × 10 ¹⁹ cm ⁻³ . In a shallow impurity diffusion layer used in a conventional LDD (Lightly Doped Drain) structure, the impurity concentration is usually about 1 × 10 ¹⁸ cm ⁻³ or less.

As described above, in the transistor having the structure of this embodiment, the impurity concentration in the lower portion of the end of the gate electrode 206 is high. In this embodiment, the nitrogen concentration at the channel interface is set to a high concentration so that the boron contained in the shallow diffusion layer 208 of the PMOS transistor does not diffuse into the channel region due to the high concentration impurity of the gate electrode 206. By forming such a gate insulating film 205, diffusion of boron is suppressed.

As described above, in a short-channel PMOS transistor having a gate length of 0.3 μm or less, if the phenomenon occurs in which boron locally diffuses from the source and drain regions to the channel, S
Deterioration of the coefficient and increase in off-current occur.

Since high-concentration nitrogen contained in the gate insulating film 205 causes deterioration of transistor characteristics and reliability, in this embodiment, the interface between the channel of the PMOS transistor and the gate insulating film 205 is formed. Fluorine which is a halogen element is introduced. As a result, it has become possible to reduce deterioration of transistor characteristics and reliability.

Next, the PMO of the above structure is shown in the characteristic diagram of FIG.
In the S transistor, the element formation region length D ₂₀₄ is 1 μm.
m, and the dependence of the S coefficient on the gate channel length when the thickness of the gate insulating film 205 is 2.5 nm. In this embodiment, the heat treatment for activating the impurities implanted into the source / drain portions is performed at a temperature of 9 ° C. in a nitrogen atmosphere.
It is performed at 00 ° C. for 10 minutes. As shown in FIG.
When the interface nitrogen concentration of the gate insulating film 205 which is a nitrided oxide film is 1 × 10 ¹⁹ / cm ³ , the channel length of the gate electrode 206 of the PMOS transistor is 0.3 μm.
In the following regions, the S coefficient is significantly deteriorated. The S coefficient is a gate voltage required to increase the drain current by one digit in the sub-threshold region.

On the other hand, when the interface nitrogen concentration of the gate insulating film 205 is set to 1 × 10 ²⁰ cm ^-3 , even in a short channel transistor having a gate length of 0.3 μm or less, the S coefficient does not suddenly deteriorate and a good S coefficient is obtained. Have been obtained. This is because boron contained in the source / drain portions formed by the shallow P-type diffusion layer 208 and the deep P-type diffusion layer 210 is prevented from diffusing into the channel by nitrogen contained in the gate insulating film 205-channel interface. is there. For this reason, it is considered that good transistor characteristics can be obtained even in a short channel PMOS transistor.

Next, the characteristic diagram of FIG.
₂₀₄ and _D200 are 2 μm, and the gate channel length dependence of the S coefficient in the PMOS transistor in which the thickness of the gate insulating film 205 is 2.5 nm is shown. In this case, even if the element formation region lengths D ₂₀₄ and D ₂₀₀ are different from the 1 μm PMOS transistor, even if the gate oxide film 205 is formed of a nitrided oxide film having an interface nitrogen concentration of 1 × 10 ¹⁹ / cm ³ ,
In a short channel transistor having a gate length of 0.3 μm or less, the S coefficient did not rapidly deteriorate.

Next, FIG. 4 shows the element forming region lengths D ₂₀₄ and D ₂₀₄ .
The gate length dependence of the threshold voltage when ₂₀₀ is 1 μm is shown. It can be seen that, unlike the S-coefficient characteristic shown in FIG. 2, the threshold voltage does not change much depending on the gate length when the element region length is 1 μm. From this, it is understood that the change in the S coefficient when the element formation region length is 1 μm is not the deterioration of the S coefficient due to the short channel effect reported conventionally.

FIG. 5 shows the transistor characteristics at a drain voltage of 1.8 V in a PMOS transistor having a gate length of 0.18 μm and a channel width of 10 μm. Here, the element formation region length D ₂₀₀ was set to 1.0 μm. FIG.
As shown by the solid line, when the interface nitrogen concentration of the gate insulating film 205 is 1 × 10 ¹⁹ cm ⁻³ , the S coefficient deteriorates and the off-leak current increases. Off-leak current is
This is the drain current when the source potential and the gate potential are the same, and in this embodiment, the drain current when the gate voltage is 0V.

On the other hand, as shown by the broken line in FIG. 5, the interface nitrogen concentration of the nitrided oxide film forming the gate insulating film 205 is 1 × 10
^{At 20} cm ^-3 , deterioration in characteristics as shown by the solid line in FIG. 5 is not observed, and good PMOS transistor characteristics are obtained.

As described above, as the gate insulating film 205,
When a gate insulating film with an interface nitrogen concentration of 1 × 10 ¹⁹ cm ⁻³ is used, the off-leak current of the transistor increases. However, when a gate insulating film with an interface nitrogen concentration of 1 × 10 ²⁰ / cm ³ is used, Does not deteriorate the S coefficient even in a region having a channel length of 0.3 μm or less. This is because the nitrogen concentration at the interface of the gate insulating film 205 is 1 × 10 ²⁰ / cm ³
This is because abnormally enhanced diffusion of boron from the source and drain regions can be reduced.

Next, by injecting fluorine into the gate polysilicon at a dose of 5 × 10 ¹⁴ / cm ² and then annealing, the PMOS transistor diffuses fluorine and is introduced from the gate electrode 206 to the gate insulating film 205. FIG. 6 shows the change of the S coefficient with respect to the gate length in the above. As shown in FIG. 6, it can be seen that even when fluorine is added to the gate insulating film 205, deterioration of the S coefficient can be suppressed.

Further, since the halogen element and silicon have a large binding energy, a stable bond can be obtained. Therefore, deterioration of transistor characteristics due to hot carrier injection, which is a problem in a fine transistor, can be reduced, and an insulating film with excellent reliability can be formed.

Next, FIG. 7 shows the deterioration rate of the mutual conductance with respect to the hot carrier stress time. In FIG. 7, the solid line indicates the degradation rate characteristics when the interface nitrogen concentration is 1 × 10 ¹⁹ / cm ³ , and the dashed line indicates the degradation rate characteristics when the interface nitrogen concentration is 1 × 10 ²⁰ / cm ^3. Show. Also,
The broken line indicates that the interface nitrogen concentration is 1 × 10 ²⁰ / cm ³ .
NM when fluorine, one of the halogen elements, is added
5 shows characteristics of an OS transistor. In FIG. 7, the drain voltage is set to 3 V as the stress voltage, and the gate voltage is set to the voltage at which the substrate current becomes maximum.

As shown by the dashed line in FIG. 7, when the gate insulating film 205 is a nitrided oxide film having a nitrogen concentration of 1 × 10 ²⁰ / cm ³ , the slope of the mutual conductance deterioration rate curve becomes large. In contrast, the nitrogen concentration was 1 × 10 ²⁰
By adding fluorine to the gate insulating film 205 containing / cm ^3, the slope of the degradation curve of the mutual conductance can be reduced as shown by the broken line.

In the first embodiment, the element isolation region 203 is formed by LOCOS (Local Oxidation of S).
, the element formation region lengths D ₂₀₄ , D ₂₀₀
Is set to 1.5 μm or less, boron diffuses from the source / drain portion due to the influence of stress and the like even when the element isolation region is formed using a trench or the like.
Also in this case, by applying the present invention, the transistor characteristics can be improved as in the above-described embodiment.

Although the present invention largely operates mainly in a transistor having a gate length of 0.3 μm or less, the reason why the nitrided oxide film is used as the gate insulating film of the transistor is that the value of the gate leakage current is small. Considering this, it is a region having a film thickness of 1 nm or more. Therefore, the present invention is effective mainly in a region where the gate length is 0.05 μm or more.

In the present invention, the thickness of the gate insulating film (nitride oxide film) is not particularly limited, but the smaller the thickness of the gate insulating film, the greater the influence of stress. A great effect is obtained in a region where the thickness of the oxynitride film to be formed is 3 nm or less.

[Second Embodiment] Next, FIG.
9 (B) and 9 (C) and FIGS. 9 (D), 9 (E) and 9 (F) show the steps of manufacturing the dual gate CMOS semiconductor device of the present invention in order.

First, as shown in FIG. 8A, a p-well 902 and an n-well 9 are formed on a silicon semiconductor substrate 901.
03 and a field oxide film (element isolation region) 904 are formed. In this embodiment, the field oxide film 904 is used as the element isolation region, but a shallow trench or the like may be used. In this embodiment, the element formation region length is set to 1.5 μm or less, and the device is manufactured as a fine element formation region.

Next, a p-well 90 serving as an NMOS element
2, impurity ions were implanted into boron and phosphorus (P) was implanted into the n-well 903 as a PMOS element to control the threshold voltage and prevent the short channel effect.

Next, before forming a gate oxide film, about 8
After performing a washing step with a mixed solution of ammonia and hydrogen peroxide at a temperature of 0 ° C. and a washing step with a mixed solution of hydrochloric acid and hydrogen peroxide at a temperature of about 80 ° C., about 1% of fluorine is added. The silicon surface was washed with a hydrogen hydride solution. Note that this washing step does not need to be particularly limited to washing with the above solution.

After this cleaning step, the silicon surface is oxidized in an oxidizing atmosphere at a temperature of about 800 ° C. to form a silicon oxide film 905 having a thickness of about 2.5 nm as shown in FIG. I do.

Next, the silicon oxide film 905, in the ammonia gas or nitrogen monoxide atmosphere, nitrided at a temperature of about 900 ° C., as shown in FIG. 8 (B), the interface nitrogen concentration 1 × 10 ²⁰ (/ A gate insulating film 906 having a size of at least cm ³ ) is formed.

After a silicon oxide film containing a trace amount of nitrogen is formed by oxidizing the silicon surface with nitrogen monoxide or nitrous oxide, nitriding is performed by nitriding in an ammonia gas or nitrogen monoxide atmosphere. A gate oxide film 906 may be formed.

By oxidizing in a nitrogen monoxide atmosphere, the oxidizing temperature and the oxidizing time can be controlled, and the gate insulating film 906 containing nitrogen can be formed in one step. The process can be simplified.

Next, as shown in FIG.
The polysilicon film 907 is formed to a thickness of about 100 to 300 nm at a temperature of about 620 ° C. by a (low pressure chemical vapor deposition) method.
Deposit to a thickness of (preferably 250 nm).

Next, as shown by reference numeral 908, about 5 × 10 ¹⁴ (/ cm ² ) of halogen element fluorine or chlorine may be implanted. This step of implanting the halogen element can be performed after the polycrystalline silicon film 907 is patterned into a desired pattern through well-known steps including photolithography and etching.

In this embodiment, ion implantation is used to introduce a halogen element into the gate insulating film 906. However, when forming the gate oxide film 906, a gas such as nitrogen trifluoride or nitrogen trichloride is used. By treating at a temperature of about 600 to 1000 ° C., fluorine or chlorine may be introduced into the gate insulating film.

In addition, P in a dual gate CMOS
In the formation of the MOS transistor, impurities are introduced into the source / drain and the gate simultaneously by ion implantation, and when BF ₂ is used as an implanted ion species, fluorine is introduced into the gate electrode. However, in this case, the injection amount and the injection energy are limited as compared with the fluorine introduction method according to the present invention. This requires a certain amount or more of implantation energy for forming a low-resistance gate electrode, and the characteristics are degraded due to generation of crystal defects and mixing of high-concentration fluorine.

Next, as shown in FIG. 9D, through well-known steps including photolithography and etching,
The polysilicon film (polycrystalline silicon film) 907 was patterned into a desired pattern to form a gate electrode 907.

After completely removing the silicon oxide film on the surface of the gate electrode 907 made of the polycrystalline silicon film and the active region (source / drain) with a hydrofluoric acid solution or the like, a silicon nitride film is formed as an impurity injection protection film 940. The film was deposited on the order of 3-30 nm (preferably 5 nm).
Note that a silicon oxide film may be used as the implantation protection film 940. In this case, when oxygen is knocked on from the silicon oxide film into the semiconductor during ion implantation and silicidation is performed in a later step, Oxygen inhibits the silicidation reaction.

For this reason, in this embodiment, a silicon nitride film is used as the injection protection film 940. If ion implantation conditions capable of sufficiently suppressing metal contamination can be used, direct implantation may be performed without an implantation protection film.

Next, as shown in FIG. 9D, a region to be a PMOS device is covered with a photoresist film 917A by a photolithography process, and arsenic (As) is added as an impurity ion acting as a donor in a silicon semiconductor to the NMOS device. Arsenic) with an energy of 2 to 30 keV and an implantation amount of 0.
Ion implantation was performed at about 5 to 5 × 10 ¹⁴ (/ cm ² ).
As a result, a shallow junction 910 was formed near the channel in the NMOS element region.

In the case of using antimony ions as impurities in the above-mentioned NMOS device, 3- to 35 ke
The implantation is performed at an energy of V and an implantation amount of about 0.5 to 5 × 10 ¹⁴ (/ cm ² ).

Next, the photoresist film 9 shown in FIG.
After removing 17A, the NMOS element is covered with a photoresist film (not shown) by a photolithography process.
Then, BF ₂ ions are implanted into the PMOS device as impurity ions acting as acceptors in the silicon semiconductor at an energy of 5 to 40 keV and an implantation amount of about 0.5 to 5 × 10 ¹⁴ (/ cm ² ). In this ion implantation, BF ₂
In ions or the like may be used instead of ions. By this implantation, a shallow junction 909 is formed in the vicinity of the channel in the PMOS element region.

Next, a silicon nitride film is formed in a thickness of 100 to 200
Then, the selectivity of the silicon nitride film to the silicon oxide film is about 50 to 100 (C ₄
Etchback is performed by F ₈ + CO) gas-based reactive ion etching (RIE) until the surface of the silicon oxide film on the element isolation region 904 is exposed. Thus, the side wall spacer 911 is provided on the side wall of the gate electrode 907.
Was formed.

In this embodiment, the sidewall spacer 911 is formed of a silicon nitride film in order to reduce a bird's beak caused by an oxidation step performed later. However, the sidewall spacer 911 may be formed of a two-layer structure film of a silicon oxide film and a silicon nitride film.

Next, as shown in FIG. 9D, the PMOS element is again covered with the photoresist film 917A by the photolithography step, and as shown by reference numeral 912, the impurity element which acts as a donor in the silicon semiconductor is removed. A certain phosphorus is applied to the NMOS element by 15 to 50 keV.
Ion implantation at an energy of about 1 to 5 × 10 ¹⁵ (/ cm ² ). In this embodiment, an experiment was performed at an energy of 30 keV and an injection amount of 3 × 10 ¹⁵ (/ cm ² ).

Next, after removing the photoresist film 917A, annealing at about 850 to 900 ° C. is performed in a nitrogen atmosphere to activate the implanted impurities.
As shown in (E), a source / drain diffusion layer 913 having a deep junction is formed. Thus, a shallow diffusion layer 910 and a deep diffusion layer 913 are formed in the NMOS element. At this time, in the PMOS element, boron is activated,
A shallow p-type diffusion layer 909 is formed from the shallow junction 909.

Next, as shown in FIG.
The S element is covered with a photoresist film 917C, and the above-mentioned PMOS element is provided in order to prevent a channeling effect.
Injection energy 30 keV, injection amount 1 × 10 ¹⁵ (/ c
Under the condition of m ² ), silicon ions are implanted. Next, as shown by reference numeral 914, boron ions, which are impurity ions acting as
Energy of ~ 30 keV, injection amount of 1-5 × 10 ¹⁵ (/
cm ² ) is implanted into the PMOS device.

Next, the photoresist film 9 shown in FIG.
After the removal of 17C, as shown in FIG. 9F, the implanted impurities are activated by a rapid thermal treatment (RTA, 1000 ° C., 10 seconds) to form a deep source / drain diffusion layer 915 in the PMOS device. . Thereafter, through a known process such as a salicide process, a desired dual-gate CMOS semiconductor device including the contact 977 and the insulating layer 966 as shown in FIG. 9F can be formed.

The PM in this dual gate CMOS
When BF ₂ is used for injection into the source / drain portion and the gate electrode for the OS transistor, the source / drain
Since fluorine is mixed in the drain portion, problems such as an increase in resistance, a decrease in heat resistance, an increase in junction leak, and the like occur in salicidation.

On the other hand, in the manufacturing method of the above embodiment of the present invention, fluorine is introduced before gate patterning, so that fluorine does not enter the source / drain portions, and the above problem does not occur.

In the case where fluorine is contained in the gate insulating film 906, interface defects can be compensated, so that the interface state density is reduced and the mobility is improved. At this time, nitrogen is contained in the gate insulating film 906 at 1 × 10 ²⁰ / cm ^3.
Because of the above, increase in penetration of boron by fluorine can be suppressed. Further, since a halogen element such as fluorine has a large bonding energy with silicon, a stable bond can be obtained.

Therefore, according to this embodiment, deterioration of transistor characteristics due to hot carrier injection, which is a problem in a fine transistor, can be reduced, and a highly reliable insulating film can be formed.

Although the device isolation region is formed by LOCOS (Local Oxidation of Silicon) in this embodiment, the device isolation region may be formed by using a trench or the like. Also in this case, when the element formation region length is set to 1.5 μm or less, boron diffuses from the source / drain portion due to the influence of stress and the like. In addition, transistor characteristics can be improved.

[Third Embodiment] FIG. 10 shows a semiconductor device according to a third embodiment of the present invention. FIG.
Shows a vertical cross section when the semiconductor device is cut perpendicularly to the longitudinal direction of the gate electrode.

As shown in FIG. 10, in this embodiment, in a semiconductor substrate 1000 roughly divided into an element isolation region 1001 and an active region 1002, a MIS (Metal-Insulator-Semiconductor) formed on the active region 1002 is formed. Semiconductor device.

In this semiconductor device, the gate insulating film 1
003 interface nitrogen concentration 1 × 10 ²⁰ cm ^- a ^three nitride oxide film. Gate electrode side wall insulating films 1005 and 1005 are formed adjacent to both sides of the gate electrode 1004.

In the third embodiment, the source / drain region 1006 extends above the active region surface AA ′ containing the interface between the gate insulating film 1003 and the active region 1002. The source and drain regions 1006 are adjacent to the gate electrode 1004 with the insulating film 1005 interposed therebetween.

The active region 1002 and the element isolation region 10
The boundary (CC ′) with 01 exists between the end in the direction perpendicular to the longitudinal direction of the gate electrode 1004 and the end (BB ′) of the source / drain region 1006. That is, the source / drain region 1006 has the stacked portion 1006A that covers the element isolation region 1001.

Further, in a vertical cross section cut perpendicular to the longitudinal direction of the gate electrode 1004, the distance d between the active region surface AA ′ of the semiconductor substrate 1000 and the surface of the source / drain region 1006 is , Element isolation region 1
It increases from 001 to the gate electrode 1004 side. That is, the source and drain regions 10
Reference numeral 06 has a convexly curved surface whose thickness gradually increases from the end (B-B ') toward the gate electrode 1004.

According to the above structure, as shown in FIG.
A contact hole 1007 connecting the source / drain region 1006 to an upper wiring (not shown) is formed in the element isolation region 100.
1 may be formed on the source / drain region 1006 which covers up to 1 level. That is, the contact hole 1007
Is the stacked portion 100 of the source / drain region 1006
6A and the element isolation region 1001.

As described above, according to this embodiment, the formation region of the contact hole 1007 does not need to be limited only to the active region 1002, and the source and drain regions 1
006 can be reduced to the processing limit.

As a specific example, the minimum processing size F
In the case of using a processing apparatus capable of processing up to a maximum, generally, the alignment margin of photolithography of the upper pattern with respect to the base is about (１) F. For this reason, even when the alignment is shifted to the maximum, the size of the source and drain regions 1006 formed on the active region 1002, that is, the margin width between the gate and the element isolation is 2 / 3F to 1F.
It should just be set to about.

In other words, the activation region 1002
To the electrically isolated gate 1004, source 100
6, and a drain 1006. The structure covers the gate 1004 from the element isolation 100.
There is no vertical step between them.

In the structure of the third embodiment, the surface 1006B of the source / drain region 1006
Are closer to the gate electrode 1004, the active area surface A-
It is separated above A '. As a result, when impurity doping is performed on the source / drain regions 1006 by the ion implantation method, the source / drain regions 1006 and the semiconductor substrate 1000 are closer to the gate electrode 1004 from the active region surface AA ′. The depth d 'to the junction 1111 becomes shallower. Thereby, the short channel effect at the time of miniaturization can be effectively suppressed. The junction 1111 is a junction between a source / drain region and a well region of the opposite conductivity type in a general ordinary CMOS.

In this embodiment, at least a part of the contact hole 1007 for connecting the source / drain region surface 1006B to the upper wiring covers the source / drain region surface 1006B. Just do it. As a result, in the transistor element of this embodiment, the surface area can be increased with respect to the area occupied by the source and drain regions 1006 on the active region 1002. Therefore, the contact area between the source / drain region 1006 and the upper wiring can be set large, and the contact resistance can be reduced. Further, the area occupied by the element, especially the area occupied by the source and drain regions can be reduced irrespective of the size of the contact.

Therefore, according to the third embodiment,
The junction area between the source / drain region 1006 and the semiconductor substrate 1000 can be reduced without sacrificing the contact resistance, and the junction capacitance can be effectively reduced. In the case of a general ordinary CMOS, the junction area is the junction area between the source and drain regions and the well region of the opposite conductivity type.

That is, in the structure of this embodiment, the occupied area can be reduced without sacrificing the contact resistance, the parasitic capacitance (junction capacitance) can be reduced, the parasitic resistance can be reduced, and a very large transconductance can be obtained. Can be obtained.

Further, in the transistor element of this structure, the ratio of the region of high resistance (the distance from the channel to the contact) occupying the current flow path is smaller than that of the normal structure.
Very little, the parasitic resistance of the source / drain region 1006 can be reduced.

Furthermore, in the source / drain region 1006, the path through which the current flows increases from near the channel region to the contact, so that the parasitic resistance can be further reduced. From these facts, in this embodiment, the current driving capability of the element can be increased, and the transconductance can be improved.

By the way, in the device having the structure of this embodiment, when the gate length is F, the distance from the device isolation region 1001 to the next device isolation region 1001 is 7 / 3F to 3/3.
It is about F.

As described above, when the element isolation 1001 is very close to the gate electrode 1004 and the gate insulating film of the related art is employed, the boron is applied to the channel by the stress between the gate electrode 1004 and the element isolation 1001. The effect of abnormal diffusion in the direction becomes more pronounced. In this case, in the device having this structure, the deterioration of the transistor characteristics such as the deterioration of the S coefficient in the PMOS transistor characteristics and the increase of the off-leak current becomes more remarkable as compared with the device having the normal structure. The element having the normal structure is an element having a gate-element separation margin of 2.5F to 3F.

On the other hand, in the third embodiment, the first
As in the embodiment, since the gate insulating film 1004 made of a nitrided oxide film having an interface nitrogen concentration of 1 × 10 ²⁰ cm ⁻³ is formed, the peak nitrogen concentration in the gate insulating film 1004 is set to 1
× 10 ²⁰ cm ^- can in ³ or more, the source and drain portions 10
06 can suppress the partially abnormally accelerated diffusion of boron.

[0109]

As is apparent from the above description, the semiconductor device of the present invention has a structure in the gate insulating film of an insulated gate field effect transistor formed in a region having a width of 1.5 μm or less in the gate longitudinal direction, and in the semiconductor device. Nitrogen is contained at the interface between the substrate and the gate insulating film. Therefore, nitrogen at the interface between the semiconductor substrate and the gate insulating film prevents diffusion of boron from the source / drain portions, suppresses abnormal diffusion of boron, and reduces deterioration of transistor characteristics and increase in variation in characteristics.

In one embodiment of the present invention, the source / drain impurity concentration under the gate end is 1 × 10 5
^In an insulated gate transistor of ¹⁹ / cm ³ or more, diffusion of boron from the source / drain can be suppressed,
Deterioration of transistor characteristics and characteristic variations can be suppressed.

In the semiconductor device according to another embodiment, the diffusion of boron from the source / drain is controlled by setting the nitrogen concentration at the interface between the semiconductor and the gate insulating film in the insulated gate transistor to 1 × 10 ²⁰ cm ⁻³ or more. , And deterioration of transistor characteristics and characteristic variations can be suppressed.

In one embodiment of the semiconductor device, the gate length of the insulated gate transistor is 0.3 μm or less. In this embodiment, by setting the nitrogen concentration at the interface of the gate insulating film to 1 × 10 ²⁰ cm ⁻³ or more, in an insulated gate transistor having a gate length of 0.3 μm or less,
The diffusion of boron from the source / drain can be suppressed, and the deterioration and the variation in the characteristics of the transistor can be suppressed.
Note that the nitrogen concentration at the interface of the gate insulating film is 1 × 10 ²⁰ cm ^−3.
In the case where it is less than or equal to, in the insulated gate transistor having a gate length of 0.3 μm or less, abnormal diffusion of boron from the source / drain becomes remarkable.

In the semiconductor device of another embodiment, the gate insulating film in the insulated gate transistor contains a halogen element. Thereby, even if the peak nitrogen concentration in the gate insulating film is high, favorable transistor characteristics can be obtained without deteriorating the interface characteristics of the channel / gate insulating film of the transistor, and a transistor excellent in reliability can be obtained. Obtainable.

In the semiconductor device of one embodiment, since the halogen element in the gate insulating film of the insulated gate transistor is fluorine, a stable Si—F bond having a large bonding energy is formed, and a good interface and A highly reliable insulated gate transistor can be formed.

Further, in the semiconductor device of another embodiment, the source and drain regions of the insulated gate field effect transistor are stacked above the channel portion and cover the element isolation region. Therefore, according to this embodiment, on the source / drain region (stacking layer) which is stacked up on the element isolation region, a contact hole for connecting the source / drain region and the upper wiring may be formed. The source and drain region width can be reduced to the processing limit.

In one embodiment of the method of manufacturing a semiconductor device, in the step of forming a gate insulating film containing nitrogen at an interface between the semiconductor and the gate insulating film, after forming a silicon oxide film as a gate insulating film, Nitrogen is introduced into the interface between the semiconductor and the gate insulating film using a gas. Therefore, a sufficient amount of nitrogen can be supplied to the interface by the nitriding treatment using ammonia gas, and the amount of nitrogen at the interface between the semiconductor and the gate insulating film can be easily controlled.

In the method of manufacturing a semiconductor device according to another embodiment, a gate insulating film is first formed using a nitrous oxide gas or a nitric oxide gas. Can be easily controlled. Further, since the nitriding treatment using the gate ammonia gas is subsequently performed, a sufficient amount of nitrogen can be supplied to the interface, and the amount of nitrogen at the interface between the semiconductor and the gate insulating film can be easily controlled.

In one embodiment of the method of manufacturing a semiconductor device, in the step of forming a gate insulating film containing nitrogen at the interface between the semiconductor and the gate insulating film, a nitrogen monoxide gas is used.
A gate insulating film containing nitrogen is formed at the interface between the semiconductor and the gate insulating film. Therefore, a sufficient amount of nitrogen can be introduced into the gate insulating film interface, and the step of forming the gate insulating film can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram showing a transistor structure according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a relationship between an S coefficient and a gate channel length in a PMOS transistor when the element formation region length in the first embodiment is 1 μm.

FIG. 3 is a characteristic diagram showing a relationship between an S coefficient and a gate channel length in a PMOS transistor when the element formation region length is 2 μm in the first embodiment.

FIG. 4 is a characteristic diagram showing a relationship between a threshold voltage and a gate channel length in a PMOS transistor when the element formation region length is 1 μm in the first embodiment.

FIG. 5 is a characteristic diagram showing a relationship between a drain current and a gate voltage in a PMOS transistor in the first embodiment.

FIG. 6 is a characteristic diagram showing a relationship between an S coefficient and a gate channel length in a PMOS transistor in the first embodiment.

FIG. 7 is a characteristic diagram showing a relationship between a deterioration rate of a mutual conductance and a stress time in the first embodiment.

FIGS. 8A to 8C are diagrams sequentially illustrating the first half of a manufacturing process of a dual gate CMOS semiconductor device according to a second embodiment of the present invention.

FIGS. 9D to 9F are diagrams sequentially illustrating the latter half of the manufacturing process.

FIG. 10 is a view showing a structure of a transistor having a stacked structure of source / drain portions in a third embodiment of the semiconductor device of the present invention.

FIG. 11A is a layout diagram of a conventional transistor, and FIG. 11B is a layout diagram of a transistor which is a premise of the present invention.

[Explanation of symbols]

101: Active region, 102: Gate, 103: Contact diameter, 104: Stacked source / drain region, 201
... semiconductor substrate, 202 ... p-well, 203 ... n-well, 204 ... element isolation region, 205 ... gate insulating film, 2
06: gate electrode, 207: injection protection film, 208: shallow p-type diffusion layer, 209: sidewall spacer, 210
... deep p-type diffusion layer, 211 ... silicide film, 212 ... interlayer insulating film, 213 ... metal wiring, 214 ... deep n-type diffusion layer, 901 ... silicon semiconductor substrate, 902 ... p-well, 903 ... n-well, 904 ... Element isolation region, 90
5 silicon oxide film, 906 gate insulating film, 907
Polysilicon film (gate electrode), 908: arrow indicating injection of halogen element, 909: shallow junction, 910: shallow p-type diffusion layer, 911: sidewall spacer, 912 ...
Arrows indicating phosphorus ion implantation, 913: deep p-type diffusion layer, 917A, 917B: photoresist film, 940 ...
Injection protective film, 1000 semiconductor substrate, 1001 element isolation region, 1002 active region, 1003 gate insulating film, 1004 gate electrode, 1005 gate electrode sidewall insulating film, 1006 source / drain region, 1007
Contact hole.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Seizo Kakimoto 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term (reference) 5F040 DA02 DA06 DA17 DA28 DB03 DC01 EC01 EC07 EC13 ED03 EE05 EF01 EF02 EH02 EH08 EK01 EK05 FA05 FA07 FA10 FA16 FA18 FB02 FC06 FC15 FC19 FC21 5F048 AA07 AA08 AC03 BA01 BB06 BB07 BB11 BB14 BC01 BC06 BE03 BF06 BG12 BG14 DA25 DA27 DA30

Claims (10)

[Claims] 1. A semiconductor device including an insulated gate field effect transistor, formed on a semiconductor substrate having an element isolation region and an element formation region, wherein the width of the gate in the longitudinal direction is 1.5 μm or less. A semiconductor device comprising nitrogen in a gate insulating film of the formed insulated gate field effect transistor and in an interface between the semiconductor substrate and the gate insulating film. 2. The semiconductor device according to claim 1, wherein the insulated gate transistor has a source / drain impurity concentration below a gate end of 1 × 10 ¹⁹ / cm.
A semiconductor device, wherein the number is ³ or more. 3. The semiconductor device according to claim 3, wherein the concentration of nitrogen at the interface between the semiconductor and the gate insulating film in the insulated gate transistor is 1 × 10 ²⁰ cm ⁻³ or more. 4. The semiconductor device according to claim 3, wherein the insulated gate transistor has a gate length of 0.5.
A semiconductor device having a thickness of 3 μm or less. 5. The semiconductor device according to claim 1, wherein a gate insulating film of the insulated gate transistor contains a halogen element. 6. The semiconductor device according to claim 1, wherein the halogen element contained in the gate insulating film is fluorine. 7. The semiconductor device according to claim 1, wherein the source and drain regions of the insulated gate field effect transistor are stacked up above a channel portion and formed on the element isolation region. A semiconductor device characterized by being covered. 8. A step of forming a gate insulating film containing nitrogen at an interface between a semiconductor and a gate insulating film in the insulated gate transistor of the semiconductor device according to claim 1. After the formation of, using ammonia gas,
A method for manufacturing a semiconductor device, comprising introducing nitrogen to an interface between a semiconductor and a gate insulating film. 9. The step of forming a gate insulating film containing nitrogen at an interface between a semiconductor and a gate insulating film in the insulated gate transistor of the semiconductor device according to claim 1, Alternatively, a method for manufacturing a semiconductor device, comprising forming a nitrogen-containing silicon oxide film using a nitrogen monoxide gas and introducing nitrogen to an interface between the semiconductor and the gate insulating film using an ammonia gas. . 10. The step of forming a gate insulating film containing nitrogen at an interface between a semiconductor and a gate insulating film in the insulated gate transistor of the semiconductor device according to claim 1, A method for manufacturing a semiconductor device, comprising forming a gate insulating film containing nitrogen at an interface between the semiconductor and the gate insulating film.