JP2002009043A - Etching device and manufacturing method of semiconductor device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent etching fail around the outer periphery of a semiconductor wafer (the outer periphery of an electrode) in the manufacturing method of the semiconductor device having a process that applies power to a flat electrode for setting a reactive gas to an ionization state (plasma) and etches a semiconductor wafer on the electrode. SOLUTION: This etching device has a first electrode for placing the semiconductor wafer, a second electrode that is arranged opposite to the first one, and a power source for supplying power to the first electrode; and ionizes the gas molecules between the first and second electrodes (changes the gas molecules between the first and second electrodes into plasma) for etching the semiconductor wafer. In this case, the first electrode is composed of a plurality of divided electrodes, and an insulator for electrically separating each divided electrode, and a plurality of the power sources for supplying different power to each divided electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching apparatus and a method for manufacturing a semiconductor device using the same, and more particularly to a plasma etching apparatus using a reactive gas and a technique effective when applied to an etching method. .

[0002]

2. Description of the Related Art Conventionally, in the manufacturing process of a semiconductor device,
In the process of forming devices on a semiconductor wafer such as silicon and wiring the devices, processing by etching is often used. Examples of the etching method include dry etching in which a reactive gas is used to react a substance on the surface of a semiconductor wafer with the reactive gas, and wet etching using a solution (etchant). As an etching apparatus used for the dry etching, a parallel plate type etching apparatus is well known.

In the parallel plate type etching apparatus, as shown in FIG. 9, a first electrode (wafer holder) 1 'serving as a lower electrode and a second electrode (upper electrode) 2 are provided with a gas supply port 3A.
And the wafer holder 1 ′ is connected to a high-frequency power source 4.

In the etching by the parallel plate type etching apparatus, first, a semiconductor wafer 5 on which a predetermined pattern is formed with a resist is placed on the wafer holder 1 ′, and a reaction gas is supplied from the gas supply port 3 A into the vacuum chamber 3. (Etching gas). As the etching gas to be supplied at this time, various gases are selected according to the thin film material on the surface of the semiconductor wafer 5 to be etched.

Next, when high-frequency power for bias is applied from the high-frequency power source 4 to the wafer holder 1 ′ which is arranged in parallel to the grounded upper electrode 2, the wafer holder 1 ′ and the upper The etching gas between the electrodes 2 is in an ionized state (plasma). The gas (gas) 6 converted into plasma is a positive ion (positive ion),
Charged particles such as negative ions (negative ions) and electrons and neutral active species (etching species) are present in a separated (ionized) state. When the etching species of the plasmatized gas 6 is adsorbed on the thin film material (material to be etched) on the surface of the semiconductor wafer 5, a surface chemical reaction occurs,
Etching is performed by exhausting and removing the etching product generated by the chemical change from the exhaust port 3B.

The chemical reaction used in the etching is
Of thin film material (material to be etched) and etching gas
Depending on the type, for example, a silicon dioxide film (S
iO _Two) Is etched, the etching gas
As C_FourF₈Etc., the silicon dioxide
SiF on the surface of the film_FourAnd produce CO and exhaust them
By doing so, the etching proceeds. In addition, the silicon dioxide
The etching of the condenser film is performed by using CF as the etching gas.
_FourAnd CHF_ThreeUsing SiF_FourAnd produce CO, Etchin
You can also

Further, when etching silicon (Si), for example, when Cl ₂ is used as the etching gas, SiCl _x is generated as a reaction product when a plasma is formed and a chemical reaction occurs, and the etching proceeds. . In addition, etching can be performed by generating SiBr _x using HBr as the etching gas or generating SiF _x using SF ₆ as the etching gas.

In addition, the etching is also used for forming a metal wiring such as aluminum (Al) when connecting the semiconductor elements formed on the semiconductor wafer 5, for example. At this time, when a mixed gas of Cl ₂ and BCl ₃ is supplied as the etching gas and the mixed gas is turned into plasma to cause a chemical reaction, AlCl ₃ is generated as a reaction product and etched.

In dry etching such as plasma etching, problems such as physical damage such as crystal defects and contamination, dielectric breakdown due to charge-up, and a phenomenon (microloading effect) in which the etching rate is different due to pattern densification are likely to occur. Various measures have been taken to avoid these problems.

[0010]

However, in the prior art, for example, in a wiring step of connecting each element formed on a semiconductor wafer with a metal wiring, as shown in FIG. First metal wiring 9A on 8A
Then, through holes are formed in the second interlayer insulating film 8B in order to connect the second metal wires 9B formed in different wiring layers via the second interlayer insulating film 8B. The first interlayer insulating film 8A and the second interlayer insulating film 8B are made of, for example, a silicon dioxide film (SiO ₂ ).
Is formed by etching with an etching apparatus as shown in FIG. At this time, as shown in FIG. 10, a through hole penetrates through the second interlayer insulating film 8B near the center of the semiconductor wafer 5, in other words, near the center of the wafer holder 1 '. Filled metal 12A
Is connected to the first metal wiring 9A, but in the interlayer insulating film 8B near the outer periphery of the semiconductor wafer 5, in other words, near the outer periphery of the wafer holder 1 ', the through hole does not penetrate, and Is not connected to the first metal wiring 9A. Similarly, when a through-hole is formed in the third interlayer insulating film 8C on the second metal wiring 9B, the through-hole near the center of the semiconductor wafer 5 penetrates and the filling metal 12B is filled with the second metal wiring. 9B, there is a problem that the through-hole near the outer periphery of the semiconductor wafer 5 does not penetrate and the filling metal 12B 'is not connected to the second metal wiring 9B.

The through hole is formed in the second interlayer insulating film 8
B, if not penetrating through the filling metal 12A '
An insulating silicon dioxide film (S) is provided between the first metal wirings 9A.
iO _Two) Is interposed between the first metal wiring 9A and the second metal wiring 9A.
The resistance value between the metal wires 9B increases. Therefore, the device
The reliability of the electrical characteristics of the
Was. In addition, defective products due to poor conduction
Increase in production yield and equipment manufacturing costs
There was a problem of rising.

The reason that the through-hole does not penetrate in the vicinity of the outer periphery of the semiconductor wafer 5 (in the vicinity of the outer periphery of the wafer holder 1 ') is not due to the difference in etching speed due to the unevenness of the etching pattern as in the microloading phenomenon, but to the following. It is considered that the cause is as follows.

The bias high-frequency power applied from the high-frequency power source 4 to the wafer holder 1 'is uniform,
As shown in FIG. 11A, the power PW of the central part (x = 0) and the outer peripheral part (x = X1) of the wafer holder 1 ′ is set to be constant. At this time, the actual power value in the vicinity of the outer periphery of the wafer holder 1 'is smaller than that in the vicinity of the center, and the state of the gasified plasma 6 depends on the density of the plasma generated near the outer periphery of the wafer holder 1'. Is considered to be lower than the density of the plasma near the center. Therefore, for example, a silicon dioxide film (SiO ₂ ) placed on the wafer holder 1 ′
When examining the distribution of the etching rate of FIG.
As shown in the figure, the center of the wafer holder 1 '(x =
0) to the outer peripheral portion (x = X1), the etching rate decreases, and an ER difference occurs between the center and outer peripheral etching rates.

From the above, for example, a silicon dioxide film (SiO 2)
₂ ) When etching 8, as shown in FIG. 11 (c), through holes 11 B and 1 B formed in silicon dioxide film 8 near the outer periphery (x = X 1) of wafer holder 1 ′.
1C is at the center of the wafer holder 1 '(x =
0) is shallower than the depth of the through hole 11A formed in the silicon dioxide film 8 in the vicinity. At this time, the etching amount near the center of the wafer holder 1 ′ and
Since the difference Δd in the etching amount near the outer periphery is large, the through hole formed in the silicon dioxide film 8 near the outer periphery of the wafer holder 1 ′ does not penetrate, and a conduction failure as shown in FIG. 10 occurs. It is thought that. When the diameter of the semiconductor wafer 5 is increased, a decrease in the etching rate in the vicinity of the outer periphery of the wafer holder 1 ′ is further increased, so that the non-opening of the through hole occurs in the vicinity of the outer periphery of the semiconductor wafer 5. Is likely to become more serious.

Further, the present invention is not limited to the case where a through hole is formed in the silicon dioxide film 8, but also in the case where a first metal wiring 9A and the like on the first interlayer insulating film 8A shown in FIG. Since an excess portion of the metal film formed on the surface of the semiconductor wafer is removed by etching using an etching apparatus as shown in FIG. 9, the metal film on the outer peripheral portion of the semiconductor wafer 5 is not sufficiently removed. There is also a problem that a short circuit occurs between adjacent metal wirings.

An object of the present invention is to provide a method of manufacturing a semiconductor device, comprising the steps of applying electric power to a flat electrode to bring a reactive gas into an ionized state (plasma) and etching a semiconductor wafer on the electrode. It is an object of the present invention to provide a technique capable of preventing poor etching near the outer periphery of a semiconductor wafer (near the outer periphery of an electrode). Another object of the present invention is to
It is an object of the present invention to provide a technique capable of preventing a decrease in an etching rate near an outer periphery of an electrode in a parallel plate type etching apparatus using electrodes on a flat plate. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

The summary of the invention disclosed in the present application is as follows. (1) a first electrode on which a semiconductor wafer is mounted, a second electrode disposed to face the first electrode, and a power source for supplying power to the first electrode; In an etching apparatus for etching a semiconductor wafer by ionizing (plasmaizing) gas molecules between two electrodes, the first electrode electrically separates a plurality of divided electrodes from each other. And a plurality of power sources that supply different power to each of the divided electrodes. (2) In the etching apparatus of (1), the first
The electrode is disk-shaped, and the periphery is divided into concentric annular electrodes.

According to the parallel plate type etching apparatus of (1), the first electrode is divided into a plurality of electrodes. Each of the divided electrodes is integrated via an insulator so as to be electrically separated. In addition, an independent power source is provided for each of the electrodes, so that different amounts of power can be supplied to the respective electrodes. According to the amount of power supplied to the respective electrodes, the first electrode and the The density of the plasma generated in the space between the second electrodes can be partially changed. Therefore, the amount of electric power supplied to the electrode near the outer periphery of the first electrode is made larger than the amount of electric power supplied to the electrode near the center of the first electrode to reduce the actual amount of electric power near the outer periphery of the first electrode. A decrease in plasma density can be suppressed and a decrease in etching rate can be prevented. By preventing the etching rate from decreasing near the outer periphery of the first electrode, the difference in the amount of etching between the periphery of the first electrode and the center is reduced. Etching failure in the vicinity of the outer periphery) can be prevented. In addition, since etching defects near the outer periphery of the semiconductor wafer are reduced, the occurrence rate of defective products is reduced, and the manufacturing yield of the device is improved, so that the manufacturing cost can be reduced.

Further, since the semiconductor wafer is substantially circular and the first electrode is also circular, the constant velocity line of the etching rate spreads concentrically from the center of the first electrode and approaches the outer periphery. It is going down. Also,
The constant velocity line of the etching rate becomes dense near the outer periphery.
For this reason, it is considered that the first electrode is most effective to divide the vicinity of the outer periphery of the first electrode into concentric annular electrodes as in the means (2).

Hereinafter, the present invention will be described in detail along with embodiments (examples) with reference to the drawings. In all the drawings for explaining the embodiments, parts having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

[0021]

(Embodiment) FIGS. 1 and 2 are schematic diagrams showing a schematic configuration of an etching apparatus according to an embodiment of the present invention, and FIG. 1 is a schematic diagram showing a schematic configuration of the entire etching apparatus. FIG. 2A shows the first electrode (wafer holder).
FIG. 2B is a schematic plan view showing a schematic configuration of FIG.
3 is a sectional view taken along line AA ′ of FIG.

In FIG. 1, 1 is a first electrode (wafer holder), 2 is a second electrode (upper electrode), 3 is a vacuum chamber, 3A is a gas supply port, 3B is an exhaust port, 4A is a first power source, 4B is a second power source, 4C is a third power source, 5 is a semiconductor wafer, and 6 is a gas that has been turned into plasma.

As shown in FIG. 1, the etching apparatus of this embodiment faces a first electrode 1 and a second electrode 2 on a flat plate such that the first electrode 1 and the second electrode 2 are parallel to each other. A vacuum chamber 3 provided with a gas supply port 3A and an exhaust port 3B, and a first power source 4A, a second power source 4B, and a third power source 4C connected to the first electrode. A semiconductor wafer 5 on which a predetermined pattern of resist is formed is mounted on the first electrode 1.

The first electrode 1 is, for example, as shown in FIG.
As shown in FIG. 2A and FIG. 2B, the first ring-shaped electrode 1B and the second ring-shaped electrode 1C which are divided into three are formed around the disk-shaped electrode 1A near the center. Have been. The disc-shaped electrode 1A, the first annular electrode 1B, and the first
The ring-shaped electrode 1B and the second ring-shaped electrode 1C are electrically separated by a highly insulating insulator 7 such as a ceramic.

Incidentally, in the first electrode 1 used in the etching apparatus of this embodiment, as shown in FIG.
0, and the x-axis is taken from the center toward the outer periphery of the first electrode 1. At this time, as shown in FIG. 2B, since the disc-shaped electrode 1A is connected to the first power source 4A, the area from the center (x = 0) to the radius X3 (x = X3) is limited. The etching speed is set according to the power supplied from the first power source 4A. Further, since the first annular electrode 1B is connected to the second power source 4B, the annular region from x = X3 to x = X2 has an etching rate corresponding to the power supplied from the second power source 4B. become. Similarly, since the second annular electrode 1C is connected to the third power source 4C, x = X
The annular region from 2 to x = X1 is the second power source 4
The etching rate is determined according to the power supplied from C.

FIGS. 3 to 5 are schematic views for explaining an etching method using the etching apparatus of this embodiment. 3A to 5, reference numeral 8A denotes a first interlayer insulating film;
B is a second interlayer insulating film, 8C is a third interlayer insulating film, 9A is a first metal wiring, 9B is a second metal wiring, 10 is a resist,
1, 11A, 11B, 11C are through holes, 12A,
12B is a filler metal.

In the method of manufacturing a semiconductor device, the steps of etching using the etching apparatus of the first embodiment include:
For example, there are a step of etching silicon (Si), a step of forming a through hole by etching a silicon oxide film (SiO ₂ ), and a step of forming a metal wiring by etching a metal film such as aluminum (Al). However, in the first embodiment, a process of forming a through hole by etching the silicon oxide film will be described as an example, and an etching method using the etching apparatus of the first embodiment will be described with reference to FIGS. I do.

First, as shown in FIG. 3A, a first metal wiring 9A made of aluminum (Al) is formed on a first interlayer insulating film 8A made of a silicon oxide film (SiO ₂ ), and then silicon is formed again. Second interlayer insulating film 8 made of an oxide film
B is formed on the entire surface.

Next, as shown in FIG.
After forming a resist 10 on the interlayer insulating film 8B and patterning it into a predetermined shape, the resist 10 is fixed to the first electrode (wafer holder) 1 of the etching apparatus as shown in FIG. At this time, the etching gas supplied from the gas supply port 3A into the vacuum chamber 3 is, for example,
C ₄ F _{8 and the} like.

While supplying the etching gas, different amounts of power are supplied from the first power source 4A, the second power source 4B, and the third power source 4C, respectively, so that the first electrode 1 and the second electrode The etching gas in the space between the electrodes 2 is turned into plasma. At this time, power PW1 supplied to the disc-shaped electrode 1A, power PW2 supplied to the first annular electrode 1B, and power PW supplied to the second annular electrode 1C
3 is, as shown in FIG. 4A, PW1 <PW
2 <PW3. The power to be supplied is, for example, power PW
1 = 1400 watts (W), power PW2 = 1500 watts (W), and power P3 = 1600 watts (W).

At this time, by increasing the power supplied to the vicinity of the outer periphery of the first electrode 1, even if the actual power amount near the outer periphery of the first electrode is reduced, the power difference from the vicinity of the center is reduced. The first electrode 1 and the second electrode 1
The difference in the density of the plasma 6 generated in the space between the electrodes 2 can be reduced and can be made substantially uniform. for that reason,
The distribution of the etching rate on the first electrode is shown in FIG.
4B, the difference ER between the etching rate in the vicinity of the center and the etching rate in the vicinity of the outer periphery can be reduced, and as shown in FIG. The difference Δd between the depths of the through holes 11C near the outer periphery is reduced.

Therefore, as shown in FIG. 3B, the through hole 11 of the second interlayer insulating film 8B can also open the second interlayer insulating film near the outer periphery to the first metal wiring 9A.
The diameter of the hole can be prevented from being reduced.

Next, as shown in FIG. 5A, the through hole 11 is filled with a metal material, and a second metal wiring 9B is formed on the second interlayer insulating film 8B. Also at this time, the etching can be performed by supplying a mixed gas of Cl ₂ and BCl ₃ as an etching gas using the etching apparatus of the first embodiment. At this time, the through hole 11 connecting the first metal wiring 9A and the second metal wiring 9B is formed.
Is directly connected to the first metal wiring 9A and the second metal wiring 9B, so that the silicon dioxide film intervenes to increase the resistance value and prevent a decrease in the reliability of the electrical characteristics of the device. Can be.

As described above, according to this embodiment,
In a parallel plate type plasma etching apparatus, the vicinity of the outer periphery of a first electrode (wafer holder) to which power for generating plasma is applied is divided into a plurality of concentric annular electrodes, and each electrode is an independent power source. And the amount of power applied to the vicinity of the outer periphery of the first electrode is made larger than the amount of power applied to the vicinity of the center. Can be reduced. Therefore, the difference between the density of the plasma generated near the center of the first electrode and the density of the plasma generated near the outer periphery is reduced, and a decrease in the etching rate near the outer periphery of the first electrode can be suppressed. . Accordingly, the etching rate in the vicinity of the outer periphery of the first electrode is decreased, so that the contact hole is not opened due to insufficient etching in the vicinity of the outer periphery of the semiconductor wafer placed on the first electrode, or the wiring is short-circuited. , And a decrease in the reliability of the device can be prevented. In addition, since the occurrence rate of defective products due to reduced reliability can be reduced,
The production yield is improved, and the production cost can be reduced.

In the above embodiment, the step of opening a contact hole in the silicon oxide film (SiO ₂ ) has been described by way of example. However, the present invention is not limited to this, and etching of silicon (Si) or aluminum (Al) It goes without saying that the etching apparatus of the first embodiment can be used for the etching.

FIG. 6 is a schematic diagram for explaining a modification of the etching apparatus of the above embodiment. In the etching apparatus of the embodiment, the first electrode (wafer holder) 1
Is divided into three electrodes, a disk-shaped electrode 1A, a first ring-shaped electrode 1B, and a second ring-shaped electrode 1C, but is not limited thereto. For example, as shown in FIG. Between the first annular electrode 1A and the first annular electrode 1B, a third annular electrode 1D and a fourth annular electrode 1E may be further formed and divided into five electrodes. Also at this time, an independent high-frequency power source is connected to each of the five electrodes, and as shown in FIG. 6B, power is supplied to each electrode such that the amount of power increases toward the outer periphery. Thereby, the first electrode 1
As shown in FIG. 6C, the difference between the etching rate in the vicinity of the center of the first electrode 1 and the etching rate in the vicinity of the outer periphery of the first electrode 1 becomes small, and the distribution of the etching rate becomes gentle. Therefore, for example, in the step of forming a contact hole in the silicon oxide film (SiO ₂ ), the rate of non-opening is further reduced, the variation in the opening area (hole diameter) is reduced, and the electrical resistance and the like are reduced. Variations in characteristics can be reduced.

FIG. 7 is a schematic diagram for explaining another modification of the etching apparatus of the above embodiment. In the etching apparatus of the embodiment, the first electrode (wafer holder)
The first high-frequency power source 4 is provided to each of the disc-shaped electrode 1A, the first annular electrode 1B, and the second
A, a second high frequency power source 4B, and a third high frequency power source 4C are connected, and the amount of power applied to each electrode is set and controlled independently by each high frequency power source. As shown in FIG. 7, by using the power control means 13,
The amounts of power applied from the first high-frequency power source 4A, the second high-frequency power source 4B, and the third high-frequency power source 4C can be collectively set and controlled.

As described above, the present invention has been specifically described based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Of course.

FIG. 8 is a schematic diagram for explaining an application example of the etching apparatus of the above embodiment. In the etching apparatus of the above embodiment, the first electrode (wafer holder) 1 and the second electrode (upper electrode) 2 are disposed so as to face each other in parallel, and between the first electrode 1 and the second electrode 2. Although the etching gas is converted into plasma using the generated electric field, the present invention is not limited to this, and can be applied to a microwave etching apparatus using a magnetron.

As shown in FIG. 8, the microwave etching apparatus includes a first electrode (wafer holder) 1 provided on a pedestal 14, a coil 15 provided around the first electrode 1, and a magnetron. 16, a supply port 17, and a bell jar 18.

As described in the first embodiment, the first electrode 1 of the microwave etching apparatus shown in FIG. 8 is divided into concentric annular electrodes at the outer peripheral portion. High frequency power source 4A, second high frequency power source 4
B, the third high frequency power source 4C is connected.

In the microwave etching apparatus, first, the semiconductor wafer 5 to be etched is placed in a bell jar 18.
The first high frequency power source 4 is placed on the first electrode 1
A, a negative (minus) high voltage is applied to the first electrode from each of the second high frequency power source 4B and the third high frequency power source 4C. Further, the coil 15 allows the semiconductor wafer 5
A magnetic field for increasing the etching efficiency is generated in the bell jar 18. At this time, the magnetron 16
When a direct current is applied with the side as the anode and the first electrode 1 as the cathode, the electrons emitted from the magnetron 16 are accelerated at a high speed, supplied to the bell jar 18 and adsorbed on the surface of the semiconductor wafer 5. Etched.

Also in the microwave etching apparatus as shown in FIG. 8, the first electrode 1 is divided into a plurality of electrodes, and the power applied to the outer peripheral portion is made larger than the power applied near the center. In addition, since a decrease in the actual power amount near the outer periphery of the first electrode 1 can be suppressed, and a difference from the actual power amount near the center, in other words, a difference in the etching rate can be reduced, the outer periphery of the semiconductor wafer 5 can be reduced. Can be prevented from deteriorating due to poor etching at the step.
Further, the rate of defective products due to poor etching near the outer periphery is reduced, and the production yield is improved, so that the production cost can be reduced.

[0044]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows. (1) In a method of manufacturing a semiconductor device, the method includes a step of applying a power to a plate-shaped electrode to bring a reactive gas into an ionized state (plasma) and etching a semiconductor wafer on the electrode. It is possible to prevent poor etching near the outer periphery of the electrode. (2) In a parallel plate type etching apparatus using a plate-shaped electrode, it is possible to prevent a decrease in the etching rate near the outer periphery of the electrode.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of an entire etching apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic plan view and a cross-sectional view illustrating a schematic configuration of a first electrode used in the etching apparatus of the present embodiment.

FIG. 3 is a schematic diagram for explaining an etching method using the etching apparatus of the present embodiment.

FIG. 4 is a schematic diagram for explaining an etching method using the etching apparatus of the present embodiment.

FIG. 5 is a schematic diagram for explaining an etching method using the etching apparatus of the present embodiment.

FIG. 6 is a schematic diagram for explaining a modification of the etching apparatus of the present embodiment.

FIG. 7 is a schematic diagram for explaining another modification of the etching apparatus of the present embodiment.

FIG. 8 is a schematic diagram for explaining an application example of the etching apparatus of the embodiment.

FIG. 9 is a schematic diagram showing a schematic configuration of a conventional etching apparatus.

FIG. 10 is a schematic diagram for explaining a problem of a conventional etching apparatus.

FIG. 11 is a schematic diagram for explaining a problem of a conventional etching apparatus.

[Explanation of symbols]

1, 1 ': first electrode (wafer holder), 1A: disc-shaped electrode, 1B: first annular electrode, 1C: second annular electrode, 1D
... 3rd annular electrode, 1E ... 4th annular electrode, 2 ... second electrode (upper electrode), 3 ... vacuum chamber, 3A ... gas supply port, 3B ... exhaust port, 4 ... high frequency power source, 4A ... first high frequency Power source, 4B: second high frequency power source, 4C: third high frequency power source, 5: semiconductor wafer, 6: gas (gas) converted into plasma, 7: insulator, 8: silicon dioxide film, 8A ...
First interlayer insulating film, 8B: second interlayer insulating film, 8C: third interlayer insulating film, 9A: first metal wiring, 9B: second metal wiring,
Reference Signs List 10 resist, 11, 11A, 11B, 11C through hole, 12A, 12A ', 12B, 12B' filled metal, 13 power control unit, 14 pedestal, 15 coil, 16 magnetron, 17 supply port , 18 ... bell jar.

Claims (3)

[Claims] A first electrode on which a semiconductor wafer is mounted; a second electrode disposed to face the first electrode; and a power source for supplying power to the first electrode. And an etching apparatus for ionizing (plasmatizing) gas molecules between the second electrodes and etching the semiconductor wafer, wherein the first electrode electrically connects the plurality of divided electrodes and each of the divided electrodes to each other. An etching apparatus, comprising: a plurality of power sources configured to separate power into each of the divided electrodes. 2. The etching apparatus according to claim 1, wherein the first electrode has a disk shape, and the periphery of the first electrode is divided into concentric annular electrodes. 3. A semiconductor wafer is placed on the first electrode, and an etching gas is supplied to a space on the semiconductor wafer.
Means for bringing the gas supplied to the space above the semiconductor wafer into an ionized state (plasma), and supplying power to the first electrode to cause a chemical reaction between the gas in the ionized state and the surface of the semiconductor wafer. A method of manufacturing a semiconductor device having a step of etching the semiconductor wafer, wherein the semiconductor wafer is placed on the first electrode divided into a plurality of electrodes, and an amount of power applied near an outer periphery of the first electrode is reduced. Applying a power to the plurality of divided electrodes so as to be larger than an amount of power applied near a center of the first electrode.