JP2002008520A - Field radiation type electron source and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field radiation type electron source in which the fluctuation of electron emitting direction is smaller than the conventional method and its manufacturing method. SOLUTION: An intense-field drift layer 6 having a porous polycrystalline silicon layer is formed on the conductive substrate 100 and a conductive film 7 is provided on the intense-field drift layer 6. The drift section 6a of the intense-field drift layer 6 is formed by smoothing the surface of a polycrystalline silicon layer 3 and then by making porous by anodizing and further by oxidizing by a rapid thermal oxidization technology.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type electron source which emits an electron beam by field emission using a semiconductor material, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as disclosed in Japanese Patent Application Laid-Open No. 8-250766, a porous semiconductor layer is formed by using a single-crystal semiconductor substrate such as a silicon substrate and anodizing one surface of the semiconductor substrate. (Porous silicon layer)
, A metal thin film is formed on the porous semiconductor layer, and a voltage is applied between the semiconductor substrate and the metal thin film to emit electrons. Elements) are known.

The field emission type electron source described in the above publication is difficult to increase in area because a single-crystal semiconductor substrate is indispensable, and requires a large-area electron source such as a flat display device. It is not suitable for

[0004] On the other hand, the present inventors have disclosed in Japanese Patent Application No.
Japanese Patent Application No. 0-272340, Japanese Patent Application No. 10-272342, and the like have proposed a field emission type electron source capable of increasing the area. These electron sources rapidly oxidize a porous polycrystalline semiconductor layer (for example, a porous polycrystalline silicon layer) between a conductive substrate and a conductive thin film by a rapid thermal oxidation (RTO) technique. The structure has a structure in which a strong electric field drift layer is formed, and electrons injected from the conductive substrate into the strong electric field drift layer drift in the strong electric field drift layer. As shown in FIG. 9, for example, this kind of field emission type electron source has a strong electric field drift layer 6 made of an oxidized porous polycrystalline silicon layer on the main surface side of an n-type silicon substrate 11 as a conductive substrate. A conductive thin film 7 made of a metal thin film is laminated via a drift portion 6 a (in the configuration shown, the entire strong electric field drift layer 6 functions as the drift portion 6 a), and the ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 11. It is formed in a laminated shape.

In order to emit electrons from the field emission type electron source shown in FIG. 9, a collector electrode 12 is provided opposite to the conductive thin film 7 as shown in FIG. Between the conductive thin film 7 and the n-type silicon substrate 11 so that the conductive thin film 7 is on the higher potential side with respect to the n-type silicon substrate 11 (the ohmic electrode 2). While applying the voltage Vps,
DC voltage Vc is applied between collector electrode 12 and conductive thin film 7 so that collector electrode 12 is on the higher potential side with respect to conductive thin film 7. If the DC voltages Vps and Vc are appropriately set, the electrons injected from the n-type silicon substrate 11 drift in the strong electric field drift layer 6 and are emitted through the conductive thin film 7 (the dashed line in FIG. The flow of electrons e- emitted through the conductive thin film 7 is shown). A material having a small work function is used for the conductive thin film 7, and the thickness of the conductive thin film 7 is set to about 10 to 15 nm.

As shown in FIG. 11, the drift portion 6a of the strong electric field drift layer 6 includes a columnar grain 21 made of polycrystalline silicon, a thin silicon oxide film 22 formed on the surface of the grain 21, A microcrystalline silicon 23 of nanometer order interposed between the polycrystalline silicon grains 21 and a silicon oxide film formed on the surface of the microcrystalline silicon 23 and having a thickness smaller than the crystal grain size of the microcrystalline silicon 23 24 at least. It is considered that the surface of the grains contained in the polycrystalline silicon before the above-described processing is made porous in the drift portion 6a, and the crystal state is maintained by the remaining grains 21. Therefore, most of the electric field applied to the drift portion 6a passes through the silicon oxide film 24 intensively, and the injected electrons e ⁻ are accelerated by the strong electric field passing through the silicon oxide film 24 between the grains 21 and are accelerated. Arrow A
(Upward in FIG. 11). The electrons that have reached the surface of the drift portion 6a are considered to be hot electrons and are easily tunneled through the conductive thin film 7 and discharged into a vacuum.

In the field emission type electron source having the above configuration, the current flowing between the conductive thin film 7 and the ohmic electrode 2 is called a diode current Ips, and the current flowing between the collector electrode 12 and the conductive thin film 7 Is called the emission electron current Ie (see FIG. 10), the diode current Ip
Ratio of emission electron current Ie to s (= Ie / Ips)
The larger the value, the higher the electron emission efficiency. In this field emission type electron source, electrons can be emitted even when the DC voltage Vps applied between the conductive thin film 7 and the ohmic electrode 2 is as low as about 10 to 20 V. In addition, this field emission type electron source has a small dependence of the electron emission characteristics on the degree of vacuum, does not cause a popping phenomenon during electron emission, and can stably emit electrons with high electron emission efficiency.

In the above configuration example, the n-type silicon substrate 11 is used as the conductive substrate. However, instead of the n-type silicon substrate 11, a conductive material such as an ITO film is formed on an insulating substrate such as a glass substrate. A substrate on which a layer is formed can be used. When a conductive substrate having such a structure is used, the area of the electron source can be increased and the cost can be reduced. FIG. 12 shows an example of a field emission type electron source using a conductive substrate having such a configuration. The field emission type electron source shown in FIG. 12 uses a conductive substrate including an insulating substrate 13 made of a glass substrate and a conductor layer 8b made of an ITO film formed on the insulating substrate 13. A conductive thin film 7 made of a metal thin film is laminated on the conductor layer 8b via the strong electric field drift layer 6 (that is, the drift layer 6a). In this field emission type electron source, after the strong electric field drift layer 6 deposits a non-doped polycrystalline silicon layer on the conductor layer 8b, the polycrystalline silicon layer is made porous by anodizing treatment, and further oxidized or It is formed by nitriding.

In order to emit electrons from the field emission type electron source shown in FIG. 12, a collector electrode 12 disposed opposite to the conductive thin film 7 is provided similarly to the field emission type electron source shown in FIG. In other words, as shown in FIG. 13, in a state where the space between the conductive thin film 7 and the collector electrode 12 is evacuated, the conductive thin film 7 is placed on the high potential side with respect to the conductive layer 8b. DC voltage Vps is applied between the conductive layer 8b and the collector electrode 12 and the conductive thin film 7 so that the collector electrode 12 is on the higher potential side with respect to the conductive thin film 7.
And a DC voltage Vc is applied. Each DC voltage Vps,
If Vc is appropriately set, electrons injected from the conductive layer 8b drift in the strong electric field drift layer 6 and are emitted through the conductive thin film 7 (note that the dashed line in FIG. Showing the flow of electrons e ⁻ ). When the field emission type electron source shown in FIG. 12 is applied to a display or the like, the conductor layer 8b is patterned in a stripe shape, and the conductive thin film 7 is formed in a stripe shape perpendicular to the conductor layer 8b. I just need.

[0010]

[SUMMARY OF THE INVENTION] In the field emission electron source having a strong electric field drift layer 6 described above, electrons to the normal direction of the surface of the drift region 6a e ^- characterized in that the release I have. However, since the polycrystalline silicon is made porous by anodic oxidation treatment and oxidized by nitriding or rapid thermal oxidation to form the drift portion 6a, the polycrystalline silicon is deposited on the conductive substrate at the time of deposition. As a result of the growth of the grains, irregularities are formed on the surface of the polycrystalline silicon layer.
When the voltage is applied between the conductive substrate and the conductive thin film 7, the drift portions 6a
An equipotential surface is formed almost along the irregularities on the surface of
^- becomes large variations in release direction is, high-definition displays such as electronic e ^- allowable angle range of the emission direction there is a problem that application to a narrow device is difficult. That is, as shown in FIG.
In the case where the degree of growth differs in the plane, the drift portion 6 formed on the conductive substrate 100 is formed as shown in FIG.
Since irregularities on the surface of a is formed, and FIG. 14 (b) to the electronic as shown e ^- turned in a direction inclined from the (upward in FIG. (b)) emission direction thickness direction of the conductive substrate 100 There was a defect that would. FIG. 14A shows an example in which the polycrystalline silicon layer 3 formed on the conductive substrate 100 is made porous halfway in the thickness direction, and FIG. The same components are denoted by the same reference numerals.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a field emission type electron source having a smaller variation in the electron emission direction than in the past, and a method of manufacturing the same.

[0012]

According to the first aspect of the present invention, there is provided a conductive substrate, a strong electric field drift layer formed on one surface side of the conductive substrate, and the strong electric field drift layer. A conductive thin film formed on the layer, and the electron injected from the conductive substrate drifts through the strong electric field drift layer by applying a voltage with the conductive thin film as a positive electrode with respect to the conductive substrate. A strong field drift layer, characterized in that the strong electric field drift layer has a porous semiconductor layer with a smooth surface oxidized or nitrided, and the surface of the porous semiconductor layer is smooth. Therefore, when a voltage is applied to the conductive thin film as a positive electrode with respect to the conductive substrate, an equipotential surface formed near the surface of the porous semiconductor layer becomes substantially parallel to one surface of the conductive substrate.
The variation in the direction of electron emission is smaller than before,
It can be applied to a device having a narrow allowable angle range of the electron emission direction such as a high-definition display.

According to a second aspect of the present invention, in the first aspect of the present invention, the porous semiconductor layer has a substantially uniform thickness in a porous region. Since an electric field acts almost uniformly on the porous region when a voltage is applied, the equipotential surface in the porous semiconductor layer becomes substantially parallel to the conductive substrate, and the dispersion of the electron emission direction and The unevenness in the amount of emitted electrons can be reduced.

According to a third aspect of the present invention, in the first or second aspect, the porous semiconductor layer has a surface roughness less than or equal to a thickness of the porous semiconductor layer. It is.

According to a fourth aspect of the present invention, in the first to third aspects of the present invention, the angle between the normal line of the surface and the virtual surface orthogonal to the thickness direction of the conductive substrate is set in the porous semiconductor layer. This is a preferred embodiment, characterized in that the electrons are distributed within an allowable angle range defined by the arrival surface of the emitted electrons.

According to a fifth aspect of the present invention, in the first to fourth aspects of the present invention, since the porous semiconductor layer is made of porous polycrystalline silicon, the dependence of the electron emission characteristics on the degree of vacuum is small and the electron emission characteristics are small. Occasionally, electrons can be stably emitted with high efficiency without occurrence of a popping phenomenon.

According to a sixth aspect of the present invention, there is provided the method for manufacturing a field emission type electron source according to the first aspect, wherein the semiconductor layer formed on one surface of the conductive substrate is made porous by anodizing. Prior to forming a porous semiconductor layer, characterized by comprising a smoothing step of smoothing the surface of the semiconductor layer, wherein the surface smoothed semiconductor layer is made porous by anodizing treatment Forming a porous semiconductor layer, it is possible to make the surface of the strong electric field drift layer smoother than before, and to provide a field emission type electron source with a smaller variation in the direction of electron emission than before. can do.

According to a seventh aspect of the present invention, in the sixth aspect, the smoothing step is a step of smoothing the surface of the semiconductor layer by an electrolytic polishing method. Since the surface of the semiconductor layer is smoothed by the electrolytic polishing method, there is no need to prepare a separate device for smoothing, and the surface of the semiconductor layer can be smoothed at low cost, resulting in an increase in cost. Can be suppressed.

According to an eighth aspect of the present invention, in the sixth aspect, the smoothing step is a step of smoothing the surface of the semiconductor layer by a reactive ion etching method. When a mask material layer such as silicon or silicon nitride film is deposited, and the mask material layer is patterned by reactive ion etching to form a mask and then anodizing treatment is performed, the mask material layer is patterned at the time of patterning the mask material layer. Since the surface of the semiconductor layer can be smoothed in succession to the etching, there is no need to prepare a separate device for smoothing, and the surface of the semiconductor layer can be smoothed at low cost. As a result, cost increase can be suppressed.

According to a ninth aspect of the present invention, in the sixth to eighth aspects of the present invention, the anodic oxidation treatment is a treatment in which the thickness of the porous region is substantially uniform. A smaller field emission power supply can be provided.

According to a tenth aspect of the present invention, in the ninth aspect of the present invention, a substrate is used in which a conductive layer having corrosion resistance to hydrofluoric acid used at the time of anodic oxidation treatment is provided on one surface of the insulating substrate. The anodic oxidation treatment is a treatment for making the semiconductor layer porous so that the thickness of the porous region is substantially equal to the distance between the conductive thin film and the conductive substrate. Since the thickness of the porous region can be made substantially uniform without adding, the cost can be prevented from increasing.

According to an eleventh aspect of the present invention, in the ninth aspect of the present invention, the anodic oxidation treatment includes a step of forming a pulse between the conductive substrate and the counter electrode such that the thickness of the porous region becomes substantially uniform. Since the current is alternately reversed in polarity and energized, the thickness of the porous region can be made substantially uniform without adding an anodizing treatment and a separate step,
The cost can be prevented from increasing.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) In this embodiment, as shown in FIG. 3, a glass substrate 14 is provided opposite to a field emission type electron source (hereinafter, referred to as an electron source) 10. And
An example in which a display device is configured by providing a collector electrode 12 and a phosphor layer 15 on a surface of a glass substrate 14 facing an electron source 10 will be described. The phosphor layer 15 is applied on the surface of the collector electrode 12 and emits visible light by electrons emitted from the electron source 10. Further, the glass substrate 14 is separated from the electron source 10 by a spacer (not shown), and an airtight space formed between the glass substrate 14 and the electron source 10 is evacuated.

In the electron source 10 used in this embodiment, as shown in FIGS. 3 to 5, a plurality of n-type regions 8a as conductor layers are formed in a stripe shape on the main surface side of a p-type silicon substrate 16. Between the drift portion 6a and the drift portion 6a made of a porous polycrystalline silicon layer, which is an oxidized porous semiconductor layer formed in a stripe shape so as to overlap with each of the n-type regions 8a. A strong electric field drift layer 6 having a separation portion 6b made of a polycrystalline silicon layer which is substantially flush with the drift portion 6a, and n on the strong electric field drift layer 6 over the drift portion 6a and the separation portion 6b.
And a conductive thin film 7 composed of a plurality of conductive thin films (for example, a gold thin film) formed in a stripe shape in a direction orthogonal to the shape region 8a.

The electron source 10 described above has a drift of the strong electric field drift layer 6 between an n-type region 8a formed in a stripe shape and a conductive thin film 7 formed in a stripe shape orthogonal to the n-type region 8a. Since the portion 6a is sandwiched, a pair of the conductive thin film 7 and the n-type region 8a is appropriately selected, and a voltage is applied between the selected pair. The strong electric field acts only on the drift portion 6a at the portion corresponding to the point of intersection, and electrons are emitted. That is, this corresponds to disposing an electron source at a lattice point of a lattice formed by the conductive thin film 7 and the n-type region 8a, and by selecting a set of the conductive thin film 7 and the n-type region 8a to which a voltage is applied. Electrons can be emitted from desired lattice points. The contact to the n-type region 8a is formed by etching the end of the drift portion 6a to expose a part of the surface of the n-type region 8a as shown in FIG. Connected to the circuit. The n-type region 8
In a, the carrier concentration is 1 × 10 ^{18 to} 5 × 10 ¹⁹ cm ⁻³ , and the voltage applied between the n-type region 8a and the conductive thin film 7 is about 10 to 30V.

The manufacturing process of the electron source 10 according to the present embodiment will be described below. First, in order to obtain the structure shown in FIG. 6A, a mask for thermal diffusion or ion implantation is provided on the main surface of the p-type silicon substrate 16, and then the p-type silicon substrate is formed by thermal diffusion technology or ion implantation technology. By introducing a dopant such as phosphorus (P) into the main surface side of the semiconductor substrate 16, a striped n-type region 8 a is formed,
Finally, the mask is removed.

Next, on the main surface of the p-type silicon substrate 16 on which the n-type region 8a has been formed, a film thickness of 1.
By depositing a non-doped polycrystalline silicon layer 3 of 5 μm, the structure shown in FIG. 6B is obtained. However, the method of forming the polycrystalline silicon layer 3 is not limited to the LPCVD method. For example, after forming an amorphous silicon layer by a sputtering method or a plasma CVD method, annealing the amorphous silicon layer is performed. May be used to form the polycrystalline silicon layer 3 by crystallization.

Thereafter, a photoresist layer as a mask layer is applied and formed on the polycrystalline silicon layer 3 and a portion above the n-type region 8a is opened by photolithography to form a portion as shown in FIG. Then, a resist layer 9 patterned in a stripe shape is formed.

Further, after forming an ohmic electrode (not shown) on the back surface of the p-type silicon substrate 16, a smoothing step for smoothing the surface of the polycrystalline silicon layer 3 as a semiconductor layer is performed by using the resist layer 9 as a mask. Then, a porous polycrystalline silicon layer, which is a porous semiconductor layer, is formed on the polycrystalline silicon layer 3 by performing an anodic oxidation treatment. The smoothing step is performed by an electrolytic polishing method using the apparatus shown in FIG. 7 used in the anodic oxidation treatment. That is, the processing bath 31 into which the electrolytic solution obtained by mixing hydrofluoric acid, ethanol, and water in an appropriate amount is put into a constant temperature water bath 32 to control the temperature of the electrolytic solution, and as shown in FIG. The p-type silicon substrate 16 of the processing portion 30 on which the polycrystalline silicon phase 3 is formed
And the counter electrode 33 as a platinum electrode are immersed in an electrolytic solution, and a current is applied between the p-type silicon substrate 16 and the counter electrode 33 for an appropriate energizing time. By setting the current density at this time to a current density of 1.5 mA / cm ² or less (the current value of the supplied current is controlled by the galvanostat 36), the polycrystalline silicon layer 3 is not made porous. The surface of the polycrystalline silicon layer 3 is electropolished, so that the surface of the polycrystalline silicon layer 3 can be smoothed. That is, it is possible to reduce the surface roughness due to the unevenness of the surface of the polycrystalline silicon layer 3 caused by the growth of the grains during the deposition of the polycrystalline silicon layer 3.

In the anodic oxidation treatment, a treatment tank 31 into which an etchant in which a proper amount of hydrofluoric acid, ethanol and water are mixed is put into a constant temperature water tank 32 to control the temperature of the electrolytic solution. The p-type silicon substrate 16 of the processed object 30 and the counter electrode 33 which is a platinum electrode are immersed in an electrolytic solution, and electricity is supplied between the p-type silicon substrate 16 and the counter electrode 33. During this time, the lamp 3 is placed on the exposed portion of the polycrystalline silicon layer 3.
Light irradiation from step 4 is performed. p-type silicon substrate 16 and counter electrode 3
3 is controlled by the function generator 35 and the galvanostat 36. That is, the function generator 35 controls the polarity and duration of the current flow, and the galvanostat 36 controls the current value of the current flow. In the current pattern in the present embodiment, a period in which the p-type silicon substrate 16 is a positive electrode and a period in which the p-type silicon substrate 16 is a negative electrode are alternately provided, and a pulse-like current is supplied in each period.

Here, the p-type silicon substrate 16 is made porous.
, And current flows easily in the porous region. On the other hand, during the period in which the p-type silicon substrate 16 is used as a negative electrode, gas by electrolysis is generated in the vicinity of the region where the porous structure is formed. Become. In other words, in the portion where the progress of the porosity is fast during the period in which the p-type silicon substrate 16 is used as the positive electrode, the progress is suppressed at the time of the next porosity. By repeating such an operation, the porous region has a substantially uniform thickness.

The energizing period (ie, pulse width) per pulse current and the current density per pulse are appropriately set according to the composition of the etchant and the temperature of the etchant. That is, the amount of charge at the time of anodizing treatment is adjusted by the composition of the etchant and the temperature of the etchant. When an etchant obtained by mixing hydrofluoric acid, ethanol, and water is used as described above, the temperature of the etchant is controlled in a temperature range from 0 ° C. to room temperature, and during the period when the p-type silicon substrate 16 is used as a positive electrode, Current density is 1 to 200m
It is desirable to supply a pulsed current so that the current density becomes −2 to −100 mA / cm ² during the period when the A / cm ² and the p-type silicon substrate 16 are used as a negative electrode. In addition, it is desirable that the time width of the pulsed current be 1 second or less in the period during which the positive electrode is used.

The porous polycrystalline silicon layer 5 in the form of stripes is formed by the anodic oxidation treatment as described above. Thereafter, the structure shown in FIG. 6D is obtained by removing the resist layer 9. However, the porous layer is formed only halfway in the thickness direction of the polycrystalline silicon layer 3. In addition, by alternately changing the energizing direction during the anodizing process and energizing the current in a pulsed manner, as shown in FIG.
It becomes possible to make the thickness of the porous region Dp substantially uniform.

After the anodic oxidation treatment, the porous polycrystalline silicon layer 5 is subjected to rapid thermal oxidation (RTO) in a dry oxygen atmosphere using a lamp annealing apparatus, so that the drift composed of the oxidized porous polycrystalline silicon layer is performed. The portion 6a is formed, and the structure shown in FIG. 6E is obtained. However, the oxidized porous polycrystalline silicon layer in the drift portion 6a is formed halfway in the thickness direction.

After that, on the strong electric field drift layer 6 having the drift portion 6a and the separation portion 6b, by using a metal mask having a stripe-shaped opening pattern by an evaporation method.
The striped conductive thin film 7 made of a gold thin film is formed, and the electron source 10 having the structure shown in FIG. 6F is obtained. The conductive thin film 7 has a thickness of 10 nm. Conductive thin film 7
As a patterning method, a photolithography technique and an etching technique may be used, or a photolithography technique and a lift-off technique may be used.

By the way, in the above-mentioned conventional field emission type electron source, as shown in FIG. 14, the thickness of the porous region Dp in the drift portion 6a is not uniform. This is because, in a conventional anodic oxidation treatment, an object to be processed in which a polycrystalline silicon layer is formed on a conductive substrate is immersed in an electrolytic solution together with a counter electrode, and the conductive layer 8b of the conductive substrate is used as a positive electrode. This is considered to be due to the fact that a constant current is continuously applied between the counter electrode and the counter electrode. In other words, the rate at which polycrystalline silicon is made porous varies.
This is because charges are concentrated on a portion that has been previously made porous, and when a constant current is continuously applied, the formation of a porous material around an area where an electric field is concentrated is intensively promoted. it is conceivable that.

As described above, in the drift portion 6a, the electric field is the strongest in the silicon oxide film 24 formed on the surface of the microcrystalline silicon 23 existing in the porous region Dp. If the thickness of Dp is non-uniform, the electric field intensity in each region of the strong electric field drift layer 6 varies. That is, the conductive thin film 7
Cannot be uniformly emitted from the entire surface of the conductive thin film 7, and the energy of the electrons emitted from the conductive thin film 7 has a distribution depending on the location.

As a result, if the conventional field emission type electron source is used as the electron source of the display device, the screen of the display device will have uneven brightness. Further, if the thickness of the porous region Dp has a distribution as shown in FIG. 14, the portion where the electric field strength is small increases inside the drift portion 6a, and in such a portion, the emission of electrons in an extreme case. In some cases, the electron emission efficiency of the electron source as a whole cannot be sufficiently increased. If the electron emission efficiency of the electron source of the display device is low, the brightness cannot be increased and the screen becomes dark.

However, in the present embodiment, as described above, a pulse-like current is applied in the anodizing process for forming the drift portion 6a, and the polarity at the time of energization is alternately inverted, so that the drift portion 6a The thickness of the porous region Dp can be made substantially uniform. As a result, in the drift portion 6a selected as a set of the n-type region 8a and the conductive thin film 7, electrons can be emitted from almost the entire surface, and the porous region Dp
As compared with the case where the thickness of the layer is not uniform, the electron emission efficiency is increased and the amount of emitted electrons is increased.

In this embodiment, before the polycrystalline silicon layer 3 as a semiconductor layer is made porous by anodizing treatment,
Since a smoothing step for smoothing the surface of the polycrystalline silicon layer 3 is provided, the surface of the drift portion 6a becomes smooth. Therefore, as shown in FIG.
Since the surface of the drift portion 6a formed on one surface side of the substrate is smooth (that is, the surface of the oxidized porous polycrystalline silicon layer is smooth), the voltage is applied by using the conductive thin film 7 as a positive electrode with respect to the conductive substrate 100. Since the equipotential surface formed in the vicinity of the surface of the drift portion 6a when the voltage is applied becomes substantially parallel to one surface of the conductive substrate, the electrons e ^{− as} shown in FIG.
Is emitted in the thickness direction of the conductive substrate 100 (FIG.
, The variation in the electron emission direction is smaller than in the past, and it is possible to apply to a device such as a high-definition display having a narrow allowable angle range of the electron emission direction. In addition, since the oxidized porous polycrystalline silicon layer has a substantially uniform thickness in the porous region Dp, the porous polycrystalline silicon layer becomes porous when the conductive thin film 7 is applied to the conductive substrate 100 as a positive electrode. Since the electric field acts almost uniformly on the converted region Dp, the equipotential surface in the drift portion 6a becomes substantially parallel to the conductive substrate, and it is possible to reduce the variation in the electron emission direction and the unevenness of the electron emission amount. it can.

Here, it is desirable that the oxidized porous polycrystalline silicon layer has a surface roughness equal to or less than the thickness of the porous polycrystalline silicon layer. To increase the electron emission efficiency, it is desirable to reduce the thickness of the drift portion 6a, and it is necessary to reduce the surface roughness as the thickness of the drift portion 6a decreases. In short, the drift part 6a
Is thicker, the equipotential surface near the surface becomes almost parallel to the surface of the conductive substrate 100 even if the surface has irregularities. However, when the thickness of the drift portion 6a is smaller, Since the equipotential surface near the surface is formed, it is necessary to reduce the allowable value of the surface roughness as the thickness of the drift portion 6a decreases.

The oxidized porous polycrystalline silicon layer in the drift portion 6a is formed by a method using the surface normal and the conductive substrate 100.
Are distributed within an allowable angle range defined by a plane of arrival of the emitted electrons (the surface of the phosphor layer 15 in the present embodiment). Here, the permissible angle range means the permissible angle range with respect to the electron emission direction when realizing a high-definition display.

Although the resist layer 9 was used as a mask during the anodic oxidation treatment, a silicon oxide film or a silicon nitride film formed in a stripe shape may be used as the mask, or a silicon oxide film or a silicon nitride film may be used. In this case, the step of removing the mask after the anodic oxidation treatment is unnecessary. In the case where a silicon oxide film or a silicon nitride film formed in a stripe shape is used as a mask, a mask material layer made of a silicon oxide film or a silicon nitride film is patterned by a reactive ion etching method, and is continuously polycrystalline. Since the surface of the silicon layer 3 can be smoothed, there is no need to prepare a separate apparatus for smoothing, and the surface of the polycrystalline silicon layer 3 before the anodic oxidation treatment can be smoothed at low cost. As a result, an increase in cost can be suppressed.

In this embodiment, the p-type silicon substrate 16 is used as the conductive substrate and the n-type region 8a is used as the conductive layer. However, the conductive substrate is limited to the p-type silicon substrate. However, the conductor layer also has the n-type region 8a.
However, the present invention is not limited to this. For example, a substrate provided with a conductor layer made of a metal thin film such as chromium on an insulating substrate such as glass may be used as the conductive substrate. The strong electric field drift layer 6 is formed by oxidizing the porous polycrystalline silicon layer 5. However, the strong electric field drift layer 6 may be formed by nitriding the porous polycrystalline silicon layer 5. The drift portion 6a may be formed by anodizing treatment in which the polarity of the pulsed current is alternately reversed as described above in any case. Thus, the thickness of the porous region Dp in the drift portion 6a can be made substantially uniform. The material of the conductive thin film 7 only needs to have a small work function. In addition to gold, aluminum, chromium, tungsten, nickel, platinum, or an alloy of these metals can be used. Further, the thickness of the conductive thin film 7 is set to 10 nm, but the thickness can be appropriately selected.

(Second Embodiment) In this embodiment, a glass substrate provided with a platinum thin film as a conductor layer on one surface is used as a conductive substrate. The material of the glass substrate is selected from quartz glass, non-alkali glass, low alkali glass, and soda lime glass according to the processing temperature in the manufacturing process. Platinum is selected as the conductor layer because it has corrosion resistance to hydrofluoric acid.

In this embodiment, however, the surface of the insulating substrate 13, which is a glass substrate, has a thickness of 0.1 mm by sputtering.
A 2 μm platinum thin film is formed as the conductor layer 8b, and thereafter, the conductor layer 8b is patterned into a stripe shape by ion milling as shown in FIG.

Next, as shown in FIG.
Then, a non-doped polycrystalline silicon layer 3 is formed to a thickness of 0.5 μm so as to cover conductor layer 8b, and as shown in FIG. Patterning by RIE is performed so as to leave the layer 3. By this patterning, the strong electric field drift layer 6 is formed.
The pattern of the portion to be the drift portion 6a in the above is formed. Therefore, after the same polycrystalline silicon layer 3 as in the first embodiment is subjected to a smoothing process using the conductor layer 8b as one electrode, an anodic oxidation process is performed to make the polycrystalline silicon layer 3 porous. Do. The depth of the porosity is made substantially equal to the thickness of the polycrystalline silicon layer 3 so that the porosity region almost reaches the conductor layer 8b. Here, even if the electrolytic solution contains hydrofluoric acid during the anodic oxidation treatment, the conductive layer 8b does not corrode because the conductive layer 8b has corrosion resistance to hydrofluoric acid. After the anodizing treatment, rapid thermal oxidation (RTO) is performed in a dry oxygen atmosphere using a lamp annealing apparatus.
By doing so, drift portion 6a composed of an oxidized porous polycrystalline silicon layer is formed.

Thereafter, as shown in FIG. 8D, a gold thin film is formed by EB vapor deposition so as to cover the insulating substrate 13 and the drift portion 6a, and a striped conductive thin film 7 is formed by patterning. 10 can be formed.

However, in this embodiment, since the polycrystalline silicon layer 3 is provided on the insulating substrate 13, a semiconductor element is formed on the polycrystalline silicon layer 3 around the electron source, so that an electron source driving circuit and the like are formed. Can be collectively formed on the insulating substrate 13.

In this embodiment, since the thickness of the porous region in the drift portion 6a is substantially equal to the thickness of the polycrystalline silicon layer 3, the entire voltage is applied to the porous portion of the drift layer 6a. That is, the applied voltage can be used for emitting electrons without waste, and the amount of emitted electrons can be increased. Although a conductive substrate provided with a conductive layer 8b on an insulating substrate 13 is used, any material other than platinum may be used as long as it has corrosion resistance to hydrofluoric acid, and other conductive materials are protected by a corrosion resistant material. By doing so, a conductor layer may be formed. Other configurations and operations are the same as those of the first embodiment.

[0051]

According to a first aspect of the present invention, there is provided a conductive substrate, a strong electric field drift layer formed on one surface side of the conductive substrate, and a conductive thin film formed on the strong electric field drift layer. ,
A field emission type electron source in which electrons injected from the conductive substrate are drifted through the strong electric field drift layer and emitted through the conductive thin film by applying a voltage with the conductive thin film as a positive electrode with respect to the conductive substrate, The strong electric field drift layer has a porous semiconductor layer whose surface is oxidized or nitrided and has a smooth surface. Since the surface of the porous semiconductor layer is smooth, a voltage is applied to the conductive thin film as a positive electrode with respect to the conductive substrate. Sometimes, the equipotential surface formed near the surface of the porous semiconductor layer is almost parallel to one surface of the conductive substrate, so that the variation in the emission direction of electrons is smaller than in the past, and electrons such as high definition displays There is an effect that it is possible to apply to a device having a narrow allowable angle range of the emission direction of light.

According to a second aspect of the present invention, in the first aspect of the present invention, the porous semiconductor layer has a substantially uniform thickness in a porous region. When a voltage is applied, the electric field acts almost uniformly on the porous region, so that the equipotential surface in the strong electric field drift layer becomes almost parallel to the conductive substrate, and the variation in the electron emission direction and the electron There is an effect that the unevenness of the amount of the release can be reduced.

According to a fifth aspect of the present invention, in the first to fourth aspects of the present invention, since the porous semiconductor layer is made of porous polycrystalline silicon, the electron emission characteristic has a small dependence on the degree of vacuum and the electron emission characteristics are small. Occasionally, electrons can be stably emitted with high efficiency without occurrence of a popping phenomenon.

According to a sixth aspect of the present invention, there is provided the method for manufacturing a field emission type electron source according to the first aspect, wherein the semiconductor layer formed on one surface of the conductive substrate is made porous by anodizing. Before forming a porous semiconductor layer, a smoothing step of smoothing the surface of the semiconductor layer is provided, so that the semiconductor layer having a smoothed surface is made porous by anodizing treatment to form a porous semiconductor layer. Since the semiconductor layer is formed, the surface of the strong electric field drift layer can be made smoother than before, and a field emission type electron source with a smaller variation in electron emission direction than before can be provided. There is an effect that can be.

According to a seventh aspect of the present invention, in the sixth aspect, the smoothing step is a step of smoothing the surface of the semiconductor layer by an electrolytic polishing method. Since the surface of the semiconductor layer is smoothed by the electrolytic polishing method, there is no need to prepare a separate device for smoothing, and the surface of the semiconductor layer can be smoothed at low cost, resulting in an increase in cost. Can be suppressed.

According to an eighth aspect of the present invention, in the sixth aspect of the present invention, the smoothing step is a step of smoothing the surface of the semiconductor layer by a reactive ion etching method. When a mask material layer such as silicon or silicon nitride film is deposited, and the mask material layer is patterned by reactive ion etching to form a mask and then anodizing treatment is performed, the mask material layer is patterned at the time of patterning the mask material layer. Since the surface of the semiconductor layer can be smoothed in succession to the etching, there is no need to prepare a separate device for smoothing, and the surface of the semiconductor layer can be smoothed at low cost. As a result, there is an effect that cost increase can be suppressed.

According to a ninth aspect of the present invention, in the sixth to eighth aspects of the present invention, the anodic oxidation treatment is a treatment in which the thickness of the porous region is made substantially uniform. There is an effect that a smaller field emission power supply can be provided.

According to a tenth aspect of the present invention, in the ninth aspect of the present invention, a substrate is used in which an electrically conductive layer having corrosion resistance to hydrofluoric acid used in anodizing treatment is provided on one surface of the insulating substrate. The anodic oxidation treatment is a treatment for making the semiconductor layer porous so that the thickness of the porous region is substantially equal to the distance between the conductive thin film and the conductive substrate. Since the thickness of the porous region can be made substantially uniform without adding, there is an effect that an increase in cost can be prevented.

According to an eleventh aspect of the present invention, in the ninth aspect of the present invention, the anodic oxidation treatment is performed in such a manner that a pulse shape is formed between the conductive substrate and the counter electrode so that the thickness of the porous region becomes substantially uniform. Since the current is alternately reversed in polarity and energized, the thickness of the porous region can be made substantially uniform without adding an anodizing treatment and a separate step,
There is an effect that a cost increase can be prevented.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an electron emission direction according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the first embodiment of the present invention.

FIG. 3 is a schematic perspective view of the same.

FIG. 4 is a perspective view of a main part of the above.

FIG. 5 is a sectional view of the same.

FIG. 6 is a process diagram of a main part showing a manufacturing process of the same.

FIG. 7 is a schematic configuration diagram of the manufacturing apparatus of the above.

FIG. 8 is a process diagram of a main part showing a second embodiment of the present invention.

FIG. 9 is a sectional view showing a conventional example.

FIG. 10 is an operation explanatory view of the above.

FIG. 11 is a diagram illustrating the principle of the above.

FIG. 12 is a sectional view showing another conventional example.

FIG. 13 is an explanatory diagram of the operation of the above.

FIG. 14 is an explanatory diagram of a problem of the conventional example.

FIG. 15 is a cross-sectional view showing a conventional problem.

[Explanation of symbols]

 Reference Signs List 6 Strong electric field drift layer 7 Conductive thin film 3 Polycrystalline silicon layer 21 Grain 22 Silicon oxide film 23 Microcrystalline silicon 24 Silicon oxide film 100 Conductive substrate

Continuing on the front page (72) Inventor Takuya Komoda 1048 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd. (72) Inventor Yoshiaki Honda 1048 Okadoma Kadoma, Kadoma City, Osaka Matsushita Electric Works (72) Inventor Takashi Hatai 1048 Kazuma Kadoma, Kadoma City, Osaka Prefecture, Japan Inside Matsushita Electric Works Co., Ltd. 1048, Kadoma, Kamon, Fumonma-shi Matsushita Electric Works Co., Ltd. F-term (reference) 5C031 DD16 DD17 DD19 5C036 EE01 EE03 EE14 EG12 EH04

Claims (11)

[Claims] 1. A conductive substrate comprising: a conductive substrate; a strong electric field drift layer formed on one surface side of the conductive substrate; and a conductive thin film formed on the strong electric field drift layer. A field emission type electron source in which electrons injected from the conductive substrate are drifted through the strong electric field drift layer and emitted through the conductive thin film by applying a voltage as a positive electrode to the substrate, and the strong electric field drift layer is A field emission type electron source comprising a oxidized or nitrided porous semiconductor layer having a smooth surface. 2. The field emission type electron source according to claim 1, wherein the porous semiconductor layer has a porous region having a substantially uniform thickness. 3. The field emission type electron source according to claim 1, wherein the porous semiconductor layer has a surface roughness equal to or less than a thickness of the porous semiconductor layer. 4. The porous semiconductor layer according to claim 1, wherein an angle between a normal line of the surface and a virtual surface orthogonal to a thickness direction of the conductive substrate is distributed within an allowable angle range defined by a plane where the emitted electrons reach. The field emission type electron source according to any one of claims 1 to 3, wherein: 5. The field emission type electron source according to claim 1, wherein said porous semiconductor layer is made of porous polycrystalline silicon. 6. The method for manufacturing a field emission electron source according to claim 1, wherein the semiconductor layer formed on one surface of the conductive substrate is made porous by anodizing treatment. A method of manufacturing a field emission type electron source, further comprising a step of smoothing a surface of the semiconductor layer before forming the semiconductor layer. 7. The method according to claim 6, wherein the smoothing step is a step of smoothing the surface of the semiconductor layer by an electrolytic polishing method. 8. The method according to claim 6, wherein the smoothing step is a step of smoothing the surface of the semiconductor layer by a reactive ion etching method. 9. The field emission type electron source according to claim 6, wherein the anodic oxidation treatment is a treatment in which the thickness of the porous region is made substantially uniform. Manufacturing method. 10. A substrate in which a conductive layer having corrosion resistance to hydrofluoric acid used in anodizing treatment is provided on one surface of an insulating substrate as the conductive substrate, and the anodizing treatment is made porous. 10. The method for manufacturing a field emission electron source according to claim 9, wherein the process is a process of making the semiconductor layer porous so that the thickness of the region is substantially equal to the distance between the conductive thin film and the conductive substrate. 11. The anodic oxidation treatment includes applying a pulsed current between the conductive substrate and the counter electrode by alternately reversing the polarity so that the thickness of the porous region becomes substantially uniform. 10. The method for manufacturing a field emission electron source according to claim 9, wherein: