JP2001527328A - Asynchronous transfer mode switch - Google Patents

Abstract

An ATM (Asynchronous Transfer Mode) switch having a plurality of switch ports (24) connected to a switch core (22) by respective bidirectional links (27, 28). A corresponding matrix unit (40) is connected to each switch port, and each matrix unit manages writing of service cells to one row of the crosspoint unit (32) and reading of service cells from one column of the crosspoint unit. I do. The bidirectional link between each switch port and the corresponding queue unit of the switch core carries both service cells and control cells. An interactive exchange of control cells is implemented in the sequence operation of the switch core. Operation relies in particular on control cell generation, including service cell transmission from the switch core, polling state control cell transmission from the switch core, reading the contents of certain control registers maintained in the switch core, and synchronization procedures. Polling status information indicating "occupied" / "empty" for a selected one of the crosspoint units is transmitted by a polling status control cell. The polling state control cell may be (1) responsive to a specific control cell invoking the polling state cell, or (2) having a predetermined number of crosspoint units affected / not present (e.g., "empty" / "occupied"). State) is generated and transmitted in any of the cases where a change has occurred.

Description

DETAILED DESCRIPTION OF THE INVENTION

Background 1. TECHNICAL FIELD The present invention relates to a switch such as a communication switch in which ATM cells are carried.

[0002] 2. Related Art and Other Considerations Increasing interest in high band services, such as multimedia applications such as video on demand, video telephony, teleconferencing, has motivated the development of Broadband Integrated Services Digital Networks (B-ISDN). Have been. B-ISDN
Is based on a technology known as Asynchronous Transfer Mode (ATM) and offers significantly enhanced communication capabilities.

[0003] ATM is a packet-oriented transfer mode using asynchronous time-division multiplexing technology. Packets are called cells and traditionally have a fixed size. Traditional ATM cells consist of 53 octets, of which 5 octets form the header and the remaining 48 octets constitute the "payload" or information portion of the cell. The header of an ATM cell contains two quantities, which are the connections of the ATM network in which the cell will be carried, in particular the VPI (Virtual Path Identifier) and the VCI (Virtual Channel Identifier). Identify. Generally, the virtual path is the primary path defined between two switching nodes in the network, and the virtual channel is one for each primary path.
There are two specific connections.

At its termination point, the ATM network is connected to a terminal device, for example, an ATM network user. Typically, there are a plurality of switching nodes between ATM network termination points, the switching nodes having ports connected to each other by physical transmission paths or links. Thus, the ATM cells forming the message may go through several switching nodes as they are transferred from one originating terminal to the destination terminal.

A switching node has a plurality of ports, and each port can be connected via a link circuit and a link to another node. The link circuit performs packetization of the cells according to the particular protocol used on the link. A cell arriving at a switching node enters the switching node at a first port and exits from a second port via a link circuit onto a link connected to another node. Each link carries cells for multiple connections. The connection is, for example, a transmission between the calling subscriber or subscriber station and the called subscriber or subscriber station.

[0006] Each switching node typically has several functional parts, the main part of which is a switch core. The switch core essentially functions like a cross connection between the ports of the switch. The internal path to the switch core is selectively controlled so that specific ports of the switch are connected together to eventually carry messages from the input to the output of the switch. In this case, the transport is performed from the departure terminal to the destination terminal.

US Pat. No. 5,467,347 to Petersen discloses an ATM in which various types of ATM cells, essentially all of uniform length, are transmitted between a switch core and a port of the switch. A switch is disclosed. Cell types include traffic cells, operation and maintenance cells, and idle cells. All types of cells have essentially the same length, but not all cells are necessarily filled with information, and therefore cause some loss in terms of transmission efficiency. The traffic cells are fed from the very first switch port to a buffer at the crosspoint of the switch matrix, and then unloaded from the buffer to the destination or destination switch port. The traffic cells sent from the original switch port to the switch have a relay address field in which each bit corresponds to a target switch port. Each traffic cell unloaded from the switch core and sent to the target switch port has a relay poll field that indicates which target switch port is occupied and which is free. Therefore, each traffic cell is disturbed by information reflecting the state of the switch port.

What is needed, therefore, is an object of the present invention to provide different types of ATMs.
An efficient ATM switching system that formats and uses cells thoughtfully and wisely.

SUMMARY Asynchronous transfer mode (ATM) switches have a plurality of switch ports, each connected to a switch core by a bidirectional link. The switch core includes a memory array unit having a cross point unit of two buffer matrices. Each switch port is connected to the corresponding matrix unit, and each matrix unit manages writing a service cell to one column of the crosspoint unit and reading service cells from one row of the crosspoint unit.

The bidirectional link between each switch port and the corresponding queue unit of the switch core carries both service cells and control cells. A service cell, known as a traffic cell or information cell, obtained at an input or output source switch port follows a path through a switch core to an output or destination switch port. The control cell does not contain the switched information, but is instead exclusively used to carry information used for the management and operation of the switching system.

The ATM switching system of the present invention allows cells of different sizes to be carried on a bidirectional link between its switch core and a switch port. For example, the serving cell has a cell size different from the control cell, and the cell size of the serving cell does not necessarily need to be uniform.

The service cells can have different cell sizes so that two consecutive service cells need not have the same length or the same payload size. A service cell transmitted with its bidirectional length includes a cell size field, which indicates the cell size of each service cell in which it is included. In one embodiment, the serving cell is the next cell size (bytes): 8, 16,
24, 32, 40, 48, and 56.

On the contrary, each of the control cells used in the exemplary embodiment is 4 bytes long. Different types of control cells (eg, LCC cells and LSC cells) are provided, and these control cell types have different formats. LCC control cells are known as link connection control cells, and LSC control cells are known as link synchronization control cells.

The switch port and its corresponding queue unit in the switch core both have a synchronization state machine, which exchanges LSC control cells. LSC
The control cell contains information that synchronizes the operation of the two state machines. At the patent crosspoint, the LSC control cell has a format that includes a field that indicates one of a plurality of synchronization states of the machine that generated the LSC control cell. By employing a short synchronization-only LSC control cell in a pre-established protocol, synchronization between the switch port and the switch core is achieved and maintained economically and quickly.

Each matrix unit has a set of control registers as part of the crosspoint status unit. The set of control registers is distinct from the buffers of the crosspoint unit, through which service cells are switched. Each switch port, at least in part, writes non-service information, e.g., control information, to or from a set of control registers to thereby associate an associated matrix unit of the switch core. Control.

Some of the control registers are known as "bitmapped" registers. This is because each bit of such a control register is associated with one of a plurality of switch ports connected to the switch core. The bit-mapped control registers include a polling state status register and a polling state release register. A given matrix unit indicates that the crosspoint buffer in the same column of the core matrix is "occupied" or "empty."
Has a bit of the polling status register set to indicate whether The polling state release register of the matrix unit may indicate that the buffer in the column managed there has transitioned from "occupied" to "empty" or that the buffer has not transitioned. Has the bit set to

Various control registers are employed to establish, for example, various operating parameters of the switching system. Such parameters may include, for example, certain sequences of operations (eg, pollable, scannable), certain timing information (eg,
Polling status, scan rate) and some invalid information (eg, scan block).

The link connection control cell (LCC) includes cells in two formats. that is,
Bitmapped format (for bitmapped registers)
In "coded" format (used for I / O operations on some bitmapped registers along with unbitmapped registers). An "encoded" LCC cell contains the address of a particular control register where data is to be written and the non-service data stored / derived from that particular control register.

[0019] Despite different cell sizes, the serving cell and the control cell have a commonly formatted field known as the physical route identifier (PRI).
A cell is identified as a serving cell when any of the first set of pre-established values is stored in the PRI field. In the example of this embodiment,
When the value of the PRI field corresponds to a value indicating one of the plurality of switch ports,
The cell is recognized as a serving cell. In contrast, at least some of the control cells are recognizable. Because the value in the PRI field is the control cell (
This is because it corresponds to the identity or numbering of the control registers affected by, for example, a control register written or read using a control cell.

Each switch port of the switch has a different combination of the status of the different crosspoint units of the switch core, ie, whether these different crosspoint units are “occupied” or “empty”. You must be notified by: In particular, the crosspoint units included in each switch port include those transmitting to the serving cell (eg, in the same column as the port) and those crossing out the cell (eg, those in the row managed by the port). ). Eventually, a bit-mapped polling status register is used which is used to prepare the corresponding polling status control cell. The polling status register has a bitmap to be updated, reflecting the occupancy / vacancy transition of the crosspoint unit where the serving cell is transmitted by the switch port. First matrix unit divides cells into specific crosspoint units (XPUs)
Not only does the matrix unit set the appropriate bitmap in the polling status register, but also causes the bit to be set in the scan status register of another matrix unit, and that other matrix unit Of the cell from the cross point unit (XPU) of the X. As soon as the matrix unit handling the read detects that the cell is allowed to be read, it resets its scan status register and resets the polling status register of the first matrix unit. Resetting the polling status register of the first matrix unit causes the bit setting of the polling status release register of the first matrix unit to indicate a transition from "occupied" to "empty".
A change in status in the polling release register of the first queue unit causes the first queue unit to issue a polling release cell to the switch port.

On the other hand, in the prior art, since the polling state information is sent to the switch port periodically or automatically included in the serving cell, the present invention essentially specializes in transmitting the polling state information. It employs a specific scenario for the generation of polling state cells to be handled globally. That is, in the present invention, the polling state information is transmitted in a polling state control cell, and the polling state control cell responds to (1) a specific control cell invoking the polling state information, or (2) the crosspoint unit. It is generated or transmitted when there is a change in presence / absence (for example, empty / occupied status).

For example, when the source switch port wants to know the status of the crosspoint unit that can transmit cells to the switch core, the source switch port sends a polling status status control cell to the switch core. In response to the poll state status retrieval control cell, at the appropriate junction, the switch core prepares and sends the poll state status control cell to the requesting (originating) switch port. When the serving cell is unloaded from the crosspoint unit, a polling release control cell is prepared and sent to its switch port to signal that the unloaded crosspoint unit is free. Using the polling status information provided by both the polling status control cell and the polling release control cell, the switch port determines which crosspoint units in the switch core are available to receive more serving cells. Can decide.

Other control cells have been employed to establish various operating parameters of the switch. These operating parameters are established for each switch port since the switch port sends control cells to the associated queue unit. Such control cells are typically stored in their corresponding control registers and contain parameters and data that are examined by the switch core in relation to the sequence and other operations of the switch core. For example, a pollable control cell (LCC) is employed to store in a pollable register a value indicating which of a plurality of selectable polling modes will be used to operate the associated matrix unit. . These various polling modes require a certain minimum frequency for transmission of service cells relative to the number of polled cells transmitted on the link.

Thus, the ATM switch of the present invention performs an interactive exchange of control cells and sequences the operation of the switch core. In particular, operations that depend on the generation of control cells include transmission of service cells from the switch core, transmission of polling state cells from the switch core, retrieval of the contents of certain control registers maintained by the switch core, synchronization procedures, and the like. Includes

Detailed Description of the Drawings In the following description, specific details, such as specific architectures, interfaces, techniques, etc., are set forth for purposes of explanation rather than limitation, and Offers a complete understanding of. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

1.0 Overview FIG. 1 shows a switch core or structure 22 and a plurality of switch port boards (SPBs).
s) shows an ATM switching system 20 including elements that are on 24; In the illustrated example embodiment, 16 switch ports board (SPBs) 24 ₀ - 24 ₁₅ can be connected to the switch core 22. The elements on each switch port board 24 having the switching system 20 are known in the illustrated embodiment as "switch ports" and include a switch port integrated circuit (SPIC) 26,
It is incorporated into the SPICs 26 ₀ -26 ₁₅ shown in FIG.

As will be described later, each of the switch port boards (SPBs) 24 has a plurality of devices in addition to the SPIC mounted thereon. For this reason, switch port boards (SPBs) 24 are also referred to as "device boards". One or more of these devices are connected to a communication transmission line to receive one or more types of communication signals, eg, telephone, data, video, and the like. Also, the devices on the switch port board (SPB) are other devices, for example,
It generates control signals and the like useful for configuring and controlling other devices on another switch port board.

One purpose of the switching system 20 is to transmit ATM cells including, for example, communication signals and control signals through the switch core 22. In this regard,
If the ATM cells are not ready, incoming or generated signals received by devices located on one of the switch port boards (SPBs) 24 are mapped to ATM cells. The cell is applied to and carried through the switch core 22 and the cell emerges from the switch core 22 for application to another switch port board (SPB) 24. For example, a voice signal from a caller to a called party in a telephone call is received at a switch port board (SPB) 24 ₀ (which is ultimately connected to the called party) and the switch core Via 22, the call is applied to the switch port board (SPB) 24 ₁₅ for transmission to the called party (in this example, ultimately connected to the switch port board (SPB) 24 ₁₅ ).

Therefore, ATM cells are transferred between each switch port board (SPB) 24 and the switch core 22. In the example of FIG. 1, cell transfer occurs across two links connecting each switch port board (SPB) 24 and switch core 22. Cells sent from the switch port board (SPB) 24 to the switch core 22 are transmitted on the port-to-core link 27, while cells flowing out of the core 22 to the switch port board (SPB) 24 are core-to-core. -Port link 2
8 is applied. The 16 port-to-core links 27 and the 16 core-to-port links 28 are subscripted according to the particular switch port board serving here. The port-to-core link 27 and the corresponding core-to-port link 28 collectively constitute a "bidirectional link".

The switch core or configuration 22 includes a memory array unit (MAU) 30 and a plurality of matrix units (RCUs) 40. The memory array unit (MAU) 30 has conceptualized cross point units (XPUs) 32 as arranged in an array of rows and columns. Multiple cross point units (XPUs) 3
2 each of the location / is indicated by numerical subscripts indicating the address is in the 0 column 0 row if XPU32 _0,0 located at column 0 1 row if XPU32 _0,1, XPU32 _0,1 If so, it is in column 0, row 1, and thus, at maximum, XPU32 _15,15 is in column 15, row 15.

The matrix unit (RCU) 40 is provided corresponding to each switch port board (SPB) 24, that is, each column of the memory array unit (MAU) 30. Since 16 boards such as switch port boards are shown in the example of FIG.
Pieces of matrix units (RCUs) 40 ₀ -40 ₁₅ is also illustrated. Each matrix unit (RCU) 40 has all the crosspoint units (XPUs) in the same column.
s) by a write bus to the input terminals of 32 and by a read bus to the output terminals of all crosspoint units (XCUs) 32 in a given row. For example, RCU40 ₀ by the write bus 42 ₀ from the cross point unit (XPUs) 32 _0,0 32 _0,15 to the input terminal, and the cross point units (XCUs) 32 _0,0 32 _15,0 output of It is connected by the read bus 44 ₀ to the terminal. Similarly, RCU40 ₁₅ by the write bus 42 ₀ to the input terminal of the cross-point uni Tsu preparative (XPUs) 32 _15,0 32 _15,15 Then, the cross point unit (XCUs) 32 _0,15 32 _15, It is connected by a read bus 44 ₁₅ to output terminal _15. In addition to the write bus 42 and the read bus 44, the matrix units (RCUs) 40 are also connected by a system clock bus (SCB) 46 and a crosspoint status bus (CSB) 48.

As shown in FIG. 2, each cross point unit (XPU) 32 actually has two buffers at the cross points. One of these buffers is referred to as Buffer 0 or Buffer CBQ ₀ and the other is known as Buffer 1 or Buffer CBQ ₁ . Each of these two buffers in each crosspoint unit (XCU) 32 is 56 bytes long. In each cross point unit (XCU) 32, the buffers CBQ ₀ and CBQ ₁ are connected in parallel with each other. Each buffer CBQ ₀ and CBQ ₁ has an input gate employed to enable the input of cells received on a corresponding write bus 42 and an output gate employed to flush cells to a corresponding read bus 44. Have. At some of the junctions here, a memory array unit (MAU) 30
The buffers CBQ ₀ of all the cross point units (XPUs) 32 are collectively referred to as “matrix 0”, while the memory array units (MAU) 3
The buffers CBQ ₁ of all the zero cross point units (XPUs) 32 are collectively referred to as “matrix 1”.

1.1 Control Register Each matrix unit (RCU) 40 includes a crosspoint status unit (XSU).
) 50. The crosspoint status unit (XSU) 50 has a plurality of control registers, including three special registers containing status information and core operation information. These control registers, for example, the switch in the payload of the buffer of the switch core 22, such as a buffer CBQ _0, C BQ ₁ are those completely different, the user data serving cell through these buffers (as described below) Is done. The three control registers involved in loading and unloading in the switch core 22 include a polling status register and a scan status register. The polling status register includes a polling status status register and a polling status release register. An indication is stored in the polling status register indicating whether the buffers of the crosspoint units (XPUs) 32 in the columns managed by the matrix unit (RCU) 40 are "empty" or "occupied". Will be updated as follows. The polling state release registers are managed by a matrix unit (RCU) 40 and also include crosspoint units (XPUs) 3 in columns read by read bus 40.
The second buffer is updated to indicate whether it has transitioned from "occupied" to "empty" or has not changed. Therefore, the polling status register and the polling release register are collectively referred to as a "polling status register".
The polling status register stores the crosspoint status bus (CS
B) Updated using 48.

[0034] Figure 6 is a part of the cross-point status bus (CSB) 48 and two representative matrix units (RCUs), in particular, shows the several go-connected to RCU40 ₀ and RCU40 _15. A more detailed discussion of the matrix units (RCUs) 40 will be given later, ie, in section 3.0, but FIG. 6 shows that each matrix unit (RCU) 40 includes three control registers of interest here. Of the cross point status unit (XSU) 50 of FIG. Such three control registers include a polling status register 50-2, a scan status register 50-4, and a polling status release register 50-8. As shown in FIG. 6, each of these control registers has 16 bits corresponding to 16 cross point units (XCUs) 32 controlled by a matrix unit (RCU) 40. In that matrix unit, these control registers are resident, that is, the sixteen crosspoint polling units (XPUs) 32 are aligned with one column of the matrix unit (RCU) 40.

1.2 CSB Bus For each matrix unit (RCU) 40, a crosspoint status bus (C
SB) 48 has a lead for outputting the bit status of the polling status register 50-2. For example, in FIG. 6, reference numeral 48-1 ₀ is painted lead crosspoint status bus (CSB) 48, which outputs the bit status polling status registers 50-2 _0. For example, the last bit of the status in the polling state status register 50-2 _0, matrix unit (RCU) 40 ₁₅ is read crosspoint unit (XPU) 32 in the last column of the memory array unit (MAU) 30 and controls and communicates with the first bit of the scan status register 50-4 _15. In this regard, reference numeral 48-2 ₁₅ different 16 matrix unit that sets a 16-bit each scan status register 50-4 ₁₅ (RCUs) 40 polling status register 50-
Which shows the lead in the cross-point status bus (CSB) 48 from 2 _0. Similarly, leads indicated by reference numeral 48-3 ₁₅ is employed to communicate the settings to various other scan status register 50-4 of the corresponding bit in a polling state status register 50-2 ₁₅ ing. Leads indicated by reference numeral 48-4 _0, the corresponding bit matrix unit (RCU) 40 ₀ of scan status register in a polling state status register 50-2 of the other matrix units (RCUs) 40 50-4 ₀ Used to communicate to set to.

The crosspoint status bus (CSB) 48 also has leads for resetting bits in the polling status register 50-2 when cells are read from the crosspoint unit (XPU) 32. For example, when a cell is read from a _crosspoint unit (XPU) 32 _0,15 ,
One of the leads of the group indicated by the reference numeral 48-5 ₁₅ connects the first bit of the scan status register 50-4 _15, the last bit of the poll state status register 50-2 ₀ reset signal Conveyed to. Reset signal inputted to the poll state status register 50-2 ₀ is conveyed to the lead line, depicted by reference numeral 48-6 _0. Similarly, by reading the cell from the first column of crosspoints unit (XPUs) 32, it will be sent to read a line reset signal is depicted by reference numeral 48-7 ₀ from the scan status register 50-4 ₀ . Reference numeral 48-8 ₁₅ denotes a lead wire for resetting a bit in a polling state status register 50-2 ₁₅ matrix unit (RCU) 40 _15.

As a result, two sets of control registers (for example, polling status register 50-2, scan status register 50-4, polling status release register 5)
0-8) are provided in each matrix unit (RCU) 40. One set of control registers is than also to the buffer CBQ ₀ in the matrix 0, another set of control registers is for buffer CBQ ₁ in the matrix 1. To specify which set of control registers a bit set or bit reset signal is sent on the crosspoint status bus (CSB) 48, the crosspoint status bus (CSB) 48 is also provided with each matrix unit (CSB). RCU) 40. Therefore, a crosspoint status bus (CSB) 48 is shown in FIG. 6 with sixteen matrix indicating leads and also includes the bit setting and bit reset leads described above.

2.0 Cell Types As described above, ATM cells are transmitted between various switch port boards (SPBs) 24 and the switch core 22. ATM switching system 2 of the present invention
0 uses cells of different lengths. 3 between the representative one switch core 22 of switch port boards, in particular, the port --to-- Core link 27 ₀ and core - tools U - switch port connected to the switch core 22 by port link 28 ₀ board (SPB) indicating the transfer to a _24-0.

The Port --to-- Core link 27 ₀ and core --to-- port link 28 ₀ each carries a plurality of cells types, including serving cell and control cell. A service cell, known as a traffic cell or user information, contains (or includes) user data, such as telephone, data, video, etc., in a payload portion thereof, which data is transmitted via switch core 22 to other switch ports. It will be transferred for application to the board (SPB) 24. The control cells depicted as LCC cells and LSC cells in FIG. 3 are used for control and management of the ATM switching system 20.

As described below with respect to FIG. 4A, the service cells can be of different lengths so that two consecutive service cells need not have the same length or the same payload size. Moreover, the control cell has a different size than the serving cell. Further, the present invention provides different types of control cells (eg, LCC cells and LSC cells), each having a control cell type having a different format. Figure 3 Hatada one switch port board (SPB) 24 ₀ indicates that the is controlled to switch core 22, but the switch core 22 and another switch port board (SPB
s) It is understood that the link to 24 also carries service cells and control cells.

2.1 Service Cell The service cell carries user data to units controlled by the switch core 22. All service cells are transported from one switch port board (SPB) 24 to one or more other switch port boards (SPBs) 24 via a switch core 22. The size of the service cell changes. In the illustrated embodiment, the correct sizes illustrated are 8, 16, 24, 32, 40, 48, 56 bytes,
These include a two-byte header (the first two bytes of the cell). In the illustrated embodiment, the maximum cell size is 56 bytes.

As shown in FIG. 4A, a service cell has a 2-byte header (the first 2 bytes of the cell) and a payload. This 2-byte header is stored in the switch core 22.
Used to carry user data to the desired or correct destination (the switch port board) and pass the rest of the cell (ie, the payload) through the switch core 22, but not to the switch core 22. User data. Some fields of the service cell will be described below.

2.1.1 PRI, Cell Type, Physical Route Identifier In a cell received on the port-to-core link 27 from the switch port board (SPB) 24, the PRI field of the received service cell contains cell data. Contains a value indicating the particular buffer or crosspoint unit (XPU) to be stored (in the same column as the receive crosspoint unit (XPU) 32). For example, if, if has a value of "5" in the PRI field cells received from the switch port board (SPB) 24 _0, the cell will be stored in the XPU _{0, 5.}

In the illustrated embodiment, a PRI value in the range of 0-19 indicates a serving cell. However, only 16 XPUs 32 are in the memory array unit 30 (FIG. 1).
) Is provided per column, so only PRI values from 0 to 15 are valid values. Service cells with PRI values outside this range are rejected. However,
The size of unsupported service cells (PRI = 16-19) is checked to find cell boundaries. As will be explained later, PRI values greater than 20 are used for different purposes in the control cell.

As will be described later, immediately before a cell is transmitted from the switch port board (SPB) 24 to the switch core 22, the PRI field is replaced with a value corresponding to the switch port board from which the cell is transmitted. For example, if, when the cell is being sent to the switch port board (S PB) 24 ₁₅ via the switch core 22 from switchport boards (SPB) 24 _0, the way to switch core 22, the switch port board ( SPB) before leaving 24 _0, the cell has a modified PRI value to "0" to "15".

2.1.2 CBQ Crosspoint Buffer Cue Code As shown in FIG. 2, each crosspoint unit (XPU) 32 has two queues or buffers, CBQ ₀ and CBQ ₁ . The purpose of the CBQ field is to direct the serving cell to one of these two queues or buffers at a particular cross point. The CBQ field indicates in which of these buffers the cell is to be stored. If CBQ value is "0", the cell indicates that it is placed into a buffer CBQ _0, CBQ value is "1" Der lever, its cell is shown to be loaded in CBQ _1. It is not valid that the CBQ value is "2" or "3", and cells having such invalid values are rejected.

2.1.3 FBP and SBP Parity Bits FBP is the parity bit of the first byte, which covers the first byte of the service cell header. SBP is the parity bit of the second byte covering the second byte of the service cell header. For the first and second bytes of the service cell header, the parity is odd, including the parity bit.

2.1.4 TTI Field The TTI (traffic type indication code) field is 3 bits. For a receiving service cell, these three bits specify the traffic type for the serving cell and whether the cell is concatenated. The traffic type or “cast” type is a cell whose cell is designated as “unicast (one destination)”, “multicast (one with several destinations)”, or “broadcast”. Broadcast cell is sent to all 16 ports). An "attached" cell indicates that the current cell is followed by a new cell directed to the same switchport board (eg, an entity with the same termination). Table 1 shows the latent value for the TT1 field.
It indicates the importance of “0” to “7”.

The TTI bit is converted by the switch core 22. Such conversion depends on the received TTI value and buffer status at switch core 22 (with respect to the associated CBQ and column). Table 2 shows the reception TTI and the conversion / transmission TTI value.

Thus, the TTI field in the transmitting cell contains an indication of whether all of this column and the actual CBQ value buffer of the relevant receiver are “empty”. If at least one buffer is occupied, that buffer is not "free".

2.1.5 SCS Field The SCS (Service Cell Size Code) field has 3 bits. These three
The bits specify the size of the serving cell. The possible sizes of the serving cells in the illustrated embodiment are shown in Table 3. The order of possible service cells is 8, 16, 24, 32, 40, 48, 56 bytes (including the header).

2.1.6 NU Field The field NU (unused) is unused, and the switch core 22 is transparent.

2.1.7 Cell Payload The payload is transferred transparently for the switch core 22.
User data ". As is clear from the SCS field (see FIG. 4A) and Table 3, the size of the payload varies from 6 to 54 bytes.

2.2 Control Cell The control cell is terminated in the matrix units (RCUs) 40 and transmitted. All control cells are 4 bytes long. As shown in FIG. 4B, all control cells have a PRI (physical route identifier) field, an FBP (first byte parity) field, and an SBP (second byte parity) field as described above in the serving cell. Have. In addition, the control cell has a 1-bit LWP field, which is the parity field of the last word. LWP covers the last word (third and fourth bytes). The parity for the last word is odd, including its parity bit.

The possible PRI values for the control cell are in the range 20-31. In the illustrated embodiment, the valid control cells are 25, 26,
It has one of 28, 30, 31. As described further herein, these PRI values represent the format and, in some cases, the "address cells" of a particular control register in the cross point unit (XCU) 32 involved in register read or write operations. .

The control cells are used for remote control and monitoring of the queue units (RCUs) 40 and for synchronizing the connection with the switch port boards (SPBs) 24. There are two types of control cells: link connection control (LCC) cells and link state control (LSC) cells.

2.2.1 Link Connection Control (LCC) Cell The LCC cell is basically employed to control and operate the switch core 22 remote from the switch port board (SPBs) 24. At this point, LCC cells are used for reading and writing to / from registers inside matrix units (RCUs) 40. The LCC cell also sends from the switch core 22 to the affected switch port board (SPB) 24 information about buffer release in the cross point units (XPUs) 32, ie, when the buffer transitions from occupied to empty. Convey. LCC in two formats
There are cells, ie, bitmap formats and coded formats. LC
The specific format of C is indicated by the PRI value. PRI value, 25, 26,
Reference numerals 28 and 30 denote LCC cells in a bitmap format, and a PRI value “31”
Indicates an LCC cell in coded format (or alternatively an LSC cell).

2.2.1.1 Bitmap Format LCC Cell FIG. 4B-1 shows a bitmap format link connection control (LCC) cell node format. The bitmap format is based on the connected switch port board (SPB) 24 and the matrix unit (RCU) 4 of the switch core 22.
The operation data is transferred at high speed to / from the control / status register in 0. Up to 1
Six bits are loaded or unloaded in one cell transfer.

2.2.1.1.1 BCD Field 16 bits loaded or unloaded in one cell transfer are stored in a BCD (buffer control data) field. Each of the 16 bits of the BCD field holds data to be written to or read from the "addressed" control register, i.e., the control register having the value specified by the PRI field. When the BCD field is used as a bitmap, BCD-N holds the value associated with the specified column or row buffer.

2.2.1.1.2 CBQ, Crosspoint Buffer Queue The CBQ field is: Serves the same purpose as for the serving cell. For example,
Indicates _one of the queues CBQ ₀ or CBQ _{1 in} the cross point unit (XPU) 32. Legal values are "0" and "1", and cells with other values are rejected.

2.2.1.1.3 RE Field and NU Field The bits marked RE in FIG. 4B-1 are reserved, and the NU field in FIG.
Bits marked with are unused. Therefore, both RE and NU have switch core 2
2 is transparent.

2.2.1.2 Coded Format LCC Cell Switch Port Board (SPB) depending on LCC cell coded format
24 allows addressing of all control registers inside the corresponding matrix unit (RCU) 40 (with the same subscript number). One byte at a time is loaded or unloaded with LCC cells having the coded format. The format of the coded LCC cell is shown in FIG. 4B-2.

If the PRI has the value “31”, this identifies that the cell is an LSC cell or an LCC cell. The additional bits of the cell, the LSI bits, distinguish between LSC cells and LCC cells. In particular, if the LSI value is "0", this indicates an LCC cell in coded format, while if the LSI value is "1", this indicates LS
3 shows a C cell.

The remaining bits of the coded LCC cell are interpreted according to Table 4. In Table 4, all combinations of writing and reading with respect to the switch core 22 are possible. In addition, cells with write / read equal to 1/1 perform write-read.

2.2.2 Link State Control (LSC) Cell The link state control (LSC) cell is
s) Used to synchronize the connection between 40 and the corresponding (ie, similarly subscripted) connected switch port board (SPB) 24. L
The SC cell format facilitates fast and reliable synchronization of cell flows. That is, it finds the beginning of the cell, maintains cell flow in each direction, and assists in dividing the cell rate in the direction toward switch core 22.

Using an LSC cell implies cooperation between the switch port board (SPB) 24 and the switch core 22. LSC cells are involved in both directions of transmission (eg, switch-to-core link 27 and core-to-switch link 28). L
The use and operation of the SC cell is described in further detail below with reference to FIGS. 8 and 9 and the corresponding sync state machines on both sides of links 27 and 28.
The format of the link state control (LSC) cell is shown in FIG. 4B-3.

2.2.2.1 Synctag (Sync Tag) Field The Synctag (sync tag) field is a 4-byte pattern used to identify an LSC cell. The Synctag field can have one of two legal values (starting at byte 0 in hexadecimal). The first valid Synctag field values are FE, 1F, 00, and 7F, indicating that the LSC cell is in the PRESYNC state (SSC = 11). The first valid Synctag field values are FE, 1C, 00, and 7F, indicating that the LSC cell is in the SYNC state (SSC = 00). The beginning of the cell is at the rise of the bit clock. The parity bits (FBP, SBP, LWP), status code and PRI are contained in the bytes of these four Synctag fields.

2.2.2.2 SSC Field The SSC (Sync Status Code) field has two bits that define the state of the appropriate sync state machine. LSC cell is a switch port board (S
PB) 24, the SSC field contains the switch port board (SP
B) Define the state of the sync state machine at 24. When an LSC cell originates from the switch core 22, the SSC field defines the state of a sync state machine at the switch core 22.

The SSC field has the following legal values: That is, “0” (indicating that the side transmitting the LSC cell is not in the PRESYNC state) and “3” (indicating that the side transmitting the LSC cell is in the PRESYNC state).

The process of transmitting an LSC cell with the appropriate state is described in section 6.0 and is illustrated in FIGS.

3.0 Switch Port Board (SPB) The switch port integrated circuit (SPIC) of each switch port board (SPB) 24
) 26 has a crosspoint status register 26R for each matrix of switches. In the crosspoint status register 26R for a particular switch port integrated circuit (SPIC) 26, the switch port integrated circuit (SPI)
C) In row alignment on the switch port board (SPB) 24 for 26,
There is a bit position corresponding to each cross point unit (XCU) 32. For example, for point status register 26R _0, there is the bit position for each XPU32 _0,0 ~32 _0,15, relates point status register 26R _15, XPU
There is a bit position for each of 32 _{15,0 to} 32 _15,15 . As described below, whenever the switch port board (SPB) 24 writes a cell to the XPU 32, the switch port integrated circuit (SPIC) 26 determines the specific XP that the cell was written to.
A bit is set in the crosspoint status register 26R corresponding to U32. Thereafter, the switch port board (SPB) 24 cannot transmit another cell to that particular XPU 32 until the XPU bit is reset in the crosspoint status register 26R. Also, as described below, the bits in the crosspoint status register 26R are reset when the switchport integrated circuit (SPIC) 26 receives a polling state release cell with a corresponding bit having one value. You. Therefore, the crosspoint status register 26R serves for handshaking between the switch port board (SPB) 24 and the switch core 22.

From the above description of the matrices, eg, matrix 0 and matrix 1, it is understood that the crosspoint status register 26R is provided in the switch port integrated circuit (SPIC) 26 for each matrix.

4.0 Matrix Unit (RCU) 1 of link 27 from switch port board (SPB) 24 to switch core 22
All cells that enter through one are destined for the corresponding matrix unit (RCU) 40 (see FIG. 1). An overview of the handling of service cells by the switch core 22 is particularly with respect to the control registers of the matrix units (RCUs) 40. FIG. 6A
6E is illustrated by the sequential frames depicted in FIG. 6E. Further details from various aspects of serving cell handling are given, for example, in section 4.6.1.3.

As mentioned above, when the switchport integrated circuit (SPIC) 26 transmits a cell to its corresponding matrix unit (RCU) 40, the switchport integrated circuit (SPIC)
IC) 26 sets a bit in its crosspoint status register 26R. The bit set corresponds to the position of the column of the particular cross-point unit (XCU) 32 to which the cell is addressed. In the frame depicted in FIG 6A~ Figure 6E, switch port integrated circuit (SPIC) 26 ₀ wants to send a service cell to the switch ports integrated circuit (SPIC) 26 _15. Therefore, leading to the switch port integrated circuit (SPIC) 26 ₀ from the transmitted service cell matrix unit to Suiddjikoa 22 (RCU) 40 ₀ via the crosspoint unit (XCU) 32 _0,15. Therefore, the switch port integrated circuit for transmitting to 6-1 and the labeled arrow serving cell (switch-port integrated circuits (SPICs) are addressed to 26 ₁₅₎ of the matrix unit (RCU) 40 ₀ in FIG. 6A (S PIC) represents the 26 _0. As shown in Figure 6A, when transmitting such services Suseru the matrix unit (RCU) 40 _0, the switch port integrated circuits (SPICs) 26 is the last bit of the cross-point status register 26R Configure (because the serving cell is addressed to the last XPU in the column, ie, the crosspoint unit (XPU) _320,15 )
.

The service cells are analyzed by a matrix unit (RCU) 40 and then cross-point units (XPUs) in the same column of the memory array unit (MAU) 30.
s) to the addressed one of the 32 via a queue unit (RCU) 40. The serving cell is temporarily stored in an appropriately addressed _one of the buffers CBQ ₁ or CBQ ₂ of the XPU 32. When a cell is stored in the crosspoint unit (XPU) 32, the matrix unit (RCU) 40 updates its crosspoint status unit (XSU) 50, in particular its appropriate polling status register, and the cell is stored. Specific buffer is "occupied"
Show that it was done. In this regard, the “occupied” state indicates that there is a cell to be unloaded, and the “empty” state indicates that the buffer is loaded.

In the example shown in FIG. 6B, the service cell is connected to the cross point unit (XCU) 32. _0,15 In coordination with the writing (indicated by the arrow labeled 6-2)
), The polling status register 50-2₀Bit 15 is set. Polling status register 50-2₀Bit 15 is set to the cross point unit (XPU) 32_0,15Indicates that is occupied. further
, Matrix unit (RCU) 40₀The crosspoint status unit (XSU) 50 of FIG. 6 converts the setting signal by the dashed line which causes reference numeral 6-3 in FIG. 6B.
As shown, the crosspoint status bus (CSB) 48 (see FIG. 6)
) Through scan state register 50-4_FifteenTo bit 0. I will explain later
So that two switchport integrated circuits (SPICs) 26₀And 26_FifteenThe scan status register bit pending at a rate between
Or when the last word is written to the XPU (scan rate register
Is set (as defined previously by setting bit 0).

Each matrix unit (RCU) 40 is a cross point status unit (XSU).
Scan its own scan status register 50-4 located at 50). When the position in scan status register 50-4 is set, the matrix unit (RC
U) 40 knows that a cell can be read from the corresponding crosspoint unit (XPU) 32. When a matrix unit (RCU) 40 begins reading cells from such a crosspoint unit (XPU) 32, the corresponding bit in scan status register 50-4 is reset. Also, the corresponding polling status register 50-2 located in the matrix unit (RCU) 40 that has written the cell in the cross point unit (XPU) 32 is reset. Therefore, in the scenario depicted in FIG. 6C, lines 6-4 depict the loading of service cells from the _crosspoint unit (XPU) _320,15 to the matrix unit (RCU) ₁₅ . As a result, the scan state register 50
The first bit reset -4 ₁₅ occurs. Matrix unit (RCU) 40 ₁₅ crosspoint status unit (XSU) 50 ₁₅ of the reset signal, crosspoint status bus as indicated by line 6-5 (CSB) 4
8 (see FIG. 6). By issuing signals from 50-4 _15, FIG. 6
As indicated by labeled lines C reference numbers 6-6, the matrix unit (RCU) 40 ₁₅ crosspoint unit (XPU) 32 a serving cell obtained from _0,15 Suiddjipoto integrated circuits (SPICs ) is applied to the 26 _15. Reading a cell from the crosspoint unit (XPU) 32 and applying it to the switchport integrated circuit (SPIC) 26 is described in more detail in Section 4.7.

The crosspoint status unit (XSU) of the matrix unit (RCU) 40
When 50 detects a change in a bit in polling status register 50-2 from an occupied state to an empty state (eg, from 1 to 0), crosspoint status unit (XSU) 50 polls at the first possible time. State release L
Issue a CC cell (see section 2.2.1). In this regard, the matrix unit (RCU) 40 has an internal polling state release register 50-8 that captures state transitions in the corresponding polling state status register 50-2. Basically, when a reset signal for the bit in question appears on the crosspoint status bus (CSB) 48, the polling state release register 50-8 corresponding to the bit position is set. In the state shown in FIG. 6D, after the reset signal indicated by the line 6-5 in FIG. 6C resets the last bit of the poll state status register 50-2 _0, crosspoint status unit (XSU) 50 ₀ 50 Set the last bit of -8 ₀ . The crosspoint status unit (XCU) 50 includes a polling state release register 50.
Check if any of the -8 ₀ bits are set. If any bit is set (like the last bit shown in FIG. 6D), a request is made to issue a polling release LCC cell. When polling state release LCC cell is issued to the switch port integrated circuits (SPICs) 26 ₀ (as shown by FIG At 6D lines 6-6), and the polling state release register 50-8 ₀ is read out Cleared. Figure 6E with clear poll state release register 50-8 _0, when receiving the polling state release LCC cell (switch-port integrated circuit as indicated by line 6-6 in FIG. 6D (SP
IC) (received at 26 ₀ ) showing the clearing of the last bit of the crosspoint status register 26 R ₀ . In this connection point, a new cell switch port integrated circuit (SPIC) 26 ₀ same crosspoint unit by (XPU) 32, i.e., written to the cross point unit (XPU) 32 _0,15.

Therefore, in the scanning process, M which each matrix unit (RCU) 40 is in charge of
Check the status of the crosspoint units (XPUs) 32 connected to the column of the AU 30 (eg, to the read bus 44) and update the appropriate polling status release registers included in the crosspoint units (XPUs) 32. A crosspoint unit (XPU) 32 containing cells is unloaded as output cells through a buffer output gate to a column bus (eg, read bus 44). When the gate of the cross point unit (XPU) 32 opens, only one cell is rejected. The crosspoint status unit (XSU) 50 is updated to indicate that the buffer of the crosspoint unit (XPU) 32 from which the cell was unloaded is now "empty". The unloaded cells are transferred to the reception switch port board (SPB) 24 via the reception matrix unit (RCU) 40. In this way,
All crosspoint units (XPUs) 32 including cells are unloaded one by one.

If reading of cells from the switch core 22 in the manner described above occurs at a lower rate than required by the receiving switch port board (SPB) 24,
A receive queue unit (RCU) 40 generates control cells instead of expected service cells. If the switch port board (SPB) 24 attempts to send a cell to the crosspoint unit (XPU) 32 with the corresponding bit in the crosspoint status register 26R set, before it enters the write bus,
The cell is rejected in the matrix unit (RCU) 40.

Each matrix unit (RCU) 40 also includes a system clock unit (SCU)
52. The system clock unit (SCU) 52 includes a logic circuit for distributing a system clock, and is connected to a system clock bus (SCB) 46.

The matrix unit (RCU) 40 converts the system clock to a cross point unit (RCU).
XPUs) 32 to the gate. Each cross point unit (XPU)
The 32 gate states, open or closed, are set to a semi-permanent state. Its gate state is set from the column, thus avoiding contention.

The write bus 42 and the read bus 44 are connected to the cross point unit (XPUs) 3
2 provides a logical interconnection between the corresponding matrix units (RCUs) 40. Buses 42 and 44 provide information such as buffer full status, read and write buffer control and data.

Therefore, the basic functions of the matrix unit (RCU) 40 include the switch core 22
Align and synchronize cells (including unlinking cell rates) between and the corresponding switch port board (SPB) 24 and switch port board (SPB) 2
4 to provide status information about the crosspoint units (XPUs) 32 so that loading and unloading of service cells from the crosspoint units (XPUs) 32 can be performed while preventing the crosspoint units (XPUs) 32 from being overwritten. included. In addition, a switch port board (SPB
) There are a number of maintenance functions performed by a matrix unit (RCU) 40 controlled from 24.

FIG. 5 shows basic components included in each matrix unit (RCU) 40. In addition to the crosspoint status unit (XSU) 50 and system clock unit (SCU) 52 already described, each matrix unit (RCU) 40 includes a line interface unit (LIU) 53 and a cell synchronization unit (CSU) 54.
, A cell analysis unit (CAU) 55, a cell write unit (CWU) 56, an operation / maintenance unit (OMU) 57, a cell generation unit (CGU) 58, and a cell read unit (CRU) 59.

4.1 Line Interface Unit (LIU) The line interface unit (LIU) 35 includes an LVDS / GLVDS interface for converting a differential signal to a digital level. As shown in FIG. 5A, each matrix unit (RCU) 40 has Vcc, ground, and a set of power connections having a bias voltage for GLVDS. Also, as shown in FIG. 5A, the line interface unit (LI) of the matrix unit (RCU) 40
U) 53, along with five differential amplifier pairs 53-1 to 53-5, three power supply pins for Vcc, ground, and bias, and two power supply pins for providing Vcc and ground to the memory array unit (MAU) 30. Has a pin.

The difference amplifier pairs 53-1 and 53-2 are used to handle the signals DCLK and D-SPSC included in the port-to-core link 27, respectively. The differential amplifier pair 53-1 that receives DCLK outputs a serial clock signal serclk. The output of the difference amplifier pair 53-2 is coupled to a bit synchronization function 53-6 that generates a serial data input signal on line s-data-in. The serial clock signal serclk and the serial data input signal on line s-data-in are later applied to a cell synchronization unit (CSU) 54 as shown in FIG. 5B.

The difference amplifier pair 53-3 is connected to the signal D-
Used to output SCSP. Difference amplifier pair 53-3 is line s-data
The signal D-SCSP is output using the serial output data signal received at -out.
Later, as shown with respect to FIG. 5B, the serial output data signal on line s-data-out originates from cell synchronization unit (CSU) 54.

The system clock bus (SCB) 46 includes lines for clock signals on lines sysclk-in and sysclk-out for each matrix unit (RCU) 40. The clock signal on line sysclk-in is used to generate a clock signal on line sysclk-out, as described below with reference to system clock unit (SCU) 52 and FIG. 5I. Signal SCLK is used to generate signal sysclk-in. The signal SCLK originates from the generated system clock and is distributed via the SPIC (on one of the switch port boards). The system clock typically comes from an external link of the network (eg, a T1 link). The system clock rate is often a multiple of 8 KHz.

4.2 Cell Synchronization Unit (CSU) The cell synchronization unit (CSU) 54 performs serial / parallel conversion,
Align halfwords with cells. Such a conversion is achieved using a specific cell synchronization (sync) pattern in the input direction. Parallel / serial conversion is performed in the output direction to form a bit stream.

The cell synchronization unit (CSU) 54 is a line interface unit (LIU)
A serial bit stream is received on line s-data-in from 53 and the bus p-data-in
Has a serial / parallel converter 54-1 for generating a 16-bit parallel signal. This 16-bit parallel signal generated by the serial / parallel converter 54-1 is also applied to a BIP-8 tester generator 54-2 and a sync tag detector or a cell sorter 54-3.

The cell synchronization unit (CSU) 54 also receives a 16-bit parallel signal on the bus p-data-out, and outputs the signal on the line s-data-out (line interface unit (LIU)).
A) a parallel / serial converter 54-4 for converting to a serial bit stream which is applied to 53). The 16-bit parallel signal on the bus p-data-out is also applied to the BIP-8 tester generator 54-2. As described later with reference to FIG. 5G, the 16-bit parallel signal of the bus p-data-out is
Obtained from a cell generation unit (CGU) 58.

Further, the cell generation unit (CSU) 54 includes a line interface unit (CSU).
LIU) 53 (see FIG. 5A), a line output from the difference amplifier pair 53-1
Serclk serial clock signal received and incoming serial clock signal serclk
Is divided into 16 to generate a parallel clock signal pclk. Parallel clock signal pc
lk is applied to many elements of the matrix unit (RCU) 40. Clock divider 5
4-5 and the serial / parallel converter 54-1 operate on both edges of the serial clock signal on the line serclk.

[0094] The sync (sync) tag detector 54-3 includes a state machine and a comparator that searches for a sync (sync) cell (LSC cell). As described in further detail below in connection with FIGS. 8 and 9, the state machine of sync tag detector 54-3 has three states:
PRESYNC, SYNC0, and SYNC1. Upon detection of an LSC cell, a sync (sync) tag detector 54-3 signals the line "sync-cell" for application to a cell generation unit (CGU) 58, as described below with respect to FIG. 5G. Output.

The BIP-8 tester generator 54-2 examines the link between the switch port board (SPB) 24 and the switch core 22 in a long term to determine the line quality. Each bit of the byte is XOR'ed with the saved parity for the corresponding bit of the previous byte. The result is checked against the control cell containing the expected result. The opposite function applies in the p-data-out direction.

4.3 Cell Analysis Unit (CAU) As shown in FIG. 5C, the cell analysis unit (CAU) 55 includes a cell synchronization unit (CAU).
CSU) 54 receives a 16-bit signal on bus p-data-in. When a cell in the stream of cells arriving on the bus p-data-in is received by the cell analysis unit (CAU) 55, the cell is either (1) a service cell transferred to the cell write unit (CWU) 56, or (2) A control cell passed to the operation management unit (OMU) 57 (see FIG. 5).

The cell analysis unit (CAU) 55 provides a PRI field for the cell (eg, FIG. 4A).
And a PRI decode unit 55-1 that checks the cell type by examining the cell type. As suggested earlier, the serving cell must be a legitimate P
The control cells have PRI values 20-31 while having RI values 0-19. Once determined, the cell type is stored in the cell type register 55-2 during cell processing and applied to the other units of the matrix unit (RCU) 40 on line "cell type". Although not impressively shown in the drawing, the signal of the line “cell type” indicates the cell write unit (CWU) 56 and the operation maintenance unit (OMU)
57 shows the cell type, so that these units do not need to repeat the cell type analysis. Cell type signals, such as those generated by the cell analysis unit (CAU) 55, are transmitted to the cell write unit (CWU) 56 and the operation and maintenance unit (OMU) 57 as to whether they should be engaged. Is shown. The cell write unit (CWU) 56 is in charge if the cell is a service cell, and the operation and maintenance unit (OMU) 57 is in charge if the cell is an LCC cell. If the cell is an LSC cell, the cell write unit (CW
U) 56 or the operation and maintenance unit (OMU) 57 is in charge.

[0098] The cell analysis unit (CAU) 55 also includes an integrity checker 55-3. The integrity checker 55-3 checks for a parity error of the control cell in the first byte, the second byte, and the last sixteenth byte (FBP in FIG. 4B).
, SBP, LWP). If the cell is a variable cell format,
Parity errors in the first and second bytes are checked for all service cells. If an error is detected in any of the cells, a fault signal is generated. Such a parity error causes a quick resynchronization and stores the cause of such a parity error. Cells having a parity fault in the first or second byte are prohibited and are not transferred to the cell write unit (CWU) 56. Moreover, the registers in the crosspoint status unit (XSU) 50 may be bad, which is updated from the switch port board (SPB) 24 after resynchronization. Various cell integrity checking operations are described in section 11.0.

The cell analysis unit (CAU) 55 further includes a PRI swap unit 55-4. For the service cell, the PRI swap unit 55-4 changes the destination value of the PRI field to the source value as described above. The destination value of the PRI field has been saved for use by the cell write unit (CWU) 56 and is applied to line dest-PRI. The service cell itself is a 16-bit bus "wr
ite data "to the cell write unit (CWU) 56.

4.4 Cell Write Unit (CWU) The cell write unit (CWU) 56 is a cross point unit (XPUs) 3
The service cell is stored in the addressed one of the two. The cell write unit (CWU) 56 shown in FIG. 5D includes a cell size logic unit 56-1, a write address counter 56-2, a cross point selection unit 56-3, and a buffer selection unit 56-4. The service cell includes a cell analysis unit (CAU) 5
5 to 16-bit bus “write data” is received, and the cell write unit (CWU) is received.
) Applied to all 56 units. Which switch cell board (SP) is essentially obtained by the line dest-PRI from the cell analysis unit (CAU) 55
B) The destination PRI value indicating whether it is transmitted to 24 is applied to the cross point selection unit 56-3.

As described below, the cross point selection unit 56-3 selects and enables a particular cross point unit (XPU) 32 to which a service cell is to be written during the processing of the service cell. . Based on the value of the field CBQ serving cell, buffer selection unit 56-4 certain crosspoint unit that will service the cell is written (XPU) 32 buffer CBQ ₀ or CBQ ₁ (see FIG. 2) One is selected and a buffer enable signal is applied to the selected buffer to generate a priority signal. Specific crosspoint unit (X
According to the PU) 32 and the buffers therein, the write address counter 56-2 generates a write address for the first 16-bit word of the incoming service cell and applies the same to the bus "write address". For each subsequent 16-bit word of the service cell, the write address counter 56-2 indicates that the cross-point unit (XPU) 32 to which all words of that cell have been addressed.
Generates additional addresses until written to Write address counter 56
-2 generates an additional address for each word of the serving cell according to the cell size as determined by the cell size logic 56-1. The cell size logic 56-1 knows the size of the serving cell based on the field SCS (see FIG. 4A). Write address counter 56-2 starts at zero and counts the cell size.

The write address counter 56-2 is also used by the crosspoint status unit (XSU) 50 to indicate the “occupied” state of the crosspoint unit (XPU) 32 (see FIGS. 5H-1 and 5H-2). The start_write signal and the end_write signal to be set are transmitted. Such signals are also transmitted via a crosspoint status bus (CSB) 48 to another matrix unit (RCU) that manages the affected crosspoint unit (XPU) 32 for unloading purposes.
) Apply to 40 scan status registers 50-4.

The cross point selection unit 56-3 includes an enable register and a multicast register. The enable register is loaded with the decoded PRI value or the start of the cell from the multicast register. The multicast register must be pre-loaded with the address for the intended crosspoint unit (XPU) 32 by the control cell prior to receiving the affected service cell. Multicast registers are only needed if switch core 22 supports point-to-multipoint connections.

4.5 Operation / Maintenance Unit (OMU) The operation / maintenance unit (OMU) basically terminates the control cell or selects one of the registers in the crosspoint status unit (XSU) 50 as the target register. Play a role in doing As shown in FIG.
The maintenance unit (OMU) includes a bitmap target code register 57-1,
Target code register 57-2, traffic mode register 57-3, article number PRI code unit 57-4, zero fill bank unit 57
-5, bitmap decoding unit 57-6, target decoding unit 5
6-7. The 16-bit bus p-data-in is applied from a cell synchronization unit (CSU) 54 to a bitmap target code register 57-1, a target code register 57-2, and a traffic mode register 57-3.

One of the three possible actions is taken with respect to cells transmitted to the operation and maintenance unit (OMU) 57. As a first operation, idle cells are discarded. As a second operation, a sync cell (eg, an LSC cell) is discarded (however, if the “cell sync (sync) status” bit in the LSC cell is set, the LSC cell must be stored. The returned LSC cell must be transmitted). As a third operation, the LCC synchronization cells are processed (whether in bitmap or coded format).

In the above respects, the control cell has a bitmap target code register 57-
1 and the target code register 57-2. If the control cell is a bitmap format cell (FIG. 4B-1), bitmap target code register 57-1 determines so and sends the cell to bitmap decode unit 57-6 to be decoded. . The selected contents of the cell are then loaded (with line "bitmap load") into the desired one of the bitmapped control registers (see Table 5 and section 4.6.1). . The target code register 57-2 functions to enable the target decode unit 57-7 to determine which target control register the bitmap format cell is directed to. According to this determination, the target decode unit 57-7 outputs a signal to the line "register select". The intended one of the registers is identified from the value in the PRI field of the bitmap LCC control cell.

An LCC control cell in coded format can include the address and storage of a target control register or data retrieved from a target control register (see Table 6). Such registers are generally described, for example, in Section 4.6.2. The code in the target register field can also hold a direct command in this context, for example, referring to the clear instruction in Table 6. Direct commands are commands that are executed immediately and are not stored in any register. Examples of a direct command include a clear command and a polling status fetch command. The clear instruction essentially clears the XSU polling status register 50-2 and scan status register 50-in (see FIG. 5H-2). The fetch poll status command forces the switch port to issue and return a poll status status LCC.

A target register field having a load marker and an unload marker is:
It is stored in the target register until the target register is overwritten. The load marker and unload marker are dynamic and are cleared once executed. The unload marker indicating data retrieval from the target register is executed first when a control cell is sent to the switch port board (SPB) 24.

The zero fill bank unit 57-5 includes a cross point status unit (
XSU) 50 is used to perform zero padding on fetch operations involving the target register. In another embodiment involving more gates, zero padding is performed on the target register itself.

4.6 Cross Point Status Unit (XSU) The Cross Point Status Unit (XCU) 50 is a register and coded link connection control (LCC) using bitmap link connection control (LCC) cells (see Table 5). And many control registers, including cells (see Table 6). Furthermore, the crosspoint status unit (XSU) 50 is a matrix unit (RC
U) 40 and a register that holds information about the current fill state for each crosspoint unit (XPU) 32 connected to the write bus 42 connected to the RCU.

4.6.1 Registers Using Bitmapped LCC Cells As shown in Table 5, three types of registers that are updated by sending bitmap LCC cells to the switch core 22 are: is there. These three types of registers are the multicast register, scan block register, and polling status register.

The registers shown in Table 5 as using bitmap LCC cells are 16 bits wide (because bitmap LCC cells carry 16 bits (FIG. 4B
-1)). All registers are updated by sending one bitmap LCC cell to the crosspoint status unit (XSU) 50. The unloading of the registers in Table 5 is done by coded LCC cells as described in section 4.6.2. In Table 5, the value “X” indicates a value that “don't worry”. If the cell has an incorrect CBQ value, the cell is rejected.

4.6.1.1 Multicast Register The 16-bit multicast register of the matrix unit (RCU) 40 holds a bitmap used when the service cell has an indication of “multicast”. Each bit of the bitmap corresponds to a port of the switch core 22, ie, one of the switch port boards (SPBs) 24. For example, bit (0) corresponds to port 0 (switch port board (SPB) 24 ₀ ), and so on until bit 15 corresponds to port 15 (switch port board (SPB) 24 ₁₅ ). In the bit map of the multicast register, a bit set to "1" means that the cell is loaded into the corresponding buffer if it is free as part of the multicast. A bit in the multicast register that is set to "0" means that the corresponding buffer is not included in the multicast. One register location is used for two queues, CBQ ₀ and CBQ ₁ , and the CBQ value for this register is not important.

4.6.1.2 Scan Block Register The cross point status unit (XSU) of each matrix unit (RCU) 40
) 50, there are two 16-bit scan block registers 59-6 (see FIG. 5F) used to mask out the buffer from the scanning process. 16
One of the bit scan block registers 59-6 has a matrix unit (RCU) 4
For CBQ ₀ buffer that is managed by 0 plays a role as a bitmap, another scan block register, as a bitmap for CBQ ₁ buffer for CBQ ₀ buffer that is managed by a matrix unit (RCU) 40 Serve the role of.

The scan block register 59-6 may be set to exclude scanning of certain CBQ ₀ / CBQ ₁ buffers, but loading of that buffer is still active, ie, the cell sets the bit set of the scan block. Is loaded into the buffer. The cell remains in the buffer until the bit is cleared. When the bit is reset, the buffer is re-coupled to the scanning process and the cell is transmitted from the switch port at the correct time.

As in the bit map of the multicast register, bit (0) of the scan block register corresponds to port 0 (switch port board (SPB) 24 ₀ ), and bit 15 corresponds to port 15 (switch). Port board (SPB
) 24 ₁₅ ). Setting a bit to "1" in the scan block register bitmap indicates that the buffer is blocked.

4.6.1.3 Polling Status Register The polling status register and polling status release register in Table 5 are collectively referred to as the "polling status register." Each matrix unit (RCU) 40
For each matrix of the switch core 22 (see FIG. 6), there is a polling status register 50-2 and a polling status release register. Therefore, for a given matrix unit (RCU) 40, there are two polling status registers and two polling release registers. The first polling status register provides a "occupied" or "empty" bitmap representation for each buffer CBQ0 (in core matrix ₀ ) in the crosspoint units (XPUs) 32 connected to the RCU by the write bus 42. The second polling status register includes the RCU
Each buffer CB in the cross point unit (XPUs) 32 connected to
For Q ₁ (in core matrix 0), includes a bitmap indication of “occupied” or “empty”. The first polling state release register indicates whether a transition from “occupied” to “empty” has occurred in the buffer CBQ ₀ (in the core matrix 0) in the cross point units (XPUs) 32 connected to the RCU by the read line 44. The second polling state release register includes a similar indication for each buffer CBQ ₁ (in core matrix 0) in crosspoint units (XPUs) 32 connected to the RCU by read line 44. . The cells that affect the polling status register are:
It is transmitted as described in section 9.0 below.

Thus, for each matrix unit (RCU) 40, there are two 16-bit polling status registers that hold an indication of whether 16 buffers in the same column are free or occupied. I do. Each matrix unit (RCU) 40 has this and poll state status register for the 16 CBQ ₀ buffer that manages, another polling state status registers for the 16 CBQ ₁ buffer which manages. Bit 0 of the polling status register corresponds to a first crosspoint unit (XPU) 32 managed by a matrix unit (RCU) 40, this correspondence continuing up to bit 15, where bit 15 is set by the matrix unit (RCU) 40. It corresponds to the last cross point unit (XPU) 32 to be managed. In each polling status register, a bit that is set to zero indicates that the corresponding crosspoint unit (XPU) 32 queue (as specified by one of CBQ ₀ or CBQ ₁ ) is empty, A bit that sets "1" indicates that the buffer is occupied. As will be described in more detail below in connection with section 9.0, the contents of the bitmapped polling status register are stored in the switch port board (SPB).
) Issued from "retrieve pollstate command
)) In response to a "Polling Status Retrieval Command (retrieve pol
lstate command) is sent to the switch core 22 with the coded LCC cell having an ADR field value of 25. Bits not used in the bitmap LCC for the polling status register are set to "0" and reserved. The bit is equal to "1".

The polling release LCC cell typically has one of the buffers in the columns managed by the queue unit (RCU) 40 that has a polling release register 50-8.
Whenever it experiences a change from "occupied" to "empty", as shown by the corresponding transitions in, transmitted from the matrix unit (RCU) 40, in particular, the cell generation unit (CGU) 58. If the cross point unit (XCU)
If both registers for 32 (CBQ ₀ and CBQ ₁ ) have changed, CB
The cell indicating the contents of the polling status register corresponding to Q ₀ is transmitted first because it has a higher priority. All changes during the ongoing "polling release" are captured and become another "polling release" cell. In each polling state release register, a bit set to "1" indicates that the status of the polling state release register has changed from occupied to empty, while a bit set to "0" maintains the current status. (Either one of occupancy and free space may be present). Unused bits in the bitmapped LCC for the polling state release register are set to "0" and reserved bits are equal to "1".

As previously described with reference to FIGS. 6A-6E, each SPIC 26 has a register 26R (see FIGS. 1 and 6) with one bit position for each crosspoint unit XPU 32 it controls. ). Whenever SPIC 26 writes a cell to crosspoint unit XPU 32, SPIC 26 sets the corresponding bit in register 26R. The positions of the bits thus written to register 26R correspond to the bit positions provided in the bitmapped LCC cells (see Table 5 and FIG. 4B-1). Bit is XPU in register 26R
SPIC 26 cannot transmit new cells to its XPU 32 as long as it is set for 32. The bit for the corresponding XPU 32 is
Only after being reset at R can another cell be transmitted to the XPU 32. The bit in register 26R is set when SPIC 26 receives a cell indicating that the bit for the XPU 32 in question in the polling state release register has been set to "1" (eg, indicating a transition from occupied to free). Is reset. Therefore, a handshake occurs between the SPIC 26 and the switch core 22. This handshake ensures that the XPU 32 is not inadvertently overwritten. To ensure that there is no mismatch between the register 26R and the switch core 22, the SPIC 26 can focus on the current crosspoint status. Attention to the current crosspoint status should be made, for example, by detecting whether SPIC 26 never resets the location in register 26R due to a timeout. At that time (or at regular intervals), the SPIC 26 issues a "retrieve pollstate command". Switch core 22 is SPIC2
6 responds by sending a polling status LCC cell (see Table 5).

For example, a crosspoint (XSU) 50 that holds information about the current fill status of each buffer of each crosspoint unit (XPU) 32, such as a polling status status register and a polling status release register, is included. The registers are updated through a crosspoint status bus (CSB) 48 (see FIG. 6). The information about the registers of the crosspoint unit (XPU) 32 essentially serves two purposes. The first purpose is to recognize (using the polling status register) the crosspoint unit (XPU) 32 that is occupied and therefore unloaded. The second purpose is "occupation"
Is to recognize (using the polling state release register) the crosspoint unit (XPU) 32 that has transitioned from "to" to "free" status, and allow new cells to be transmitted there.

As described in section 10.0, each matrix unit (RCU) 40 performs a scan operation on its associated column. SPIC 26 sets its scanable counter (see Section 4.6.2.4) to set its associated R
The scanning processing period in the CU 40 can be controlled. The scanning process is described in FIG. 18 and is a part of the overall flow of the operation shown in FIG.

FIG. 5H-2 shows an embodiment having a polling status register 50-2, a polling rate register 50-3, a scan status register 50-4, and a scan rate register 50-5. 5H-2 depicted above line DH-L is a portion of each crosspoint unit (XPU) 32 attached to a write bus 42 connected to a particular crosspoint status unit (XSU) 50. It is provided for each buffer CBQ ₀ and CBQ ₁ . Part of FIG. 5H-2, which is drawn below line DH-L, is a specific crosspoint status unit (XSU).
) 50 connected to the read bus 44 connected to each cross point unit (X
PU) 32 for each of the buffers CBQ ₀ and CBQ ₁ .

In FIG. 5H-2, the line p− obtained from the cell synchronization unit (CSU) 54
The data-in parallel input data is applied to both input terminals of the polling rate register 50-3 and the scan rate register 50-5. As described below with reference to sections 4.6.2.8 and 10.0, the parallel input data on line p-data-in is applied to polling rate register 50-3 and Indicates which of the two polling options is included. Similarly, Section 4.6.2
. 9 and section 10.0, the parallel input data on line p-data-in is applied to scan rate register 50-5 to incorporate either of the two scan options. To indicate. Polling rate register 50
The signal to terminal Q at -3 is applied to switch 50-6 as an output select signal, depending on which of the two polling options is selected. The signal to terminal Q of scan rate register 50-5 is applied to switch 50-7 as an output selection signal, depending on which of the two scan options is selected.

The polling status register 50-2 has a set terminal S, a reset terminal R, and an output terminal Q. Set terminal S of polling status register 50-2 receives a signal on line "start-write" from cell write unit (CWU) 56 (see FIG. 5D). According to the contents of the polling status register 50-3, the switch 50-6 applies one of the signals of the lines "start-read" and "end-read" to the reset terminal R of the polling status register 50-2. The lines “start-read” and “end-read”
"Signal, as will be described later with reference to FIG. 5F, the cell read unit (C
RU) 59. The polling status register 50-2 according to the timing depending on whether one of the lines “start-read” and “end-read” is selected.
Apply a signal at the line "poll data".

The state of the polling status register 50-2 of FIG. 5H-2 is applied to the appropriate bits of the polling status register 50-2 by the signal "poll data". For example, if the structure is depicted above the lines DH-L in FIG. 5H-2 is included in the matrix unit (RCU) 40 ₀ cross point status unit (XS U) 50 _0, in particular, cross-point unit If it belongs to (XPU) 32 _0,1 , then the crosspoint unit (XPU) 32 _0,1 when loaded with the serving cell, as indicated by the setting of the polling state register 50-2, The signal on line "poll data" sets bit BCD1 (bit 2 of byte 6) of the bitmapped polling status register (see FIG. 4B-1 and Table 5).

Similarly, the scan status register 50-4 includes a set terminal S, a reset terminal R,
It has an output terminal Q. The reset terminal R of the scan status register receives a signal on line "start-read" from the cell read unit (CRU) 59 (see FIG. 5F). According to the contents of the scan rate register 50-5, the switch 50-7 is connected to the line "st".
One of the signals of “art-write” and “end-write” is set to the scan state register 50.
-4 set terminal S. The signals on the lines "start-write" and "end-write" are obtained from the cell write unit (CWU) 56 as described with reference to FIG. 5D. The Q terminal of scan status register 50-4 applies a signal on line "scan data" according to the timing depending on whether line "start-write" or "end-write" is selected, which is shown in FIG. 5F, applied to a cell read unit (CRU) 59, as described below.

The status of the scan status register 50-4 of FIG. 5H-2 is applied to the appropriate bits of the polling status release register (see FIG. 6) by the signal “scan data”. For example, if the structure is depicted below the line DH-L in FIG. 5H-2, the matrix unit (RCU) 40 ₀ cross point status unit (XSU) contained in 50 _1, in particular, cross-point unit If it belongs to (XPU) 32 _0,1 (as indicated by the setting of scan status register 50-4)
Serving cell is unloaded from the cross point unit (XPU) 32 _{0, 1} Rutoki, line "scan data" signal at the bitmapped poll state release register (see Figure 4B-1 and Table 5) Set bit BCD1 (bit 6 of byte 6).

FIG. 5H-1 shows another more simplified implementation where the polling state and the function of the scan state register are essentially both included in the crosspoint status unit (XSU) 50. Crosspoint function register 50
Performed by -1. Two such registers 50-1 have two buffers (buffers CBQ ₀ and CBQ _{1 for} each such XPU):
It should be understood that there is for each crosspoint unit (XPU) 32 mounted on the read bus 44. The setting terminal of the register 50-1 is connected to a line “start-write” to which a signal is applied from a write address counter 56-2 of a cell write unit (CWU) 56 (see FIG. 5D). A reset terminal of the register 50-1 is connected to a read address counter 59 of a cell read unit (CRU) 59.
-1 is connected to the line "end-read" to which the signal is applied. Register 50-1
Are connected to lines "poll-data" and "scan-data", the latter of which is included in a crosspoint status bus (CSB) 48. Line “scan-dat
a "is applied to a cell readout unit (CRU) 59, as described below with respect to FIG. 5F.

4.6.2 Register Using Coded LCC Cell Cross Point Status Unit (XSU) 5 Using Coded LCC Cell
The command registers contained in 0 are shown in Table 6. In Table 6, sub-columns CBQ, ADR, 4.6.2 under the "Address" column are the coded LCC cells (see Figure 4B-2) needed to address the particular register shown. Refers to the value of a similarly named field. The columns marked "Write" and "Read" indicate the registers loaded and / or unloaded by the coded LCC cells. A value “X” in any column indicates a “don't care” state (eg, any value).

4.6.2.1 Polling Enable Register The polling enable register contains the mode code used by the matrix unit (RCU) 40 in the cell transmission process. The mode code is further described with reference to cell transmission (see Section 9.0 and FIG. 10). Only the two LSBs (least significant bits) of the pollable register are used. Polling enable register 2
One LSB value corresponds to a mode (eg, mode 0, 1, 2, 3). For example, the value “0” of the pollable register refers to mode 0 (for example, transmitting only LSC cells). In mode 0, the internal register is not read. Attempts to read the register become pending as soon as the pollable changes to mode 1, 2, or 3, and are executed. An attempt to write to the register is possible when the value stored in the pollable register is "0".

4.6.2.2 LCC Parity Mode Register The Least Significant (LSB) bit of the LCC parity mode register is used to connect the parity mode. Apply the following code: That is, “0” means that a normal parity is generated, and “1” means that a reverse parity FBP, SBP, LWP is generated in an LCC cell to be transmitted.

4.6.2.3 Cell Integrity Register The cell integrity register holds error indications due to various detected faults in the switch core 22. The integrity check operation is described, for example, in section X0. A detection fault sets the corresponding bit in the register.
That bit is cleared when the register is unloaded. If bit 0 is set, this indicates that the FBP, SBP, or LW
Indicates P. If bit 1 is set, this indicates an unsupported PRI value in the received cell, or a modified CBQ value in the concatenated stream, or too many crosspoint buffer sizes, overwrite attempts in the crosspoint buffer. (Unicast or multicast, not broadcast). Bit 2 is unused. If bit 3 is set, this indicates an FBP or SBP error when unloading the serving cell from the buffer. Bits 4-7 are unused.

4.6.2.4 Scannable Registers The scannable registers forming part of the call size logic 59-2 (see FIG. 5F) control the start and stop of the scanning process. The scan enable register is an 8-bit counter and can be preset to any value from 0 to 255. The counter is decremented by one every 8th byte of the service cell transmitted to the corresponding port. If the value of the counter is at zero, the scanning process stops. If the counter is preset to 255, the countdown is not possible and the scanning process will be possible until a new value (1 or more and less than 255) is loaded into the register.

4.6.2.5 System Clock Register The system clock register (see FIG. 5I) controls the multiplexer for the system clock output of each port. Values 0-15 set the port number of the system clock source. In the system clock register, bits 0-3 contain the port number of the clock source, and bits 4-7 are unused. The system clock register is set to be equal to zero on a read "read" from switch core 22.

4.6.2.6 Self-PRI Register The self-PRI register is a 4-bit read-only register. The value on read is equal to the actual port number. In its own PRI register, bits 0-3 are its own port number and bits 4-7 are set equal to zero.

4.6.2.7 Revision Number Register The revision number register is an 8-bit read-only register that holds information on the revision number of the switch core 22. The first revision of the switch core 22 is “1”. In the revision number register, bits 0-7 contain the revision number starting with "1".

4.6.2.8 Polling Rate Register The switch port boards (SPBs) 24 (“switch ports”) that transmit service cells to each other via the switch core 22 can have different speeds.
In order to achieve the maximum performance of the service cell via the switch core 22, at the beginning or end of the unloading of the service cell, the crosspoint unit (X
It is necessary that the buffer of the (PU) 32 become "free". Depending on the speed differences between the switch port boards (SPBs) 24, this choice is made.

In each matrix unit (RCU) 40 of the switch core 22, two 16-bit registers (one per CBQ, ie, one for buffer CBQ ₀ ), as previously described as polling status register 50-2 One for buffer CBQ ₁ ). The polling rate register 50-3 is shown in FIG. 5H-2. The buffer for one column is indicated as "empty" or "occupied" in the corresponding polling status register 50-2. The contents of the polling status register 50-2 are transmitted by bitmap LCC cells sent from the queue unit (RCU) 40 to the switch port board (SPB) 24 in response to the polling status command to be retrieved.

[0140] The polling rate register defines when the associated buffer is indicated as "free". For each matrix unit (RCU) 40, its matrix unit (RC
For each crosspoint unit (XPU) 32 in the column connected to U) 40, there is one register bit in the polling rate register. This register bit is the same for the two CBQ buffers in the cross point unit (XPU) 32. The lower 8 bits are located at PRC = 0 and the most significant bytes are both at address 14 with RPC = 1.

The indication of occupancy / empty of the buffer polling status register 50-2 is set to “empty” at either the start or end of cell unloading. Whether the indication is set to empty at either the start or end of cell unloading is determined by the setting of the corresponding bit in the polling rate register. When set to zero ("0"), an indication of "empty" is provided at the unload of the last word from the buffer, while setting the corresponding bit of the polling rate register to "1" causes an indication of "empty". Is provided on unloading the first word from the buffer.

FIG. 11 shows, for a specific matrix unit (RCU) 40 _x , the relationship between the polling rate registers managed by the matrix unit (RCU) 40 and the bits in the cross point units (XPUs) 32. A specific matrix unit (RCU) 40 _x shown in FIG. 11 manages a column x of the memory array unit (MAU) 30.

The next scenario in conjunction with FIG. 12 is that when two switch port boards (SPBs) 24, referred to as switch ports X and Y, are configured to transmit service cells to each other, how the polling rate register is Should be set to. First, the bit rate of the opposing switch port is not known. Thus, an indication of "empty" is made when unloading the last word from the buffer. When the switch port sends a serving cell to itself, an indication of "free" is made when unloading the first byte from the buffer, so that the bit rate in this case is always the same. The polling rate register is initialized via the LCC cell for this case.

As shown below the dashed horizontal line in FIG. 12, the two switch ports X and Y can now transmit service cells to each other. In the illustration, the speed of switch port X is assumed to be much faster than the speed of switch port Y, and the corresponding bit in the polling rate register has been set accordingly.

The “empty” indication of the buffer holding the service cell from X to Y is set when the last word is unloaded from the buffer. The "empty" indication of the buffer holding the service cell from Y to X is set when the first word is unloaded from the buffer.

4.6.2.9 Scan Rate Register In order to achieve the maximum performance of the service cell via the switch core 22, an indication of the available cells also needs to be made at the start or end of the service cell loading. is there. The selection is made depending on the speed differences between the switch port boards (SPBs) 24.

[0147] The scan rate register defines when cells in the associated buffer are indicated as "available." The indication is loaded into an internal snapshot register, which is used by the scanning process.

FIG. 13 shows scan rate register bits and cross point units (XPUs).
32 shows the relationship between the two. For each cross point unit (XPU) 32 in a column connected to this matrix unit (RCU) 40, there is one register bit in the scan rate register. This register bit is common for the two CBQ values (16 bits in total). The lower 8 bits are located at RPC = 0 and are the most significant byte at RPC = 1. Both are at address 15.

The "cell available" indication for the buffer is made at the beginning or end of cell loading. Whether the "cell available" indication for that buffer is made at the beginning or end of cell loading depends on the bit setting of the scan rate register corresponding to that buffer. In this regard, setting the scan rate bit to "0" indicates that a "cell available" indication is provided with the loading of the last word into the buffer, while the scan rate bit is set to "1". Setting indicates that a "cell available" indication is provided with the loading of the first word into the buffer. The reset of the indication is always made when the first byte of the cell is unloaded.

The next scenario in conjunction with FIG. 14 is how the scan rate register should be set when two switch ports, X and Y, are to be set up to transmit service cells to each other. Is explained. Initially, the bit rate of the opposing switch port is not known. Therefore, the "cell available" indication is set when the last word into the buffer is loaded.
An indication of "cell available" when the switch port sends a serving cell to itself is made when loading the first byte into the buffer, so that the bit rate in this case is always the same. Through the LCC cell, the scan rate register begins its function.

In the second state of FIG. 14, the two switch ports can now transmit service cells to each other. The speed of switch port X is assumed to be much faster than the speed of switch port Y, and the corresponding bit in the scan rate register is set accordingly. The "cell available" indication of the serving cell from X to Y is made upon loading of the first word into the buffer. The indication of "empty" of the service cell from Y to X is made when the last word is loaded into the buffer.

4.6.2.10 Clear Command When a clear command is sent to switch core 22, the corresponding internal register of this port is immediately cleared. Different data bits in the data field of the LCC cell clear different registers in switch core 22.

The following mapping applies to the clear instruction. The clear instruction having the data bit (0) set to “1” corresponds to the corresponding CBQ
Clears the value poll status register and thus serves as a CLEAR poll status command.

The clear instruction having the data bit (1) set to “1” corresponds to the corresponding CBQ
Clears the polling release (scan state) register of the value, and thus serves as a clear (CLEAR) scan state instruction. If there is no port connected to the column and the polling state bit of the crosspoint in this column is set, the polling state will remain high and the clear scan state will generate cells from this crosspoint. The polling state bit remains high because there is no clock to this port and a cell is generated for each new "clear scan state".

The clear instruction having the data bit (2) set to “1” corresponds to the corresponding CBQ
Clears the value's snapshot register and thus serves as a clear (CLEAR) snapshot instruction.

The clear instruction having the data bit (3) set to “1” corresponds to the corresponding CBQ
Clears the value scan block register and thus serves as a clear (CLEAR) scan block instruction.

The clear instruction having the data bit (4) set to “1” corresponds to the corresponding CBQ
Clears the multicast register for the value and thus serves as a CLEAR multicast command. Recommendation:

4.6.2.11 Poll State Retrieval Command When a Poll State Retrieval Command is sent to switch core 22, the internal polling status is retrieved. There is one instruction for the matrix 0 CBQ ₀ buffer and another for the matrix 1 CBQ ₁ buffer.

4.6.2.12 Scan Block Register The reading of the scan block register is performed by transmitting the coded LCC cell with the ADR field value 28 to the switch core 22. The RPC field value and CBQ field value of the LCC cell provide the corresponding data in the scan block register.

4.6.2.13 Multicast Register To read the multicast register, the switch core 22 sends the ADR field value 3
This is done by sending a coded LCC cell with zeros. The RPC field value of the LCC cell gives the corresponding data in the multicast register.

4.7 Cell Read Unit (CRU) In accordance with the scan state processing, the service cell is
6. Therefore, SPIC 26 can only stop the serving cell from arriving by either blocking all affected crosspoints (XPUs) in that row or setting the scannable counter to zero. . Therefore, the scan state processing (see FIG. 18) is performed for the XPUs 32 (
Scan status register 50-4, see FIG. 5H-2) to find the corresponding XPU
Unload any service cell detected from. Cell readout unit (C
RU) 59 is a cross point unit (XPUs) mounted on the read bus 44
The cell generation unit (CGU) 58 initiates the process of applying the outgoing service cell to the output cell stream of the link 28 after obtaining the outgoing cell from the appropriate one of the 32.

After finding a crosspoint unit (XPU) 32 with a corresponding scan status register 50-4 having an “occupied” status, the buffer of the occupied crosspoint unit (XPU) 32 is unloaded. . Then, the status of the buffer for the unloaded crosspoint (XPU) 32 is changed to "empty" in the polling status release register 50-8. The above operations are performed for all crosspoint units (XPUs) 32 connected to a read bus 44 to which a matrix unit (RCU) 40 is also connected.

As shown in FIG. 5F, the cell read unit (CRU) 59 includes a read address counter 59-1, a cell size logic unit 59-2, a selection unit 59-3, and a set of snapshot registers 59. -4, one set of scan data gates 59-5, and one set of scan block registers 59-6.

When the crosspoint unit (XPU) 32 is to be unloaded,
Crosspoint status unit (XSU) 50 applies the signal on line "scan data" to gate 59-5 of cell read unit (CRU) 59. For each crosspoint unit (XPU) 32 managed by crosspoint status unit (XSU) 50, the configuration of FIG. 5H-2 is duplicated, and thus a separate for each such crosspoint unit (XPU) 32. Line “scan d
It should be recalled that there is an "ata" signal on line "scan data" passes through gate 59-5 if so enabled by the corresponding register in the set of scan block registers 59-6. At this time, the scan signal to be gated corresponds to the corresponding one of the snapshot registers 59-4 and the selection unit 59-3.
Is applied in parallel with

Specific cross point unit (XPU) to which scan signal to be gated belongs
Focusing on 32, selection unit 59-3 sends the appropriate signal to cause the serving cell to be fetched from its cross point unit (XPU) 32. In particular, the selection unit 59-3 applies a signal on the line "buffer enable" of the read bus 44, transmits a signal on the line "read control", and outputs
9-1 allows a particular scan data line to be used to determine which particular cross point unit (XPU) 32 is to be addressed, and a buffer selection on read bus 44 line "priority". A signal is sent to ensure that a selected _one of the buffers CBQ ₀ and CB Q ₁ in the addressed cross point unit (XPU) 32 is correctly specified. Further, the selection unit 59-3 transmits a signal on a line “service cell” to a cell generation unit (CGU) 58.
(See FIG. 5G) to indicate that the service cell is available.

The read address counter 59-1 uses a signal on the line “read control” to determine the address of the cross point unit (XPU) 32 corresponding to the gated scan signal received by the selection unit 59-3. Use The address is applied on line "read address" of read bus 44. At the start of reading, the read address counter 59-1 reads the cross point status unit (X
Set signal on line "start-read" for application to SU) 50 (see FIG. 5H-2).

The bytes of the service cell are obtained by the cell read unit (CRU) 59 on the read bus 44 line “read data”. As the header of each cell is received and applied to cell size logic unit 59-2, cell size logic unit 59-2 determines the length of the cell (ie, from the SCS field (see FIG. 4A)). With cell size logic unit 59-2, read address counter 59-1 is repeatedly applied on line "read address" until all bytes of the cell are obtained, as determined by cell size logic unit 59-2. Address can be incremented. Then, the cell size logic unit 59-2 causes the read address counter 59-1 to issue a signal on the line "end-read" for application to the cross point status unit (XSU) 50 (FIG. 5H-2).

The cell read unit (CRU) 59 allows the cross point unit (XP)
U) When unloading a cell from the 32 buffer, the polling status register 50-2 for the buffer to be unloaded is reset to an "empty" state. In this regard, depending on the value of the polling rate register, the line "
One or the other of the "end-read" or the line "start-read" is used to reset the polling status register 50-2 (see FIG. 5H-2).

When the addressing is performed by the selection unit 59-3 in the above-described manner, the cells of the selection buffer of the addressed cross point unit (XPU) 32 are read by the cell read unit (CRU) on the line “read data” of the read bus 44. ) 59 and a cell generation unit (CGU) 58 (see FIG. 5G).

4.8 Cell Generation Unit (CGU) The cell generation unit (CGU) 58 determines which cells should be sent to the switch port board (SPB) 24 at the next cell interval. Cell generation unit (CGU
) 58 are applied to system clock unit (SCU) 52 via bus p-data-out (see FIG. 5B).

As shown in FIG. 5G, a cell generation unit (CGU) 58 includes a next cell control unit 58-1, a polling enable register (shown as a register 58-2P), a scan enable register (a register 58-2P). 58-2S), parity generator 58-3, control cell fill bank 58-4, PR
An I integrity check unit 58-5 is included. The next cell control unit 58-1 determines which type of next cell is to be sent to the switch port board (SPB) at the next cell interval, and determines the type of the next cell by sending the lines "sync-cell" and "service". -cell ”and“ OAM cell ”, and the polling enable register 5
8-2P, receives a signal indicating the contents of the scan enable register 58-2S. The signal on the line “sync-cell”, the output from the cell synchronization unit (CSU) 54 (see FIG. 5B), indicates that the synchronization cell (LSC cell) is
) 24. Operation and maintenance unit (OMU) 57 (FIG. 5E)
) Received on line "OAM" indicates that an asynchronous control cell has been received from the switch port board (SPB) 24. Cell readout unit (
CRU) 59 (see FIG. 5F), the signal on line "service-cell" is fetched from the service cell and available on PRI integrity check unit 58-5 on line "read-data". Indicates that there is. Cell generation unit (C
GU) 58 uses the signal input thereto, for example, in section 9.0 and FIG.
0 controls the cell transmission procedure described.

In accordance with the cell transmission procedure, the next cell control unit 58-1 sets the line “control-
The signal is output to the control cell fill bank 58-4 by "cell-unload", and is output to the parity generator 58-3 by the line "read-control". Receives a signal from the target code register 57-2 (see FIG. 5E) at PRI integrity check unit 58-5 receives a service cell from cell read unit (CRU) 59 on line "read-data", Performs integrity and sends the service cell to parity and parity generator 58-3 prior to transmission to cell synchronization unit (CSU) 54, line interface unit (LIU) 53, and switch port board (SPB) 24. send.

Basically, the cell has the following priority rule (in order of decreasing priority):
Is transmitted from the cell generation unit (CGU) 58 in accordance with

[0174] 1. Link State Control (LSC) cell if a hunt condition appears or an LSC cell prompt occurs. The LSC cell has an RPIC corresponding to the SPIC 26
Used to maintain alignment on the link to CU 40, ie, to identify cell boundaries. During the hunt state, the RCU 40 cannot find the cell structure,
Instead, the LSC with a code indicating that the RCU 40 is not in synchronization and needs to receive LSC cells until the RCU 40 stops transmitting LSC cells.
Send the cell. Alternatively, the SPIC 26 is not in a synchronized state, and transmits a corresponding request to the RCU 40 so that the RCU 40 continuously issues an LSC cell (however, a code indicating that the RCU 40 is not in a synchronized state is added). Not).

[0175] 2. OAM cells according to early request or prompted polling schedule, also known as pending LCC cells prompted by SPIC 26.

[0176] 3. Service cell / control cell depending on current scan mode schedule. 4. Idle or OAM cells with unprompted CBR (constant bit rate) polling data.

The cell generation unit (CGU) 58 must be able to hold the release of the OAM cell on demand if an LSC cell prompt occurs. An LSC and an idle cell are generated by the control cell fill bank 58-4 and the common part of the OAM cell.

The PRI integrity check unit 58-5 checks whether the value of the PRI field of the cell is
Test for a match with the self PRI using the self PRI register as shown in Table 6. Optionally, the PRI integrity check unit 58-5 can also perform a parity check. Parity generator 58-3 adds or changes the required parity for all cell types.

4.9 System Clock Unit The system clock unit (SCU) 52, which is generally shown in FIG. 5 as having a matrix unit (RCU) 40, is shown in more detail in FIG. 5I.
The signal sysclk-in resulting from SCLK (see FIG. 5) is present for each matrix unit (RCU) 40 and applied to a system clock unit (SCU) 52. Multiplexer (mux) 52-1 includes the appropriate matrix unit (RCU)
From 40, one of the signals sysclk-in applied to the signal interface unit 53 (see FIG. 5A) is selected as the signal sysclk-out. The selection by the multiplexer (mux) 52-1 is controlled by the system clock register 52-2. System clock register 52-2 is set by the LCC cell in coded format. If desired, a slew rate register 52-3 is provided and set to control the slow-to-fast transition speed (V / nanosecond) with the SCLK-OUT and D-SCSP signals (see FIG. 5A). ). Note that four rates can be set.

5.0 Initialization FIG. 7 is a flowchart showing basic steps including an initialization procedure for the ATM switching system of FIG. Upon power-up of the switching system 20, for synchronization, and as depicted by step 7-1 in FIG. 7, each switch port board (SPB) 24 has at least five links in coded format. Transmit the state control cell (LCC cell) to its corresponding matrix unit (RCU) 40 (see FIG. 5). In some cases, such as when the switching system 20 is operating and loses synchronization for any reason, a smaller number of LSC cells (for
For example, three LSC cells) are required. The last LSC cell transmitted in connection with initialization or resynchronization should have an SSC field value of "SYNC" (see FIG. 4B-3). Synchronization is described in more detail in Section 6.0 below.

After synchronization has been established, a series of LCC cells in coded format are transmitted from each switchport board (SPB) 24 to each matrix unit (RCU) 40. The issuance of each of the series of coded LCC cells corresponds to steps 7-2 to 7-9 in FIG.
Is reflected by

The coded LCC cell issued in step 7-2 is used to set the polling enable register (see Table 6) to zero. Polling enable registers are discussed, for example, in Section 4.6.2.1. To achieve initialization of the polling enable register, the coded LC in step 7-2
The field of the C cell is set to the next value (see FIG. 4B-2). That is, PR
I field = 31, ADR field = 4, RPC field = 0. Field CBQ = X, the data field is set to 0 (hexadecimal notation), the write bit is set to "1" and the read bit is set to "0".

Steps 7-3 to 7-7 are performed for each crosspoint unit (XPU) 32 for each matrix unit (RCU) 40 in switching system 20. In step 7-3, an LCC cell clear command is sent to each of matrix 0 and matrix 1. This LCC cell clear command resets the positions of the polling status register 50-2 and the scan status register 50-4 (see FIG. 5H-2) associated with the XPUs owned by the RCU 40.

In step 7-4, two coded LCC cells are transmitted to initialize the scan rate register to the high byte and the scan rate register to the low byte (
See Table 6). Scan rate registers are discussed, for example, in Section 4.6.2.9. The first LCC cell in step 7-4 initializes the scan rate register to the low byte, and the second LCC cell in step 7-4 initializes the scan rate register to the high byte. The high byte of the scan rate is used for the CBQ ₀ buffer of the cross point unit (XPU) 32 (in matrix 0 of the memory array unit (MAU) 30) and the low byte of the scan rate is used for the cross point unit (XPU) 32. used (in the matrix 1 of memory array unit (MAU) 30) relative CBQ ₁ buffer. The byte is set to indicate an unknown rate (if the rate is not actually known).
The fields of the coded LCC cell for the first cell in step 7-4 are set to the following values (see FIG. 4B-2). That is, PRI field = 31, AD
R field = 15, RPC field = 0, field CBQ = X, data field is set to 0 (hexadecimal notation), write bit to “1”,
The read bit is set to "0". The fields of the coded LCC cell for the second cell in step 7-6 are set similarly, except that the RPC field = 1.

In step 7-5, two coded LCC cells are transmitted to initialize the polling rate register to the high byte and the polling rate register to the low byte (see Table 6). The polling rate register can be found, for example, in section 4.6.2.2.
8 In a manner similar to that for the scan rate register, the byte is set to indicate an unknown rate (if that rate is not actually known). The fields of the coded LCC cell for the first cell of step 7-5 are set to the following values (see FIG. 4B-2). That is, PRI field = 31, ADR field = 14, RPC field = 0, field CBQ =
X, the data field is set to 0 (hexadecimal notation), the write bit is set to "1" and the read bit is set to "0". The fields of the coded LCC cell for the second cell of step 7-5 are set similarly, except that the RPC field = 1.

In step 7-6, the coded LCC cell is transmitted to enable the scan enable register (see Table 6). Scan enable registers are discussed, for example, in section 4.6.2.4. The fields of the coded LCC cell of step 7-6 are set to the following values (see FIG. 4B-2). That is, PRI field = 31, ADR field = 7, RPC field = 0,
Field CBQ = X, the data field is set to FF (hexadecimal notation), the write bit is set to "1" and the read bit is set to "0".

In step 7-7, the coded LCC cell is transmitted and sets the polling enable register to mode 1 (see Table 6). The significance of mode 1 is explained with reference to FIG. The fields of the coded LCC cell of step 7-7 are set to the following values (see FIG. 4B-2). That is, PRI field = 31, AD
R field = 4, RPC field = 0, field CBQ = X, data field is set to 01 (hexadecimal notation), write bit is set to “1”,
The read bit is set to "0".

In step 7-8, the process waits for a time equivalent to the duration of the 32 maximum-length (eg, 56 bytes) service cells. During this wait time, any cells created are ignored. The waiting time of steps 7-8 allows any sporadic service or control cells to drain out of the switching system 20. If, for example, a polling status register of the matrix units (RCUs) 40 may occur at power up, it indicates that there are cells available for reading, or another matrix unit (RCUs) 40 If there is no connected switch port board (SPB) 24, sporadic service cells may occur. Such sporadic service cells are flushed out after the link is synchronized and the polling enable mode is set to mode 1, 2, or 3.

6.0 Synchronization As shown in FIG. 1, each switch port board (SPB) 24 is connected to the switch core 22 by bidirectional links, particularly links 27 and 28. On each side of the link is a sync (sync) tag detector or cell aligner aligner. For example, in the matrix unit (RCU) 40, a sync (sync) tag detector 54-3 is provided in a cell synchronization unit (CSU) 54 (see FIG. 5B). The role of the sync tag detector is to detect LSC cells.

As shown in FIG. 3, cells having various sizes are transferred as a bit stream between the switch port board (SPB) 24 and the switch core 22 in both directions.
At links 27 and 28, there is no clear information about the start of the cell other than the internal structure of the cell. Therefore, the switch core 22 and the switch port board 24
Must perform cell alignment to synchronize links 27 and 28.

Synchronization is achieved by inserting LSC cells [see FIG. 4B-3] as needed. The LSC cell transferred from the switch port board (SPB) 24 to the switch core 22 is analyzed by the synchronization tag detector 54-3, and the LSC cell transferred from the switch core 22 to the switch port board (SPB) 24 is a switch port board. At (SPB) 24, it is parsed by a corresponding, similarly operating synchronous tag detector. The sync tag detector has no effect except on the LSC cells.

Synchronization tag detector and synchronization (sync) in the switch port board (SPB) 24
8) Each of the tag detectors 54-3 comprises a state machine device operating according to the state diagram shown in FIG. In order to achieve quick and fast synchronization and maintain the operational state of the links 27 and 28, both sides of the link, ie, the switch core 22 and the switch port board (SPB) 24, must be able to report their state using LSC cells. Hereinafter, the operation of the synchronous tag detector will be generally described.
It will be appreciated that the description can be made using both the -3 and the synchronous tag detector in the switch port board (SPB) 24.

The incoming LSC cell from the corresponding side is compared with a predefined pattern for LSC cells [see FIG. 4B-2 and section 2.2.2.1] by the sync tag detector. The SSC field indicates that a synchronous (sync) tag detector
Generated in PRESYNC state (indicated by SC value 11), one of the synchronization states,
For example, SYNC0 or SYNC (indicated by the SSC value “SYNC”, ie, 00)
1 indicates whether or not it was generated.

As shown in FIG. 8, the sync (sync) tag detector stays in the PRESYNC state until three consecutive error-free LSC cells are received, then one of the two sync states (SYNC0 or SYNC1). to go into. When both sides of the link, the switch port board (SPB) 24 and the switch core 22 reach the SYNC1 state, the service cell and the LCC cell are switched to the switch port board (SPB) 24 and the switch core 2
Between the two.

Each service cell provides information on its size, especially the SCS field [FIG. 4A
Reference]. This size information is used to maintain cell synchronization. The predetermined cell defect as detected by the integrity check unit 55-3 [see FIG. 5C]
Put the sync tag detector in the PRESYNC state. If an LSC cell with a PRESYNC value in the SSC field is received in the SYNC1 state, the state machine enters the SYNC0 state. In the SYNC0 state, (PR is set in the SSC field).
Until any cell (other than the LSC cell with the ESYNC value) is received,
An LSC cell having a SYNC value in the C field is always transmitted.

The following LSC cell transmission rules describe the operation of the synchronization state machine of FIG. Transmission rule 1: In the PRESYNC state, the following operation is performed. (1) An LSC cell having PRESYNC in the SSC value is transmitted, and received cells other than the LSC cell are discarded. (2) If three error-free LSC cells are received consecutively and the third LSC cell has PRESYNC in the SSC value, the state transitions to the SYNC0 state. (3) If three error-free LSC cells are continuously received and the third LSC cell has the SYNC state, the state shifts to the SYNC1 state.

Transmission rule 2: In the SYNC0 state, the following operation is performed. (1) Only the LSC cell having SYNC in the SSC value is transmitted, and cells other than the LSC cell are discarded. (2) When an error-free cell other than the LSC cell having the PRESC in the SSC value is received, the state shifts to the SYNC1 state. (3) If an error exists in the received cell, the state transits to the PRESYNC state.

Transmission Rule 3: In the SYNC1 state, the following operation is performed. (1) Permit transmission of a service cell and a control cell. (2) When leaving the SYNC1 state, the switch core 22 completes the ongoing cell transfer. (3) If an LSC cell having no error and having the SSC value of PRESYNC is received, the state transits to the SYNC0 state. (4) If an error exists in the received cell, the state transits to the PRESYNC state.

FIG. 9 illustrates state transitions that may be a sync tag detector 54-3 in the example of synchronization and resynchronization. In FIG. 9, the SSC value of the LSC, for example, the state of the synchronous tag detector that issued the LSC cell is shown in parentheses. The notation “SYNC” in parentheses generally refers to synchronization, eg, SYNC0 or SYNC1.

In FIG. 9, first, assuming that the switch core 22 is in the PRESYNC state, the switch core 22 receives the LSC cell having the PRESC in the SSC value, and further switches the LSC cell having the PRESC in the SSC value into the switch core. 22
To the switch port board (SPB) 24. After three consecutive receptions of the LSC cell, the sync (sync) tag detector 54-3 transitions to the SYNC0 state, and transmits an LSC value having the SYNC value as the SSC value. Switch port board (SPB) 24
Transitions to the SYNC1 state after receiving three LSC cells (operation of transmission rule 1 (3
)). Then, after receiving the LSC cell having SYNC in the SSC value,
Transition to the C1 state, an additional LSC cell with SYNC in the SSC value is transmitted. At this time, the switch core 22 and the switch port board (SPB) 24
Are in the SYNC1 state, and the service cell can be exchanged via the links 27 and 28.

After the synchronization is established, the synchronization (sync) tag detector 54-3 of the switch core 22 sets the SSC
Upon receiving an LSC cell having a value of PRESYNC, the synchronization tag detector 54-3
Returns to the SYNC0 state and responds with an LSC cell with SYNC to the SSC value.
If an LSC cell with PRESYNC in the SSC value continues to be received, the sync tag detector 54-3 returns to SYNC0 and responds with a continuous stream of LSC cells.

When a defect is found in the received service cell, the switch core 22
Go to the YNC state and start sending LSC cells with the SSYNC value of PRESYNC to the switch port board (SPB) 24. These LSC cells cause the switch port board (SPB) 24 to transmit an LSC cell having PRESYNC in the SSC value. After receiving such an LSC cell for three consecutive times, the synchronous tag detector 54-3 shifts to the SYNC1 state again and the service cell starts to flow.

The cell stream shown in FIG. 3 is constantly maintained between the switch port board (SPB) 24 and the switch core 22. Continuity is measured by cell rate decou
pling). The switch core 22 (in particular, the cell generation unit (CGU)
) 58 [see FIG. 5G]) has the SSC field set to the current synchronization state of the switchport board (SPB) 24 and switch core 22 when there are no service cells or LCC cells to transmit on the link 28. ) The LSC cell in the direction from switch core 22 to switch port board (SPB) 24, i.
Send to the two-port link 28. The switch port board (SPB) 24
If there are no service cells or LCC cells to send on link 27, the LSC cell with the SSC field set to the current synchronization state is sent from switch port board (SPB) 24 to switch core 22, i.e., port-to-switch. Send to core link 27;

7.0 Cell Reception After synchronization of the cell streams, the serving cell and the control cell are processed separately as described below.

7.1 Control Cell Reception The control cell, ie both the LSC cell and the LCC cell, is different from the serving cell and ends in the matrix unit (RCU) 40. The received LSC cells are basically used for synchronization purposes, eg as described in section 6, and as described above [see FIGS. 8 and 9], the matrix unit (RCU) 40 and especially the synchronization tag detector 5
Affects state machine 4-3. Whether the LCC cell is coded (see FIG. 4B-1) or bit-mapped (see FIG. 4B-2), one matrix unit (RCU) 40 in the switch core 22 is connected to the connected switch port. Board (S
PB) 24 to control and operate. In this regard, each switch port board (SPB) 24 controls its own queue unit (RCU) 40.

In controlling the matrix unit (RCU) 40, some LCC cells are used to update control registers inside the matrix unit (RCU) 40, particularly the registers of the crosspoint status unit (XSU) 50 shown in Table 6. . The received LCC cell contains data for this purpose. Up to 16 bits of data in the register can be updated by one bitmapped LCC cell [see section 2.2.2.1]. In a coded LCC cell, 8 bits are written to or read from a register of the matrix unit (RCU) 40. Other LCC cells contain commands executed by the matrix unit (RCU) 40.

Table 7 shows the various fields (PRI, ADR, Write, Read, [see FIG. 4B-2]) of the LCC cell received by the matrix unit (RCU) 40 and the operations performed for each field. This operation includes an operation performed by the matrix unit (RCU) 40, including the issuance of an arbitrary response cell. As shown in Table 7, the LCC cells received at the matrix unit (RCU) 40 generally serve the following purposes.

(1) Update of a register (see Table 6) inside the matrix unit (RCU) 40. The received LCC cell contains the data and address for the register. (2) Start reading registers in the matrix unit (RCU) 40. The received LCC cell contains the register address, and the RCU responds with the LCC cell containing the actual data of the addressed register.

(3) Update of a register inside the matrix unit (RCU) 40 and start of reading of the same register. The received LCC cell contains the address of the register to be updated and the update data to be stored in the addressed register. At the same time as the update,
The CU responds with an LCC cell confirming the data written to the register. (4) From the connected switch port board (SPB) 24 to the matrix unit (R
CU) 40 command load. The received LCC cell contains the command code.

[0210] Consecutive coded LCC cells for writing to the registers of the matrix unit (RCU) 40 are allowed. However, only one raw coded LCC cell for reading the register of the matrix unit (RCU) 40 is allowed. During the readout period, writing to the registers of the matrix unit (RCU) 40 using coded LCC cells

[0211] Polling state retrieval command ("retrieve_pollstate_command") (see Table 6)
Not allowed except. The polling status fetch command can be transmitted at any time from the switch port board (SPB) 24, and the queue unit (RCU) 40 receives (
Respond the polling status (assuming the RCU is in sync). The provisions of this paragraph apply only to coded LCC cells, not to bitmapped LCC cells. The bitmapped LCC cell is the coded LC
No interference from the C cell.

As mentioned above, Table 7 shows the possible LCC cell flows, ie, the matrix units (R
CU) 40 and the switch port board (SP) issued by the RCU
B) shows the LCC cell responding to 24. In Table 7, the switch core 22 generated when one buffer becomes empty due to no cell being loaded is shown.
With the exception of the last LCC cell (polling state) initiated by the internal logic of, all cell flows are initiated by the switch port board (SPB) 24 connected to the corresponding matrix unit (RCU) 40.

7.2 Service Cell A service cell passes from one port to another through the switch core 22, ie, from one switch port board (SPB) 24 to another switch port board (SP).
B) Guided to 24. Also, the service cell can be copied to some or all other ports. The copy to some ports of the service cell is “
Copies to all ports are known as "multicasts", respectively, as "broadcasts.""Multicasts" and "broadcasts" are described elsewhere herein, eg, in Section 8.0 below.

8.0 Cell Buffering The header of a service cell has the destination port number of the cell in the PRI field (see FIG. 4A). For example, if the switch port board (SPB) 24 ₁₅ is the destination port, the PRI field for that cell received by the queue unit (RCU) 40 would be “15”. However, the cell is a crosspoint unit (X
PU) 32 (eg, a cross point unit (XPU) in this example)
32 ₁₅ ), the PRI value originally stored in the cell received at the matrix unit (RCU) 40 is stored in the switch port board (SPB) 24 that issued the service cell. Replaced by the value corresponding to the port number.

Therefore, SPB24_FifteenSPB24 with PRI value "15" to go to ₀ In the example of a service cell issued by XPU32, the PRI value of the service cell is XPU32_FifteenReplaced with "0" by matrix unit (RCU) 40 before transmission to
Can be The change of the PRI is performed by the PR of the cell analysis unit (CAU) 55 [see FIG. 5C].
This is performed by the I swap unit 55-4. PRI value (for example, port number)
Occurs in one byte of the service cell including the parity bit, and
A new parity bit FBP must be determined and replaced with a serving cell.
No.

The service cell header also contains a 2-bit CBQ that indicates which of the two buffers CBQ ₀ and CBQ ₁ of the cross-point unit (XPU) 32 that the service cell is to be addressed by the PRI. Have. in addition,
The second byte of the serving cell contains a traffic type indicator (TTI) [see FIG. 4A].

If the traffic type indicator (TTI) indicates multicast, the cell is copied to some crosspoint units (XPUs) 32. In particular,
Cross point unit (XPU) 3 to receive a multicast service cell
2 is defined by a 16-bit register inside the matrix unit (RCU) 40, in particular the multicast register shown in Table 6 [section 4.6.2.1.
3]. Within the queue unit (RCU) 40, there is only one multicast register. Each bit of the multicast register is a crosspoint unit (X) on a column served by a matrix unit (RCU) 40 that receives cells.
PU) 32 ₀ to 32 ₁₅ . An active bit in the multicast register indicates that a cell is loaded into the corresponding XPU 32 in the column.
Therefore, the multicast register must be loaded before the serving cell arrives.

When the traffic type indicator (TTI) indicates “broadcast”, the service cell is supplied to all the switch port boards (SPBs) 24.
The multicast registers inside the queue unit (RCU) 40 are not used for broadcast.

During the multicast, the serving cell is copied to a cross point unit (XPU) 32 with an empty buffer (either CBQ ₀ or CBQ ₁ ). If the multicast register requires loading into the XPU 32 with a free buffer, an error is indicated by the cell integrity register 55-3 (see FIG. 5C). A cross point unit having an empty buffer CBQ ₀ or CBQ ₁ (
(XPU) 32 remains loaded. Nearly the same procedure is used during the broadcast. That is, an empty buffer is loaded independently of the other buffers. However, no errors due to free buffers are presented during the broadcast.

9.0 Cell Transmission At the transmitting side of the matrix unit (RCU) 40, cells from different sources are multiplexed by a cell generation unit (CGU) 58 so as to form a continuous cell stream from the switch core 22. And output [see FIGS. 5 and 5G].

The cell transmission rate from the matrix unit (RCU) 40 is determined by the same clock as the clock used for cell reception, for example, DCLK. DCLK is supplied from a switch port board (SPB) 24 connected to this port. As shown in FIG. 5A, signal DCLK is eventually frequency-divided (by frequency divider 54-5 [see FIG. 5B]) to produce signal pclk. Therefore, each switch port board (SP
B) 24 supplies its DCLK signal to the associated RCU 40.

The cells transmitted from the switch core 22 include both control cells and service cells. The next cell control unit 58-1 [see FIG. 5G], when requested to accept each cell indicated by the name of each line, sends a synchronization cell (syn) on the line.
c-cell), control cell (control-cell) and service cell (service-cell) are received. The next cell control unit 58-1 sets internal requests for cell output according to the signals taken out on these lines, and processes these requests as shown in FIG. Once a request for a particular type of cell is satisfied, the request is "cleared."

Before the control cell is transmitted from the matrix unit (RCU) 40 to the corresponding switch port board (SPB) 24, a parity bit is determined and added. The parity bit for the serving cell is checked by the PRI-integrity check unit 58-5 (see FIG. 5G) when unloaded from the crosspoint unit (XPU) 32. Cells with incorrect parity bits are discarded and indicated in the cell integrity register.

FIG. 10 is a flowchart showing a cell transmission process from the switch core 22. Which of the different options or modes (1, 2 or 3) is valid is determined by the contents of the polling enable register [see Table 6 and section 4.6.2.1].

Modes 2 and 3 in FIG. 10 are fundamentally different from mode 1 by giving a predetermined priority to the generation of a service cell. In particular, modes 2 and 3 use a specific byte counter (see especially steps 10-18) to ensure that the serving cell has a higher priority than the polled LCC cell for a given time. Such a predetermined "time" can be set to the time for transmitting a 32 or 64 byte service cell in modes 2 and 3, respectively.

FIG. 10 shows each of three modes in cell transmission, including transmission mode 1, transmission mode 2, and transmission mode 3. Transmission mode 0 involves only one LSC cell transmission for synchronization purposes in step 10-0. The operation performed in the remaining transmission modes will be described below. Although FIG. 10 illustrates the general concept of operation, it should be understood that some rare exceptions are allowed on rare occasions such as power ups and bit errors.

Recall that with reference to FIG. 10, the polling release LCC cell described in section 4.6.1.3 shows a cross point unit (XPU) 32 with a released or “empty” buffer. There is a need. Release polling status LCC
The cell is transmitted each time the buffer (either CBQ ₀ or CBQ ₁ ) changes from an occupied state to an empty state. If the state of buffers with different priorities changes, two polled LCC cells are transmitted, the first cell for queue CBQ ₀ and the second cell for queue CBQ ₁ .

In addition, the 8th byte (eighth), also known as the scan enable register, or cell size logic 59-2 [see Section 4.6.2.4 and FIG. 5F]
byte) There is a service cell counter. The data read signal is used to determine the cell size and control reading from the cross point so that the entire service cell can be read. In addition, the data read signal is also used for decrementing the scan enable counter. The scan enable counter is decremented every time 8 bytes of the service cell are transmitted.

When the value of the eighth byte service cell counter is equal to zero, the service cell ends. Thereafter, the read control prohibits the next service cell read. After the scan enable counter is loaded with a new (non-zero) value, the next service cell column is unloaded. In other words, the scanning process is restarted by writing the value (1 to 255) to the scan enable register [see Table 6]. When the value of the eighth byte service cell counter is preset to 255,
All decrements are invalidated, and the scanning process always continues.

In FIG. 10, ongoing cell transmission is always completed before the next cell is transmitted, even if the next cell has a higher priority. Furthermore, only one byte counter is used independently of the CBQ value in the serving cell.

9.1 Cell Transmission Mode 1 The cell transmission mode 1 follows a priority system according to the type of a cell to be transmitted. The cell transmission priorities represented by FIG. 10 are as follows, and will be described in order from the highest priority.

(1) When an LSC cell transmission request is received on a synchronous cell line (step 1
0-1), the LSC cell is transmitted according to the link synchronization process (for example, see section 6.0), and the LSC cell transmission request of the next cell control unit 58-1 is cleared (step 10-2).

(2) In step 10-3, the crosspoint status unit (XSU) 5
If an LCC cell requesting reading of a register 0 (shown in Table 6) is received on the control cell line, the requested coded LCC cell is sent out and the request is cleared (step 10-4). Step 10-4 is not triggered by the polling release LCC cell.

(3) If a polling status request is received upon receipt of the “polling status extraction command”, a bit-mapped LCC cell having a polling status is issued in step 10-6. The contents of the bitmapped LCC cells are stored in the polling status register [Section 4.6.
1.3]. Furthermore, the polling state changes when such a buffer is cleared. The polling status request for buffer CBQ ₀ is given a higher priority than the polling status request for buffer CBQ ₁ .

(4) In step 10-7, the polling status register changes from “occupied” to “occupied”.
If it has changed to idle "is detected, the bit of the bitmap poll state release LCC cell at step 10-8 are transmitted. One poll state status register buffer in the matrix 0 (i.e., CBQ ₀ buffer) It has a map, buffers and the other poll state status register matrix 1 (i.e., CBQ ₁ buffer) in a bitmap in the section 4.6.1 .3 and Table 5 reference. step 10-7, Buffer CBQ ₀ is given a higher priority than buffer CBQ _{1. The} bitmap LCC cell transmitted in step 10-7 is an individual of all buffers released since the last "release polling" command. Transport information about the priority of the CBQ (CBQ ₀ or CBQ ₁ ).

Step 10-9 in FIG. 10 includes steps 10-2, 10-4, 10-6 and 1
If no operation is performed in 0-8, it indicates that a scan process or an operation is performed. The scanning process is described, for example, in section 10.0 herein.

After the scan in step 10-9 is completed, in step 10-10, the service in which the above-described four priority rules for the cell generation unit (CGU) 58 [see section 4.8] are supplied from the switch core 22. A determination is made whether a cell is needed. If the determination in step 10-10 is affirmative, step 10
At -11, the service cell is transmitted.

If the determination in step 10-10 is negative, LS is determined in step 10-0.
C cells are transmitted from a cell generation unit (CGU) 58. In other words, if there are no other types of cells to be transmitted, the LSC cells are transmitted according to the cell rate separation process.

9.2 Cell Transmission Mode 2 Cell transmission mode 2 limits the number of bitmap LCC cells that include polling state information, and instead allows more service cells to be transmitted. If there is a service cell to be transmitted, transmission of the polling state information cell is permitted only after a service cell of at least 32 bytes has been transmitted since the immediately preceding polling state information cell was transmitted.

Steps 10-12 to 10-17 of executing mode 2 transmission are similar to steps 10-1 to 10-6 of executing mode 1. However, step 10
At -18, a check is made as to whether the polling enable counter has expired. The polling enable counter is a cell size logic unit 58-
2 [see FIG. 5H]. In step 10-18, the polling enable counter is referenced so that too many polling release LCC cells are not issued if the serving cell is continuously (ie, continuously) transmittable.

For example, a service cell having a length of 8 bytes corresponds to a cross point unit (XP
U) 32, the output speed of the serving cell is reduced if polling release LCC cells are interspersed between such serving cells. When mode 32 is set, polling release LCC cells cannot be issued more frequently than every 32 bytes of consecutive service cells. This means that at least four 8-byte long service cells exist before issuing the polling release LCC cell.

The polling enable counter is decremented for each byte of the service cell according to a signal from the cell size logic unit 59-2. Once the polling release LCC cell is issued, the polling enable counter is reset. The polling enable counter is built into the queue unit (RCU) 40 and is not controlled by the switchport integrated circuit (SPIC) 26. The switchport integrated circuit (SPIC) 26 merely indicates which particular mode will cause cell generation there.

Therefore, the polling enable counter is incremented by one for each byte of the transmitted service cell. The final value of this counter is 32 or 64 (
Respectively, depending on whether the number of polling enable registers is two or three). Unsolicited polled LCC cells are only sent if this byte counter has reached its final value or if there are no service cells to send.

If the polling enable counter for the service cell referred to in step 10-18 has expired, for example, if it is 32 or more in mode 2, the cell transmission priority becomes equal to mode 1. In particular, steps 10-24 to 10-2
The applicable one of the nine has the possibility to be activated as shown in FIG. Step 10-28 in which the service cell is transmitted is also (Step 10-
It is responsible for incrementing the polling enable counter by the length of the cell (referenced at 18).

If the polling enable counter for the service cell referred to in step 10-18 has not expired, a scan process is performed (step 10).
-19). Then, at step 10-20, it is checked whether a service cell has been requested (in a manner like step 10-10). If a service cell has been requested, the service cell is provided in step 10-21, and step 10-
The byte counter referenced at 18 is incremented according to the length of the cell.
If a service cell has not been requested, it is checked in step 10-22 whether there is any buffer whose polling state has changed to an empty state. If the determination is negative, an LSC cell is transmitted (step 10-23). Otherwise, in step 10-24, the polling release LCC cell is transmitted in a manner similar to step 10-8.

9.3 Cell transmission mode 3 This mode is the same as mode 2 except that the polling state information cell can be transmitted only after a service cell of at least 64 bytes has been transmitted since the last transmission of the polling state information cell. is there.

10.0 Scan Process The scan process is a process of determining when the switch core 22 can output a cell from the buffer CBQ ₀ or CBQ _{1 of the} cross point unit (XPU) 32. As described above, the synchronization (LSC) cell is a switch core 22 according to FIG.
(See Section 6.0). On the other hand, the LCC cell is basically transmitted from the switch core 22 as a response from the LCC cell issued by the switch port board (SPB) 24. LCC cell exchanges are shown in Table 7 and described in sections 7.0 and 9.0.

The switch core 22 also issues an LCC polling status cell that informs the switch port board (SPB) 24 of the availability of service cells from a number of crosspoint units (XPUs) 32. In view of the fact that their contents are based on the contents of a polling state release register (see, for example, polling state release register 58-8 in FIG. 6), one type of polling state cell is also known as a polling state release cell. Have been. Thus, the polled state cell provides the switch port board (SPB) 24 with an indication of whether the same row of buffers is "empty" or "occupied."

A certain buffer (or a plurality of buffers), for example, a switch port board (S
When the CBQ ₀ or CBQ ₁ of any of the 16 cross point units (XPUs) 32 in the row monitored by the PB 24 is released (ie, the state changes from “occupied” to “empty”), The polling release LCC cells are transmitted according to the cell transmission rules described in section 9.0 with reference to FIG. As soon as it is possible to start loading new cells into the buffer, the buffer is "empty". When a cell is loaded, the buffer is marked "occupied."

The transmit and receive switch ports (ie, switch port board (SPB) 2
Depending on the speed difference in 4), an "empty" indication of the buffer is made according to one of the two polling options. These two polling options are shown in FIG. In the first polling option, "empty" of the buffer is displayed when cell unloading from the buffer is started (see point P1 in FIG. 15). In the second polling option, "empty" of the buffer is displayed when cell unloading from the buffer ends (see point P2 in FIG. 15). The polling rate register (section 4.6.1.3) determines which of the first and second polling options is used.
And 4.6.2.8). The first polling option is commonly used when the sending switch port speed is equal to or lower than the receiving switch port speed, or when the speed difference is less than 4%. The second polling option is generally used when the transmission-side switch port speed is equal to or greater than the reception-side switch port speed, or when the speed difference is unknown.

Each matrix unit (RCU) 40 scans a buffer on an assigned column of the memory array unit (MAU) 30 (see FIG. 1). A buffer having a “cell available” state (for example, CBQ ₀ or CBQ _{1 of the} cross point unit (XPU) 32) is unloaded using the service cell output from the switch core 22, and the transmitted buffer is “empty”. Is marked.

“Cell Available” is displayed immediately if there is a possibility that unloading of cells from the buffer may be started. When the first word of a cell is unloaded from the buffer,
The buffer is marked as "empty".

According to the speed difference between the receiving side and the transmitting side RCU, a “cell available” indication of the buffer is made according to one of the two scan options shown in FIG. In the first scan option, as indicated by a point Q1 in FIG. 16, when the cell loading from the buffer is started, the "cell available" display of the buffer is made. In the second scan option, as shown by the point Q2 in FIG. 16, when the cell loading from the buffer is completed, the "cell available" display of the buffer is made. Which of the first and second scan options is used is determined by the scan rate register (section 4).
. (See 6.1.3 and 4.6.2.9). As shown in FIG. 16, the first scan option is generally used when the transmitting switch port speed is equal to or lower than the receiving switch port speed, or when the speed difference is less than 4%. The second scan option is generally used when the transmitting switch port speed is equal to or greater than the receiving switch port speed, or when the speed difference is unknown.

As described above (see FIG. 2), two buffer queue matrices (named CBQ ₁ or CBQ ₁ ) exist in each column of the memory array unit (MAU) 30. CBQ ₀ has a higher priority than CBQ ₁ . With buffer queue CBQ ₀ or CBQ _1, two snapshot registers are provided for each queue. The real buffer state is loaded into the snapshot register. The buffer status is masked by the contents of the corresponding scan block register. The actual buffer status is a scan status register (for example, see scan status register 50-4 in FIG. 6).
Holds. The "cell available / empty" state of each buffer is copied to the snapshot register. After loading the snapshot register, all bits corresponding to CBQ ₀ are processed and these bits are cleared when the buffer is unloaded. The buffers are processed in order, ie, buffer 0, buffer 1, and so on. Once all bits corresponding to CBQ ₀ have been cleared, the next time the routine is called, a new snapshot of CBQ ₀ is taken. The same processing is performed until all the bits of the snapshot register are cleared. If all bits of the snapshot register are zero in the new snapshot, CB
Q ₁ is scanned. The scanning of CBQ ₁ is performed according to the same principle.

FIG. 17 illustrates the basic scan process (shown as 17-0). In step 17-1, the determination of whether a snapshot register queue CBQ ₀ is empty is performed. If the snapshot register queue CBQ ₀ is empty, in step 1 7-2 snapshot register queue CBQ ₀ is loaded with the state of (masked by scan block 0) queue CBQ _0. Then, in step 17 -3, the determination of whether a snapshot register queue CBQ ₀ is empty is performed.

If the determination in step 17-3 is affirmative, in step 17-4 queue C
If the determination is made BQ ₁ of the snapshot register is empty. If the snapshot register queue CB Q ₁ is empty, at step 17-5, the snapshot register queue CB Q ₁ is loaded (the masked scan block 1) of queues CBQ ₁ state. Then, at step 17-6, determination of whether a snapshot register queue CBQ ₁ is empty it is performed.

[0257] In step 17-2, the snapshot register queue CBQ ₀ is loaded with the state of (masked by scan block 0) queue CBQ _0. Then, at step 17-3, if the snapshot register queue CBQ ₁ is empty, the service cell transmission request is not issued (step 17-7).

[0258] In step 17-1 or 17-3, if the snapshot Torejisuta queue CBQ ₀ is determined to be empty, the next buffer in place of the queue CBQ ₀ is unloaded at step 17-8, the queue The bit of the snapshot register corresponding to CBQ ₀ is cleared. Similarly, step 17-4 or 17
In -6, snapshot when the snapshot register queue CBQ ₁ is determined to be empty, the next buffer in place of the queue CBQ ₁ in step 17-9 is unload, corresponding to queue CBQ ₁ Register bits are cleared. Then, following either step 17-8 or 17-9, a check is made in step 17-10 to see if the scan enable counter is zero. If the scan enable counter is zero, no service cell transmission request is issued (step 17-7). Otherwise, a service cell transmission request is issued as shown in step 17-11.

11.0 Integrity Checking Integrity checking inherently maintains cell synchronization and prevents defective cells from undergoing further processing or being forwarded. For all the received cells from the switch port board (SPB) 24, the parity check of the first byte and the second byte is performed using the FBP and SBP fields (see FIGS. 4A and 4B). For control cells, the last word parity (LWP) is also checked (see FIG. 4B).

For a service cell to be buffered in the switch core 22, the first byte operation is performed before the cell is stored in the buffer from the viewpoint of changing the value of the PRI field. This change occurs when the cell is a crosspoint unit (X
PU) 32 (see description of PRI swap unit 55-4 and FIG. 5C). As a result of this operation, the cross point unit (XPU
) Before storing in the appropriate one of the 32, a new FPB is determined and added to the serving cell. When a cell is unloaded from the buffer of the cross point unit (XPU) 32, these parities (FBP and SBP) are checked.

Since the second byte changes due to the TTI conversion, a parity bit (SBP field) of the second byte is calculated and added in connection with transmission of all cells.

FIG. 18 is a diagram illustrating the parity check of the service cell. When the service cell is received from the switch port board (SPB) 24, the parity check using the FBP and SBP fields is performed as described above as indicated by S-1. If an error is detected in the service cell, a cell discard process (CDP) is activated (S-2). Step S-3 is a cell analysis unit (CAU) 55 [FIG.
PRI exchange performed and the calculation of a new FBP. Step S
-4 is a cross point unit (XPU) of the memory array unit (MAU) 30
) 32 represents the storage of the service cell in the appropriate one. When the cell is unloaded from the cross point unit (XPU) 32, a check using the FBP and SBP bits is performed (step S-5). If an error is detected, S-
As shown in FIG. 6, the cell discarding process is started. Step S-7 shows the TTI conversion and the calculation of the new SBP, and then the cell is transmitted from the matrix unit (RCU) 40 to the destination switch port board (SPB) 24 (step S-8). The last word parity (LWP) is further added to the control cell.

Tables 8, 9 and 10 show possible error detection checks and actions that can be taken on the receiving and transmitting side of the operational switch core 22 (CDP: cell discard processing, AIP: interrupt insertion) Processing, LSP: link synchronization processing). In particular, Table 8 shows errors and countermeasures for the control cell, and Tables 9 and 10 show errors and countermeasures for the serving cell. Table 9 also shows Table 10 for the first cell in the chained stream.
Is also applied to the subsequent cell and the last cell in the chained stream, respectively.

11.1 LSP: Link Synchronization Processing The LSP defines the processing that must be performed when an error indicates a loss of cell synchronization. The LSP performs the following operations: (1) Exclude ongoing cells from other processing.
(2) Forcing a device in a synchronized state to a pre-synchronization state.

11.2 CDP: Cell Discard Processing CDP involves the handling of both serving and control cells. On the receiving side, the CDP specifies that a receiving cell, which is a serving cell or a control cell, is excluded from other processing. On the transmitting side, the CDP specifies that service cells unloaded from the crosspoint buffer should be discarded and that LSC cells should be inserted instead. The cross point buffer is set to an "empty" state.

For chained cells, the receiving side discards all remaining chained cell streams if the CDP is activated due to exceeding the buffer size. C
If the DP is activated by another error, such as a modified PRI / TTI / CBQ or no service cell in the chained cell stream, the erroneous cell is discarded. The remaining concatenated cells in the stream are considered as new concatenated cell streams (ie, loaded or discarded depending on whether the buffer is available or not).

On the transmitting side, for concatenated cells, the CDP shall indicate that the serving cell unloaded from the crosspoint buffer should be discarded and
Specifies that SC cells are to be inserted. All subsequent chained cells in the buffer are excluded from other processing and the buffer is set to "empty" if loading of "new" cells has not yet started.

11.3 Interrupt Insertion Process The interrupt insertion process (AIP) is a process in which an interrupt signal is inserted into the crosspoint buffer addressed in the specified CBQ in place of the first two bytes of the service cell that starts the process. Stipulates that The interrupt signal is 16 bits long and 16
It is FE1C of the base number. Starts at the first byte.

11.4 Cell Integrity Register Display Error The notation “CIR _x ” means that the error is an error represented by the setting bit bit _x of the cell integrity register. This bit is cleared after reading the register.

[0270] 12. Clock Distribution All ports have two connections for the system clock. One input and one output. The output source is input from any other port. Actual source (
Port number) is programmable, and different sources can be set to different ports. The transmission rate of the cell transmitted from the matrix unit (RCU) 40 is determined by the same clock used for receiving the cell. This clock is supplied by an external unit connected to this port.

The system clock coming in on all ports is distributed to all other RCUs. RC
Inside U there is a semi-static switch. This switch is RC
It is controlled by the system clock register in U. The output of this switch is connected to the port's system clock output. See FIG. The system clock output of all ports is transparent from the system clock input of all ports.

The present invention can be used with the ATM systems disclosed in the following co-filed US patent applications. These U.S. patent applications are also incorporated herein by reference.

US Patent Application No. 08 /, (Attorney Docket No. 2380-24), entitled “Asynchronous Transfer Mode System Handling Different AAL Protocols (ASYNCHRONOUS TRANS
SFER MODE SYSTEM HANDLING DIFFERING AAL PROTOCOLS)

US Patent Application No. 08 /, (Attorney Docket No. 2380-25), entitled “CENTRALIZED QUEUING FOR ATM NODE”

US Patent Application No. 08 /, (Attorney Docket No. 2380-26), entitled “CELL HANDLING UNIT FOR ATM NODE”

US Patent Application No. 08 /, (Attorney Docket No. 2380-27), entitled “ATM TIMESTAMPED QUEUING”

US patent application Ser. No. 08 /, (Attorney Docket No. 2380-28), entitled “Coordinated Cell Discharge from ATM Queue (COORDINATED CELL DISCHARGE FROM ATM Q)
UEUE) ''

US Patent Application No. 08 /, (Attorney Docket No. 2380-30), entitled “COMBINED HEADER PARAMET for ATM Nodes”
ER TABLE FOR ATM NODE) ''

US Patent Application No. 08 /, (Attorney Docket No. 2380-46), entitled “METHOD, ARRANGEMENT, AND APPARATUS FOR TELECOMM
UNICATION)

Although the present invention has been described with reference to the most realistic and preferred embodiments presently conceivable, the present invention should not be limited to the disclosed embodiments, but, on the contrary, of the appended claims. It is to be understood that they are intended to cover various modifications and equivalent arrangements included within the spirit and scope. For example, the present invention provides a switch core 2
2 and the number of matrices in the switch core 22 are not limited. Furthermore, while many aspects of the invention have been described as being implemented by hardware elements, such aspects can alternatively be achieved by software programming techniques.

[0281]

[Table 1]

[0282]

[Table 2]

[0283]

[Table 3]

[0284]

[Table 4]

[0285]

[Table 5]

[0286]

[Table 6]

[0287]

[Table 7]

[0288]

[Table 8]

[0289]

[Table 9]

[0290]

[Table 10]

[Brief description of the drawings]

The foregoing objects, features and advantages of the present invention will become apparent from the foregoing more particular description of the preferred embodiments, as illustrated by the accompanying drawings.
In the accompanying drawings, reference symbols refer to the same components from different perspectives. The drawings need not be adjusted in length, but rather emphasized in that they illustrate the principles of the invention.

FIG. 1 is a diagrammatic representation of an ATM switching system according to an embodiment of the present invention.

FIG. 2 is a diagram schematically illustrating a part of a cross point unit (XPU) included in a switch core of the ATM switching system of FIG. 1;

FIG. 3 shows a switch core and a switch port board of the ATM switching system of FIG.
2 illustrates the flow of cells to and from SPB).

FIG. 4A illustrates a format of a service cell used in the ATM switching system of FIG. 1;

FIG. 4B illustrates a general format of a control cell used in the ATM switching system of FIG. 1;

FIG. 4B-1 illustrates the format of a bitmap formatted Link Connection Control (LCC) cell.

FIG. 4B-2 illustrates the format of a coded link connection control (LCC) cell.

FIG. 4B-3 illustrates a format of a link state control (LSC) cell.

FIG. 5 is a diagrammatic representation of a matrix unit (RCU) included in the ATM switching system of FIG. 1;

FIG. 5A is a diagrammatic representation of a line interface unit (LIU) included in the ATM switching system of FIG. 1;

FIG. 5B is a diagrammatic representation of a cell synchronization unit (CSU) included in the ATM switching system of FIG.

FIG. 5C is a diagrammatic representation of a cell analysis unit (CAU) included in the ATM switching system of FIG. 1;

FIG. 5D is a cell write unit (CWU) included in the ATM switching system of FIG. 1;
Is shown graphically.

FIG. 5E is a diagrammatic representation of an operation management unit (OMU) included in the ATM switching system of FIG. 1;

FIG. 5F is a cell read unit (CRU) included in the ATM switching system of FIG. 1;
Is shown graphically.

FIG. 5G is a diagrammatic representation of a cell generation unit (CGU) included in the ATM switching system of FIG. 1;

5H-1 graphically illustrates different incorporation of the crosspoint status unit of the ATM switching system of FIG. 1;

5H-2 graphically illustrate different incorporation of the crosspoint status unit of the ATM switching system of FIG. 1;

FIG. 5I shows a system clock unit (S) included in the ATM switching system of FIG. 1;
CU) is shown graphically.

FIG. 6 is a diagram schematically illustrating a state where a part of a CSB is connected to elements of a matrix unit (RCUs) in FIG. 1;

FIG. 6A is a diagrammatic representation of a sequence of events as a service cell is carried through the core of the ATM switching system of FIG. 1;

FIG. 6B is a graphical depiction of the sequence of events as a service cell is carried through the core of the ATM switching system of FIG. 1;

FIG. 6C is a graphical depiction of the sequence of events as a service cell is carried through the core of the ATM switching system of FIG. 1;

FIG. 6D is a graphical depiction of the sequence of events as a service cell is carried through the core of the ATM switching system of FIG. 1;

FIG. 6E is a graphical depiction of the sequence of events as a service cell is carried through the core of the ATM switching system of FIG. 1;

FIG. 7 is a flowchart showing basic steps included in an initialization procedure for the ATM switching system of FIG. 1;

FIG. 8 is a diagrammatic representation of a state machine included in a cell synchronization unit (CSU) of the ATM switching system of FIG.

9 illustrates a time transition illustrating the operation of the state machine of FIG.

10A is a diagram schematically illustrating cell transmission in the ATM switching system of FIG. 1. FIG.

FIG. 10B schematically illustrates cell transmission in the ATM switching system of FIG. 1;

FIG. 11 schematically shows the relationship between the polling rate register and the bits in the crosspoint unit.

FIG. 12 schematically illustrates a scenario for setting a polling rate register.

FIG. 13 schematically shows the relationship between bits in the scan rate register and the crosspoint unit.

FIG. 14 schematically illustrates a scenario of setting a scan rate register.

FIG. 15 schematically illustrates a polling option regarding a transmission timing of an instruction indicating a queue changing from “occupied” to “empty”.

FIG. 16 schematically illustrates a scan option with respect to a transmission timing of an instruction indicating a queue that changes from an “empty” state to a “cell available” state.

FIG. 17 is a flowchart showing basic steps in a scanning process.

FIG. 18 schematically illustrates an error check operation for a service cell.

FIG. 19 is a diagram schematically showing a system clock distribution in the ATM switching system of FIG. 1;

────────────────────────────────────────────────── ─── Continued on the front page (31) Priority claim number 09/188, 265 (32) Priority date November 9, 1998 (November 19, 1998) (33) Priority claim country United States (US) ( 81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, SD, SZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, K, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT , UA, UG, UZ, VN, YU, ZW [Summary continued] (1) In response to a particular control cell invoking a polled state cell, or (2) A predetermined number of affected crosspoint units Is generated or transmitted depending on whether there is a change in the presence / absence (for example, “free” / “occupied” status).

Claims (34)

[Claims] 1. A method for operating an ATM switch having a plurality of switch ports connected to a switch core, wherein the switch core has a plurality of crosspoint buffers, (1) in the switch core, Maintaining polling status information indicating which of the selected plurality of crosspoint buffers has a serving cell among the crosspoint buffers of the core; and (2) the source switch port performs the polling. Transmitting a polling state read control cell from the transmission source switch port to the switch core when the confirmation of the status information of the state is desired; and (3) responding to the polling state read control cell, Polling status information And (5) using the polling state status information obtained from the polling state read control cell, among the crosspoint buffers included in the switch core. Determining which of the selected plurality of cross-point buffers is capable of transmitting the service cell including exchangeable user data from the source switch port. Method. (6) transmitting a service cell from the source switch port to a specific crosspoint buffer in the switch core; and (7) relating to the specific crosspoint buffer according to the step (6). Changing the status information of the polling state. 3. The method according to claim 1, further comprising the step of: when the service cell is transmitted in the step (6), setting a scan rate indication for a destination switch port in which the service cell is to be supplied from the specific crosspoint buffer. 3. The method of claim 2, wherein: 4. The method according to claim 1, further comprising the step of: upon reading the service cell of the step (7) from the specific crosspoint buffer, resetting the polling state status information relating to the specific crosspoint buffer. The method according to claim 3, wherein 5. (10) In the switch core, polling indicating which of a plurality of the selected cross point buffers from among the cross point buffers included in the switch core has a service cell read out. Maintaining state release information; detecting a change in the polling state release information for the specific crosspoint buffer; and transmitting the polling state release information to the source switch port in response to the detection. The method of claim 4, further comprising: 6. The method according to claim 5, wherein said polling state release information includes a control cell transmitted to said switch port. 7. maintaining a crosspoint status register at the switchport; setting an indication of the crosspoint status register when the switchport sends a service cell to the particular crosspoint buffer; The method of claim 6, further comprising resetting the display of the crosspoint status register upon receipt of the polling status release information. 8. The method of claim 1, wherein neither the polling state read control cell nor the polling state status control cell contains exchangeable user data. 9. A method for operating an ATM switch having a plurality of switch ports connected to a switch core having a plurality of crosspoint buffer units by a corresponding plurality of corresponding bidirectional links, the plurality of switch ports being provided. Generating a cell stream for supplying the bidirectional link between a selected one of the switch cores and the switch core, wherein the cell stream includes service cells interspersed with control cells, and the control cell Does not include exchangeable user data, the control cell is (1) a polling state read control cell, and (2) which crosspoint buffer unit of the switch core can accommodate a service cell from the selected switch port. A polling status cell indicating whether or not the switch is present; and (3) the switch How which crosspoint buffer unit of the core, characterized in that it comprises a polling state releasing cell which indicates whether the change to the idle state. 10. The polling status cell is transmitted from the switch core to the selected switch port in response to receiving the polling status read control cell at the switch core. 9. The method according to 9. 11. The method according to claim 9, wherein the polling state release cell is generated upon detecting a transition of the crosspoint buffer unit to an empty state. 12. A source switch port and a destination switch port, wherein a first crosspoint buffer set storing service cells received from the source switch port and a second cross point buffer set for obtaining service cells to the destination switch port are provided. A method of operating an ATM switch connected to a switch core having a cross point buffer set, comprising: transmitting a polling state read control cell from the source switch port to the switch core; Transmitting, in response to the reception, a polling status control cell including a status indication of the first crosspoint buffer set from the switch core to the source switch port; Said state According to the display,
Transmitting a service cell for storing in one of the first set of crosspoint buffers from the source switch port to the switch core; one of the first set of crosspoint buffers; Reading the service cell from the to the destination switch port to provide an indication that one of the first crosspoint buffer sets is empty; and one of the first crosspoint buffer sets. Transmitting a polling release control cell from the switch core to the source switch port in response to the idle indication. 13. A scan status register, wherein one of the first set of crosspoint buffers is common to the second set of crosspoint buffers and a scan status register maintained in association with the second set of crosspoint buffers. Setting the transmission of the service cell from the source switch port to one of the first set of crosspoint buffers; and setting one of the first set of crosspoint buffers to The method of claim 12, further comprising resetting the scan status register in response to reading the service cell from one. 14. An ATM having a switch port connected to a switch core.
A method of operating a switch, comprising: transmitting a stream of control cells and service cells between the switch port and the switch core; and a crosspoint in the switch core during a stream from the switch core to the switch port. A polling status control cell for indicating a buffer status, wherein the polling status control cell is (1) a polling status command command cell received from the switch port at the switch core; and (2)
A method comprising being included in the stream in response to any one of the state changes of the crosspoint buffer. 15. An ATM having a switch port connected to a switch core.
A method of operating a switch, comprising transmitting cells in a first direction from the switch port to the switch core and in a second direction from the switch core to the switch port, wherein the second direction The polling status cell including a polling status cell, the polling status cell including a cell presence / absence notation for at least some crosspoint buffers of the switch core; and (1) the polling status status cell. And (2) generating the polling state cell in response to at least one of a reception at the switch core, and (2) a change in presence / absence of a cell for a predetermined number of the crosspoint buffers,
Transmitting. 16. The method according to claim 15, wherein said predetermined number of crosspoint buffers is one. 17. The polling status cell includes a polling status cell having a cell present / absent notation for a crosspoint buffer in a row of the switch core, wherein the polling status cell is associated with the switch associated with the switch port. The method of claim 15, including polling state release cells having a cell-to-no-cell transition notation for a crosspoint buffer in a row of the core. 18. The method according to claim 15, wherein the polling state cell and the serving cell are mixed in the second direction. 19. The method of claim 15, further comprising controlling a relative frequency of said polling cell transmission to said serving cell. 20. The method of claim 15, wherein the polled state cell is essentially dedicated to transmission with and without cells for at least some crosspoint buffers of the switch core. 21. The method of claim 15, wherein said polling state cell has no payload exchangeable via said switch core. 22. The method further comprising generating a synchronization cell and transmitting in the second direction, wherein the transmission of the synchronization cell comprises: (1) receiving at the switch core a cell invoking the synchronization cell; 16. The method of claim 15, wherein the method is performed in response to at least one of the occurrence of an error. 23. The method of claim 15, further comprising transmitting the service cell in the second direction in response to receiving at the switch core a cell inviting a service cell. 24. An ATM having a switch port connected to a switch core.
A switch, wherein both a service cell and a control cell are transmitted on a bidirectional link between the switch port and the switch core, the switch core having a crosspoint buffer, and the switch core having a crosspoint buffer. For at least some of the cells, the presence / absence of a cell is monitored, and the control cell transmitted from the switch port to the switch core includes a polling state read control cell and a service cell request control cell; Transmission of a service cell and a polling status cell to the switch port associated with the reception of one of the service cell request control cell and the polling status read control cell, respectively, and the polling status cell is transmitted to the switch port by the crosspoint buffer. ATM switches and supplying for at least some of the serving cell with / without notation. 25. An ATM switch in which a plurality of different cell exchange relations corresponding to control cell types are established between a switch port and a switch core, wherein in the first cell exchange generation relation, the ATM switch comprises: A service cell transmission from the switch core to the switch port is performed by a first type control cell transmission from a port to the switch core. In a second cell exchange relationship, a second type control cell from the switch port is: An ATM switch for providing a second type control cell to be transmitted to said switch port, wherein said second type control cell includes a cell presence / absence notation in a cross point buffer of said switch port. 26. In a third cell generation relationship, a third type control cell transmitted from the switch port requests transmission of a third type control cell to the switch port, and the third type control cell is The method of claim 25, including the contents of a control register of the switch core. 27. In a fourth cell generation relationship, a fourth format control cell transmitted from the switch port requests transmission of a fourth format control cell to the switch port, and the fourth format control cell is The method of claim 26, including information used for synchronization of one of the switch ports. 28. A method of operating an ATM switch having a plurality of switch ports connected to a switch core having a plurality of crosspoint buffers, comprising: (1) in the switch core, the crosspoint buffer of the switch core; And maintaining polling status information indicating which of the selected plurality of crosspoint buffers has a serving cell; and (2) a specific crosspoint of the switch core from the source switch port. Transmitting a service cell to a buffer; (3) changing the status information of the polling state for the specific crosspoint buffer according to step (6); and (4) starting from the specific crosspoint buffer. 3) Sir Resetting the status information of the polling state for the specific cross point buffer upon reading the cell, (5) in the switch core, a plurality of the cross point buffers selected from the Maintaining polling state release information indicating from which of the crosspoint buffers the service cell has been read; and (6) detecting a change in the polling state release information for the particular crosspoint buffer. And (7) transmitting the polling state release information to the source switch port. 29. The method according to claim 28, wherein said polling state release information includes a control cell transmitted to said switch port. 30. maintaining a crosspoint status register at the switchport; setting an indication of the crosspoint status register when the switchport sends a service cell to the particular crosspoint buffer; The method of claim 28, further comprising resetting the display of the crosspoint status register upon receipt of the polling status release information. 31. The method of claim 28, wherein neither the polling state read control cell nor the polling state status control cell contains exchangeable user data. 32. When the source switch port desires to check the status information of the polling state, transmitting a polling state read control cell from the source switch port to the switch core; and 29. The method of claim 28, further comprising the step of: in response to transmitting the polling status information into a polling status control cell for transmission to the source switch port. 33. Using the status information of the polling state obtained from the polling state read control cell, assigning the selected one of the plurality of cross point buffers among the cross point buffers included in the switch core. 33. The method of claim 32, further comprising determining from the source switch port whether the service cell containing exchangeable user data can be transmitted. 34. The method according to claim 34, further comprising the step of, when transmitting the service cell in the step (3), setting a scan rate indication for a destination switch port in which the service cell is to be supplied from the specific crosspoint buffer. The method according to claim 28, wherein