JPH1098478A - Cell exchange system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a cell from being aborted without provision of a speed adjustment buffer even in the case of connection of a transmission line having only a transmission speed lower than a transmission speed of a switch output line. SOLUTION: When a transmission line speed detection section 5ai detects a transmission speed of a transmission line 4i, a read timing arithmetic section 14 calculates and outputs a read timing or each switch output line 3i at a cycle where cells are not collided with each other on the transmission line 4i based on a transmission speed of the switch output line 3i and a transmission speed of the transmission line 4i. Then a read address control section 15 reads an address from an address queue 11i based on a read timing and cells from a common buffer memory 8 are outputted to the switch output line 3i at a cycle where cells corresponding to the address from the common buffer memory 8 are not collided on the transmission line 4i. As a result, since cell abort is not caused, the speed adjustment buffer having been conventionally to a transmission line connector 5i is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to ATM (Asynchronous Transfer), which is information of a frame structure in which various types of multimedia information such as voice, data and images are blocked, and finite-length data such as fixed-length packets. Mode;
(Asynchronous transfer mode) A cell switching device for inputting a cell of a communication system and outputting the cell via an output line indicated by destination information included in the cell, and connecting the output line and the transmission line to connect the transmission line The present invention relates to a cell switching system for transferring the cell to an external terminal, an external system, an external network, or the like via the external device.

[0002]

2. Description of the Related Art A cell switching system is an ATM (Async
hronus Transfer Mode) A cell switching device for inputting a cell of a communication system and outputting the cell via an output line indicated by destination information included in the cell, and connecting the output line to a transmission line. This is a system in which the cells are transferred to an external terminal or the like via the transmission line. In this system, various kinds of information are communicated by exchanging such cells. In addition, ATM (Asynchronus
Transfer Mode (Asynchronous Transfer Mode)
For example, a continuous signal such as a line signal, voice, text, or moving image is divided into all fixed lengths, and a header indicating destination information and the like is added to the packet to create a packet. Since packets are internationally standardized and are called cells, they are hereinafter referred to as "cells.")
Means a method for transferring information.

FIG. 10 shows a configuration of a conventional cell switching system of the ATM communication system. The cell switching system shown in FIG. 10 is based on the 1993 IEICE Autumn Meeting B-
417, Yoshino, Suzu, Nakayama, Tachibana, Block diagram from network-side received data to terminal-side received data of AAL (ATM Adaptation Layer) processing LSI introduced in "Development of LSI for ATM Adaptation Layer TYPE-1 Processing" Is slightly modified. Note that the names of the network-side reception data lines are changed to switch output lines, AALLSI is changed to transmission line connection devices, terminal-side reception data lines are changed to transmission lines, and external buffers for reception are changed to speed adjustment buffers. .

More specifically, in this conventional cell switching system, as shown in FIG. 10, cells are switched via a switch input line 2i (i is an arbitrary natural number from 1 to m; the same applies hereinafter). For example, the cell switching device 100 that inputs and outputs via the switch output line 3i indicated by the destination information of the cell, and each switch output line 3i and a transmission line 4i for transmitting data to an external terminal or the like are connected to each other, for example. To prevent cell collision and discard in the transmission line connection device 101i when the transmission line connection device 101i performing AAL type 1 service or the like is connected to a transmission line having a transmission speed lower than the transmission speed of the switch output line. Each transmission line connection device 101i
And a speed adjusting buffer 102i provided for each. The specific configuration of the cell switching device 100 is described in, for example, the document IEEE GLOBAL TELECOMMUNICATIONS C.
ONFERENCE 1993, Session 40, Paper number 7, H. Yamanaka,
H.Saito, H.Yamada, M.Tsuzuki, S.Kohama, H.Ueda, H.Kondo
h, Y.Matsuda, K.Oshima, “622Mb / s8x8Shared Multibuff
er ATM switch with Hierachical Queuing and Multic
ast Functions ”describes a common buffer type.

FIG. 11 shows the timing of cells to be input / output in the conventional cell switching apparatus 100 shown in FIG. In FIG. 11, (a), (b), (c), (d)
Indicates the input timing of cells to each of the switch input lines 21, 22, 23, and 24, (e) indicates the output timing of cells from the cell switching device 100 to the switch output line 31, and (f) indicates the transmission line. 41 shows the output timing of the cell to 41. Here, this timing is represented by a time required for the switch output line 31 to transfer one cell as a time slot, which is a unit time, and a time by this time slot is indicated by t. Also, the switch input line 21,
It is assumed that all cells input from 22, 23, and 24 are destined for the switch output line 31, and the transmission speed of the switch output line 31 is V, the transmission speed of the transmission line 41 is V / 3, The transfer delay time of the cell from 100 to the transmission line connection device 1011 is assumed to be zero time slot.

Therefore, the switch output line 31 is
As shown in 1 (e), cells 1, 2 and 3 are output continuously for each time slot. On the other hand, the transmission speed of the transmission line 41 is V / 3, which is 1/3 times the transmission speed V of the switch output line 31, so that one cell is transferred on the transmission line 41 as shown in FIG. This would require three time slots. Therefore, in order to bridge the difference between the state shown in (e) and the state shown in (f), the speed adjustment buffer 102 of the transmission line connection device 1011 is used.
At 1, the cells 1 to 3 are held for a certain period of time.

FIG. 12 shows a cell holding state of the speed adjusting buffer 1021 at time t in the cell input / output state shown in FIG. Specifically, as shown in FIG. 11E, the cells 1, 2, 3 are output from the cell switching apparatus 100 at times t = 2, 3, 4, respectively, so that the speed / speed adjustment buffer 1021 is output. Are cells 1 and 2 at the timings of time t = 2, 3 and 4 as shown in FIG.
2 and 3 are inputted and held. On the other hand, the transmission speed of the transmission line 41 is V / 3, and it takes three time slots to transfer one cell. Therefore, the speed / speed adjustment buffer 1021 transfers the cell 1 via the transmission line 41.
The cell 1 is held at the time t = 2, and is further held from the time t = 3 to the time t = 3 to 5 until the transfer to the transmission line 41 is completed at the time t = 5 for the first time. On the other hand, for the cell 2, it is necessary to wait for the transfer of the cell 1 to be completed, and it takes time to transfer three time slots from that point. It will hold t = 4-8. Cell 3 is the same as cell 2.

[0008]

However, in the conventional cell switching system, when a transmission line having a transmission speed lower than the transmission speed of the switch output line is connected as described above, the transmission line connection device and the transmission line are not connected. In order to prevent cell collision and discard in the above, a speed adjusting buffer is provided for each transmission line connection device, so that the cost is increased by the amount of the speed adjusting buffer and the speed adjusting buffer holds cells. There is a problem that a cell transfer delay occurs.

Accordingly, the present invention has been made in view of such a problem, and even when a transmission line having a transmission speed lower than the transmission speed of the switch output line is connected,
It is an object of the present invention to provide a cell switching system that can prevent cell collision and discard without newly providing a speed adjustment buffer, and can prevent a delay in cell transfer by the speed adjustment buffer.

[0010]

According to the present invention, there is provided a cell switching apparatus for inputting a cell and outputting the cell via an output line indicated by destination information contained in the cell. In a cell switching system in which a line is connected to a transmission line and the cell is transferred to the outside via the transmission line, the cell input according to the address is stored, and the address is specified by the address. A cell storage unit for outputting a cell, a destination output line detection unit for detecting an output line to output the cell based on the destination information of the input cell, and an output line detected by the destination output line detection unit. Address storage means for storing, for each output line, the address of the cell output to the output line in the cell storage means, and the transmission speed of each output line. Based on the transmission speed of each transmission line, a read timing for reading the address from the address storage means is calculated for each of the output lines so as to prevent a cell collision on each of the transmission lines, and output. Reading the address from the address storage means for each of the output lines based on the read timing output from the read timing effect means, and designating the read address to the cell storage means And read address control means. The cell storage means includes a buffer memory such as a RAM.

Further, in the following invention, transmission line speed detecting means for detecting the transmission speed of each transmission line is further provided for each transmission line, and the read timing effecting means previously stores the transmission speed of each output line. Output line speed storage means, and transmission line transmission provided for each of the output lines, wherein the transmission line speed detection means detects the transmission speed of each output line stored in advance in the output line speed storage means. Read timing calculating means for dividing the quotient by the speed and outputting the quotient as the read timing for each of the output lines; and a read timing calculating means provided for each of the read timing calculating means. Counting is performed one by one for each required cell transmission time, and when the count value becomes equal to the read timing for each output line calculated by the read timing calculation means, a corresponding operation is performed. And a read timing output counter which outputs the read timing signal for instructing the output of the cell to the force lines, is composed of a read address control means,
The address is read from the address storage means for each output line in response to the input of the read timing signal output from the read timing output counter, and the read address is specified to the cell storage means.

Further, in the following invention, transmission line speed detecting means for detecting the transmission speed of each transmission line is further provided for each transmission line, and the read timing effecting means previously stores the transmission speed of each output line. An output line speed storage unit, a plurality of input terminals corresponding to the transmission line speed detection unit, and one output terminal, wherein the plurality of input terminals are selected one by one, and the transmission is performed via the selected input terminal. An input selector for inputting the transmission speed of the transmission line detected by the linear speed detecting means and switching the transmission speed to be output one by one via the one output terminal; A read timing operation for dividing the transmission speed of each output line thus obtained by the transmission speed of the transmission line output one by one for each transmission line from the input selector and outputting the quotient as the read timing for each output line. Means, having one input terminal and a plurality of output terminals corresponding to the plurality of input terminals of the input selector, and inputting a read timing output from the read timing calculating means through the one input terminal; An output selector that selects the plurality of output terminals one by one in synchronization with a selection process of the plurality of input terminals of the input selector and outputs read timing via the selected output terminals; Each output line is provided corresponding to each output terminal, and each output line counts by one for each cell transmission time required for transmitting one cell, and the count value is calculated by the read timing calculation means. When the read timings become equal to each other, a read timing signal for outputting a read timing signal instructing output of a cell to a corresponding output line is output. A read address control means for reading the address from the address storage means for each of the output lines in response to the input of the read timing signal output from the read timing output counter, and reading the read address. To the cell storage means.

Further, in the following invention, the transmission line speed detecting means further detects a new transmission speed each time the transmission speed of each transmission line changes, and the read timing calculating means further detects the transmission line speed detecting means. Each time a new transmission speed of each transmission line is transmitted, a new read timing is calculated, and the read timing output counter further counts a counter value each time a new read timing is transmitted from the read timing calculation means. Is cleared to 0, and thereafter, each output line counts one by one for each cell transmission time required for transmitting one cell, and the count value becomes equal to the new read timing calculated by the read timing calculation means. In this case, a read timing signal for instructing output of a cell to a corresponding output line is output.

Further, in the following invention, the cell storage means, the destination output line detection means, the address storage means, the read timing effecting means and the read address control means are provided in the cell exchange, while the transmission line speed detection means is provided. , Are provided in the transmission line connection device for each output line connecting the output line and the transmission line.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. First, a cell switching system according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration of a first embodiment of a cell switching system according to the present invention. In FIG. 1, reference numeral 1 denotes a common buffer type cell switching device using a common buffer memory described later, and 2i (i is an arbitrary natural number from 1 to m) denotes a cell input to the system to the cell switching device 1. A switch input line for transferring, 3i is a switch output line for outputting a cell from the cell switching device 1, 4i is a transmission line, 5i
Is a transmission line connection device for connecting each switch output line 3i and each transmission line 4i, and has a transmission line speed detection unit 5ai for detecting the transmission speed of each transmission line 4i connected to itself.

In the cell switching apparatus 1, reference numeral 6i is provided corresponding to each of the switch input lines 2i, and a switch output line 3i serving as a destination of the cell is determined based on destination information of a header portion of the cell input from the switch input line 2i. A header processing circuit functioning as a destination output line detecting means for detecting, a cell multiplexing circuit for multiplexing and outputting cells input from a plurality of switch input lines, and a cell storing a cell at a specified address; , A common buffer memory as a cell storage means capable of reading cells irrespective of the storage order, and a cell 9 read out from the common buffer memory 8 is separated into a plurality of switch output lines 3i and output. Cell separation circuit 10, address queue unit group 1
1, a control unit including a free address pool unit 12, a write address control unit 13, a read timing effect unit 14, and a read address control unit 15.

The address queue section group 11 is a FIFO (First I / O) functioning as an address storage means provided for each switch output line 3i as a cell destination.
n First Out) It is composed of a plurality of address queue units 11i such as memories.

The free address pool section 12 stores unused free addresses among the addresses in the common buffer memory 8.

The write address control unit 13 reads a free address in the common buffer memory 8 from the free address pool unit 13 and, based on the detection output of the header processing circuit 6i, uses the free address as a switch output line 3i as a destination of an input cell. Is stored in the address queue 11i corresponding to the header processing circuit 6i.
And the cell input through the cell multiplexing circuit 7 is controlled to be written into the common buffer memory 8.

The read timing effector 14 functions as a read timing effector, and will be described later when the transmission speed of each transmission line 4i is sent from the transmission line speed detector 5ai of each transmission line connection device 5i. In this way, the read timing for each address queue 11i corresponding to each switch output line 3i is calculated and output to the read address control unit 15 as a read timing signal.

The read address control section 15 functions as a read address control section. Based on a read timing signal for each address queue section 11i from the read timing directing section 14, a read address control section 15 transmits a cell from the corresponding address queue section 11i to the cell. And reads out the cell from the common buffer memory 8 based on the address, outputs the cell to the corresponding switch output line 3i via the cell separating circuit 6, and vacates the address released by reading the cell. The address is notified to the free address pool unit 12 as an address.

FIG. 2 shows the configuration of the read timing effect section 14 in detail. The read address rendering unit 14 includes a switch output line speed storage unit 141 in which the transmission speed of each switch output line 3i is stored in advance, and a read timing calculation circuit provided for each switch output line 3i and each transmission line 4i. Read timing operation circuit group 1 comprising 142i
42, similarly, each switch output line 3i and each transmission line 4
read timing output counter group 1 including read timing output counters 143i provided corresponding to each of i
43. In the first embodiment, the transmission speed of each switch output line 3i is common, and the switch output line speed storage unit 141 stores the switch output line 3i.
It is assumed that a common transmission speed is stored, but when the transmission speed of each switch output line 3i is different, the switch output line speed storage unit 141 stores the transmission speed for each switch output line 3i. I do.

Next, the operation of the first embodiment will be described.
This will be described with reference to the drawings.

First, when a cell is input to the cell switching device 1 via the switch input line 2i, the header processing circuit 6i detects the switch output line 3i which is the destination of the cell from the destination information of the header of the cell, and The destination switch output line 3i is notified to the write address control unit 13. This input cell is input to the cell multiplexing circuit 7 via the header processing circuit 6i.

The write address control unit 13 reads a free address in the common buffer memory 8 from the free address pool unit 13 and stores the read free address in the header processing circuit 6i.
Is stored in the address queue 11i corresponding to the detected destination switch output line 3i, and the input cell in the cell multiplexing circuit 7 is written into the common buffer memory 8 based on the vacant address.

On the other hand, the read address control unit 15 receives the address queue unit 11 from the read timing effect unit 14.
Each time the read timing signal is input, the cell storage address is read from the corresponding address queue section 11i based on the read timing signal for each i, and the cell is read from the common buffer memory 8 based on the address. The data is output to the corresponding switch output line 3i via the cell separation circuit 6, and the address released by reading the cell is notified to the free address pool unit 12 as a free address.

Next, the read timing signal effect processing in the read timing effect section 14 and the like will be described in detail with reference to the drawings.

FIG. 3 is a flowchart showing the operation of the read timing effecting section 14 in the arithmetic processing. Here, V1 is the transmission speed of each switch output line 3i, and V2i is the transmission speed of each transmission line 4i.

First, in the read timing rendering section 14, each of the read timing calculation circuits 142i of the read timing calculation circuit group 142 transmits the transmission line 4i from the transmission line speed detection section 5ai of the corresponding transmission line connection device 5i.
Waiting for the transmission speed V2i (step S1).
00), when each transmission line speed detector 5ai transmits the transmission speed V2i of the transmission line 4i (step S10).
0 “YES”), corresponding read timing operation circuit 1
42i receives the transmission speed V2i, and changes the transmission speed V1 of each switch output line 3i to the transmission speed V of the transmission line 4i.
2i to obtain the quotient Vmaxi (step S
110).

Next, the quotient Vmaxi is transferred to the corresponding read timing output counter 143i as the read timing cycle (step S120), and the process returns to step 100 again to return to each transmission line speed detector 5a.
When the transmission speed V2i of the transmission line 4i is transmitted from i, the same processing as described above is repeated.

When the transmission speed of each transmission line 4i does not change, each transmission line speed detection unit 5ai corresponds only to the case where each switch output line 3i and each transmission line 4i are connected first. It is sufficient to detect the transmission speed of the transmission line 4i and transmit it to the read timing operation circuit 142i. However, it can be used depending on, for example, the type of external terminal (not shown) connected to the transmission line 4i and its control. If there is a possibility that the transmission speed of the transmission line 4i may change, the transmission speed of the transmission line 4i is detected and read out every time the transmission speed changes or at a predetermined cycle, assuming that the transmission speed changes. The data is transmitted to the timing calculation circuit 142i so that it can cope with a change in the transmission speed. If the quotient Vmaxi does not become an integer, the quotient Vmaxi is rounded up to an integer. Further, since the transmission speed V1 of each switch output line 3i is generally faster than the transmission speed V2i of the transmission line 4i, the quotient Vmaxi
Is not less than 1, but the transmission speed V of the transmission line 4i
When 2i is faster than the transmission speed V1 of each switch output line 3i and the quotient Vmaxi is less than 1, the read timing is set to 1 and transferred to the corresponding read timing output counter 143i, The cells are read continuously.

FIG. 4 shows a read timing output counter 1
A read timing signal output process in 43i is shown by a flowchart.

First, each read timing output counter 1
43i, the corresponding read timing operation circuit 142
i, the read timing cycle Vmaxi is transmitted, and when the read timing cycle Vmaxi is received (step 200 "YES"), the counter value is subsequently cleared to 0, that is, cleared (step 210). The value is the read timing cycle Vmaxi
It is determined whether or not they match (step 220).

If the read timing cycle Vmax is not equal to the counter value (step 220 "N
O "), the value of the read timing signal is turned off (step 230), and thereafter, it is determined whether or not one cell slot, that is, the time required for each switch output line 3i to transfer one cell has elapsed (step 230). (Step 240) If one cell slot has elapsed (Step 240 “YE
S "), the counter value is incremented by +1 (step 250), and the process returns to step 220 again, where the value of the counter is set to the read timing cycle Vmaxi.
It is determined whether or not they match.

On the other hand, the read timing cycle Vmaxi
Is determined to be equal to the counter value (step 220 "YES"), the counter value is first cleared to 0 (step 260), the value of the read timing signal is turned on, and the read timing output A read timing signal for instructing address read to address queue 11i corresponding to counter 143i is output to read address control unit 15 (step 270).

Thereafter, the value of the read timing signal becomes O
As in the case where the read timing signal is not output by the FF, after one cell slot time has elapsed (step 240 “YE
S "), the counter value is incremented by +1 (step 250), and the process returns to step 220 again, where the value of the counter is set to the read timing cycle Vmaxi.
Is determined, and the above series of processing is repeated.

As described above, the count value of the read timing output counter 143i is incremented by +1 every time one cell slot elapses, and when the count value matches the read timing cycle Vmaxi, the read timing signal Is turned ON, and a read timing signal instructing the address read to the address queue 11i corresponding to the read timing output counter 143i is output to the read address control unit 15.

FIG. 5 is a flowchart showing the operation procedure of the read address control unit 15. Specifically, when the value of the read timing signal from read timing output counter 143i is turned “ON” (step 300 “YES”), read address control section 143i has transmitted the read timing signal. Is read out from the head of the address queue unit 11i corresponding to the address and sent to the common buffer memory 8 (step 310), and the process returns to step 300 to repeat the above processing. .

Therefore, a cell corresponding to the address sent from the read address control unit 15 is read from the common buffer memory 8, and the cell is output to the corresponding switch output line 3i via the cell separation circuit 9. Will be.

Next, the transmission speed V1 of the switch output line 3i
The relationship between the value of the read timing output counter 143i and the read operation by the read address control unit 15 when the transmission speed V2 of the transmission line 4i is specified will be described.

FIG. 6 shows the transmission speed V of the switch output line 3i.
Time when the cell slot is a unit time when 1 = 2V and transmission speed V2 = 1V of the transmission line 4i, the value of the read timing output counter 143i, the value of the read timing signal, and the switch output line 3i by the read address control unit This shows the state of address reading of the service address queue 11i.

The transmission speed V2 of the transmission line 4i = 1V
Is detected by the transmission line speed detector 5ai and notified to the read timing calculation circuit 142i. The read timing calculation circuit 142i calculates V1 / V2 according to the algorithm shown in FIG.
Is calculated. Thereafter, the read timing Vmax = 2
Is transferred to the read timing output counter 143i.

Therefore, in the read timing output counter 143i, the algorithm shown in FIG. 4 is performed with the read timing Vmax = 2, so that the value of the read timing output counter 4i is set to one cell slot as shown in FIG. Each time, "0" and "1" are set alternately, and FIG.
As shown in (b), the read timing signal is alternately switched between "ON" and "OFF" for each cell slot and transferred. That is, at time t = 0, the value of the read timing output counter 143i is set to "0" as an initial value, and therefore, the value of step 22 shown in FIG.
“NO” due to comparison processing of equality judgment with Vmax = 2 of 0
And the value of the read timing signal becomes "OFF" as shown in FIG. Next, at time t = 1,
The value of the read timing output counter 143i is counted up by +1 and becomes "1". However, since the comparison of the equality determination with Vmax = 2 results in "NO", the value of the read timing signal is also "OFF". is there. And time
When t = 2, the read timing output counter 143
The value of i is again counted up by +1 and becomes “2”, so that “YES” is determined by comparing the equality determination with Vmax = 2.
And the value of the read timing signal becomes “ON”.
At the same time, the read timing output counter 143
The value of i is reset to "0", and the above processing is repeated again.

Then, in the read address control unit 15,
Since the processing shown in FIG. 5 is performed, based on the input of "ON" of the read timing signal shown in FIG. 6B from the read timing output counter 143i, the corresponding switch output as shown in FIG. The address is read from the address queue 11i for the line 3i. That is,
The address is read from the address queue unit 11i for the switch output line 3i corresponding to the two cell slots once.

Accordingly, as shown in FIGS. 6A to 6C, the value of the read timing output counter 143i, the value of the read timing signal "ON" or "OFF", and the address wait for the switch output line 3i. The state of the operation of reading the address from the matrix 11i is a repetition having a cycle of a continuous state of two cell slots at time t = 1, 2.

FIG. 7 shows a state of address reading from the address queue section 11i for the switch output line 3i in the case of FIG. As shown in FIG. 7, assuming that addresses A0, A1, A2, and A3 are stored from the beginning in the address queue 11i for the switch output line 3i, the address queue 11i performs reading and writing in a FIFO format. Therefore, the address A0 is read at time t = 2, the address A1 is read at time t = 4, the address A2 is read at time t = 6, and the address A3 is read at time t = 8 by the read address control unit 15. It will be read.

As described above, when the read address control unit 15 reads an address from each address queue unit 11i every other cell slot, that is, once every two cell slots, the address is shared as shown in FIG. The cell sent to the buffer memory 8 and stored at the corresponding address in the common memory 8 is similarly read once every two cell slots, and the switch output line corresponding to the address queue section 11i via the cell separation circuit 9. 3i, the cell at the address is similarly output once every two cell slots.

By the way, the transmission speed V2 of the transmission line 4i = 1
V is 1 from the transmission speed V1 = 2V of the switch output line 3i.
/ 2 times slower. Therefore, for example, as shown in FIG.
= 2, the cell corresponding to the address A0 is output from the common buffer memory 8 via the cell separation circuit 9 to the corresponding switch output line 3i and the transmission line 4i connected to the switch output line 3i. On 4i, it takes two cell slots to complete the transfer, that is, until time t = 3. However, at this time t = 3, FIG.
7, no cell is output on the switch output line 3i, and at time t = 4 when the transfer of the cell corresponding to this address A0 ends on the transmission line 4i, the cell corresponding to the next address A1. Is output, so that cell collision in the transmission line connection device 5i can be prevented.

Therefore, according to the cell switching system of the first embodiment, each switch output line 3i is determined based on the transmission speed of the switch output line 3i and the transmission speed of each transmission line 4i.
The read timing of each address queue unit 11i is determined so that the cell does not collide or be discarded every time. Based on the read timing, the cell corresponding to the read address is output from the common buffer memory 8 to the switch output line 3i. Therefore, cells are not transferred redundantly on each transmission line 4i, and collision and discard of cells in the transmission path 4i and the transmission line connection device 5i can be prevented.

For this reason, according to the cell switching system of the first embodiment, it is assumed that a transmission line having a transmission speed lower than that of the switch output line is connected, and the switch output line and the transmission line are connected. In order to prevent cell collision and discard in the transmission line connection device that connects the line, the speed adjustment buffer provided for each transmission line connection device is not required, so that it is possible to prevent an increase in cost. In addition, it is possible to prevent cell transfer delay in the speed adjustment buffer. Here, the point that the cell transfer delay can be prevented will be described in comparison with the prior art. According to the first embodiment, the speed adjustment puffer 102i provided for each transmission line connection device 101i shown in FIG. It is no longer needed,
The one cell slot of the minimum cell waiting time in the speed adjustment puffer 102i corresponding to (e) to (f) shown in FIG. 11 becomes unnecessary. That is, as shown in FIG. 11E, the cell 1 output on the switch output line 3i at t = 2 is the speed adjustment buffer 1 in the case of the first embodiment.
02i, the transfer to the transmission line 4i is started at the same time, that is, at t = 2, unlike the prior art, so that the speed adjusting buffer shown in FIG. The transfer delay of one cell slot due to 102i is eliminated.

In the first embodiment, the transmission line connecting device 5 for connecting each switch output line 3i to each transmission line 4i.
Although the transmission line speed detector 5ai for detecting the transmission speed of each transmission line 4i is provided for i, the present invention is not limited to this configuration. That is, for example, each transmission line 4i
Is known on the side of the read timing directing unit 15 of the cell switching device 1, but if the transmission line connected to each switch output line is not known, the transmission line connection device 5i sets the transmission line connected to A detection unit for detecting an identification number and a type number for identification and identification, and furthermore, an identification code and the like is provided. The detection unit sends the detection unit to the read timing rendering unit 15, and each transmission is performed based on the identification number and the like. The transmission speed of the line 4i may be obtained, and the read timing of each address queue 11i may be calculated.

In the first embodiment, when the read timing calculation circuit 142i calculates the read timing, the read timing is calculated based on the transmission speed of the switch output line 3i and the transmission line 4i. If cells are always transmitted at the maximum transmission rate on the output line 3i and the transmission line 4i, the read timing may be calculated based on those maximum transmission rates.

Embodiment 2 Next, a second embodiment of the cell switching system according to the present invention will be described.

The cell switching system according to the second embodiment is basically configured to operate in the same manner as in the first embodiment. However, in the first embodiment, each of the address queuing units 11 i A read timing operation circuit group 142 including a corresponding read timing operation circuit 142i is provided. In the second embodiment, the read timing operation circuit group 142 is replaced with a read timing operation circuit group having only one read timing operation circuit. It is characterized in that the arithmetic unit can calculate the read timing of each address queue unit 11i. Therefore, the configuration other than the read timing calculation unit is the same as the configuration of the first embodiment shown in FIGS. 1 and 2, and therefore the second embodiment will be described focusing on the configuration and operation of the read timing calculation unit. Shall be explained.

FIG. 8 shows a configuration of a read timing operation unit which is a characteristic part of the second embodiment. As shown in FIG. 8, the read timing calculator 144 according to the second embodiment includes a transmission line speed detector 5a corresponding to each input terminal.
i, an input selector 144a for inputting the transmission speed of each transmission line 4i, sequentially selecting one of the transmission speeds, and selectively outputting the output from one output terminal;
A read timing arithmetic circuit for sequentially calculating the read timing of each address queue 11i based on the transmission speed of each transmission line 4i from the transmission line 4a and the transmission speed of the switch output line 3i stored in the switch output linear speed storage unit 141 in advance. 144b, and an output selector 144c that sequentially and selectively outputs the read timing output from the read timing operation circuit 144b to the corresponding read timing output counter 143i.

Next, the second embodiment configured as described above
The operation of the read timing calculator 144 will be described with reference to the drawings.

FIG. 9 shows the output of the input selector 144a,
The correspondence relationship with the output of the output selector 144c is shown. Specifically, the input selector 144a inputs the transmission speed of each transmission line 4i from each transmission line speed detection unit 5ai, and sets the transmission speed of each transmission line 4i to a timing T + 1 as shown in FIG. , And sequentially switched for each cell slot to output the data to the read timing calculation circuit 144b one by one. Therefore, the input selector 144a sets the time T + 1
Output the transmission speed of the transmission line 41 at time T + m + 1
In this case, the transmission speed of the transmission line 41 is output again.

Then, the read timing operation circuit 144
b, the transmission line 4 input from the input selector 144a as shown in FIG.
i based on the transmission speed of the switch output line 3i stored in the switch output line speed storage unit 141 and the switch output line 3i connected to the transmission line 4i of the transmission speed input from the input selector 144a. , And outputs the result to the output selector 144c.

The output selector 144c outputs the read timing input from the read timing operation circuit 144b to the corresponding read timing output counter 143i in synchronization with the output of the input selector 144a as shown in FIG. 9B. Will be. That is, the respective read timings are output to the read timing output counters 1431, 1432, and 1433 from the time T + 1 every cell slot.

After that, the operation is the same as in the first embodiment, and the read timing output counter 143i
Performs the processing shown in FIG.
The read address for each address queue unit 11i is output to the address buffer unit 11i, and the read address control unit 15 reads the address of the common buffer memory 8 from each address queue unit 11i based on the read timing, and stores the cell of the address in the common buffer. The data is output from the memory 8 to the corresponding switch output line 3i.

Therefore, according to the second embodiment, since only the configuration of the read timing operation unit 144 is different, and the other configuration is the same as that of the first embodiment, it is duplicated on each transmission line 4i. Cells are no longer transferred,
Cell collision and discard in the transmission line 4i and the transmission line connection device 5i can be prevented. As a result, similarly to the first embodiment, a transmission line having a transmission speed lower than the transmission speed of the conventional switch output line can be used. Assuming the case of connection, the speed adjustment buffer provided for each transmission line connection device to prevent cell collision and discard in the transmission line connection device connecting the switch output line and the transmission line becomes unnecessary, It is possible to prevent an increase in cost and to prevent a delay in cell transfer in the speed adjustment buffer.

Further, in the second embodiment, read timing calculation section 144 is provided with input selector 144a and output selector 144c, so that only one read timing calculation circuit 144b is required. When the number of 3i is large, the number of read timing operation circuits can be reduced, and the cost can be further reduced.

[0064]

As described above, according to the cell switching system of the present invention, the timing of reading an address from the address storage means can be obtained based on the transmission speed of the switch output line and the transmission speed of the transmission line. The cell corresponding to the address is output from the cell storage means to the switch output line at a timing such that the cell does not collide on the transmission line based on the readout timing. Transfer is not performed, and cell collision on the transmission line and discarding of cells at the connection point between the output line and the transmission line can be prevented.

Therefore, according to the cell switching system of the present invention, it is assumed that a transmission line having a transmission speed lower than that of the switch output line is connected.
In order to prevent cell collision and discard in the transmission line connection device that connects the switch output line and the transmission line, the speed adjustment buffer provided for each transmission line connection device becomes unnecessary, thereby preventing an increase in cost. This makes it possible to prevent a delay in cell transfer in the speed adjustment buffer.

In the next invention, the transmission speed of each transmission line is detected for each transmission line, and the address is read out based on the detected transmission speed of the transmission line and the transmission speed of the switch output line. Since the timing is obtained, and the cell corresponding to the address is output from the cell storage means to the switch output line at a timing such that the cell does not collide on the transmission line based on the readout timing,
This eliminates the need for a speed adjustment buffer provided for each transmission line connection device, thereby preventing an increase in cost and for calculating and setting the read timing of the cell storage address for each transmission line. Become.

Further, in the following invention, the input timing and the output selector are provided in the read timing effect means, so that only one read timing operation circuit is required, and in particular, the number of switch output lines is large. In this case, the number of read timing operation circuits can be reduced,
It is possible to further reduce costs.

Further, in the next invention, each time the transmission speed of the transmission line changes, the transmission speed is detected, and the read timing is calculated based on the transmission speed of the transmission line and the transmission speed of the switch output line. Since the read timing signal is output each time the read timing is calculated, a new read timing signal can be output each time the transmission speed of the transmission line changes, and the transmission to be connected to each switch output line can be performed. Even if the transmission speed of the line changes on the way, it is possible to respond quickly and easily.

In the following invention, the transmission line speed detecting means of the present invention is provided in a transmission line connection device for each switch output line connecting the switch output line and the transmission line. Since the components other than the transmission rate detecting means are provided in the cell switching device, the main components constituting the present system can be provided in the cell switching device, and maintenance such as maintenance and inspection of the system can be performed. It will be easier.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a cell switching system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing in detail the configuration of a read timing rendering section 14 together with an address queue section group 11 and a read address control section 15;

FIG. 3 is a flowchart showing a calculation processing operation in a read timing rendering section 14;

FIG. 4 is a flowchart showing a read timing signal output process in a read timing output counter 143i.

FIG. 5 is a flowchart showing an operation procedure of a read address control unit 15;

FIG. 6 shows the transmission speed V1 = 2V of the switch output line 3i,
A read timing output counter 143i for a time change when the transmission speed V2 of the transmission line 4i is 1V.
It is a figure which shows the value of etc.

FIG. 7 is a diagram showing a state of address reading from the address queue unit 11i for the switch output line 3i in the case of FIG. 6;

FIG. 8 is a diagram showing a configuration of a read timing calculation unit which is a characteristic part of the second embodiment.

FIG. 9 shows an input selector 144a according to the second embodiment.
FIG. 14 is a diagram showing a correspondence relationship between an output of an output selector and an output of an output selector 144c.

FIG. 10 is a diagram showing a configuration of a conventional cell switching system.

11 is a diagram showing timings of cells to be input / output and the like in the conventional cell switching apparatus 100 shown in FIG.

12 is a diagram showing a cell holding state of the speed adjustment buffer 1021 at time t in the cell input / output state shown in FIG. 11;

[Explanation of symbols]

Reference Signs List 1 cell switching device, 2i (i = 1 to m) switch input line, 3i switch output line, 4i transmission line, 5i transmission line connection device, 5ai transmission line speed detection unit, 6i header processing circuit (destination output line detection means) , 7 cell multiplexing circuit, 8 common buffer memory (cell storage means), 9 cell separation circuit, 10 control section, 11 address queue section group, 11
i address queue section (address storage means), 12
Free address pool unit, 13 write address control unit,
14 readout timing effector (readout effector), 141 switch output linear velocity storage (output linear velocity storage), 142 readout timing operation circuit group,
142i read timing calculation circuit (read timing calculation means), 143 read timing output counter group, 143i read timing output counter, 15
Read address control unit (read address control means).

Claims (5)

[Claims] 1. A cell switching device for inputting a cell and outputting the cell via an output line indicated by destination information contained in the cell, connecting the output line and a transmission line, and In the cell switching system in which the cells are transferred to the outside, the cells input according to the address are stored, and
Cell storage means for outputting a cell corresponding to the address by designating the address; destination output line detection means for detecting an output line to output the cell based on the destination information of the input cell; Address storage means for storing, for each of the output lines, an address in the cell storage means of a cell output to the output line based on the output line detected by the detection means; Based on the transmission speed of each transmission line, a read timing at the time of reading the address from the address storage means is calculated and output for each of the output lines so that no cell collision occurs on each of the transmission lines. Read timing effecting means; and the address writing for each output line based on the read timing output from the read timing effecting means. Read address control means for reading the address from the storage means and designating the read address to the cell storage means. 2. A transmission line speed detecting means for detecting the transmission speed of each transmission line for each transmission line, wherein the read timing effecting means comprises an output line speed storage means for storing the transmission speed of each output line in advance. Is provided corresponding to each output line, dividing the transmission speed of each output line stored in advance in the output line speed storage means by the transmission speed of the transmission line detected by the transmission line speed detection means. Read timing calculation means for outputting the quotient as read timing for each output line; and read timing calculation means provided for each of the read timing calculation means;
When each output line counts by one for each cell transmission time required for transmitting one cell, and the count value becomes equal to the read timing of each output line calculated by the read timing calculation means. A read timing output counter for outputting a read timing signal for instructing the output of a cell to a corresponding output line, wherein the read address control means outputs the read timing signal output from the read timing output counter. 2. The cell switching system according to claim 1, wherein the address is read from the address storage means for each of the output lines, and the read address is specified to the cell storage means. 3. A transmission line speed detecting means for detecting a transmission speed of each transmission line for each transmission line, wherein the read timing effecting means comprises an output line speed storage means for storing the transmission speed of each output line in advance. And a plurality of input terminals and one output terminal corresponding to the transmission line speed detection means, wherein the plurality of input terminals are selected one by one, and the transmission line speed detection means is connected via the selected input terminal. An input selector for inputting the detected transmission speed of the transmission line and switching the transmission speed to be output one by one via the one output end; and each output line stored in the output linear speed storage means in advance. Read timing calculating means for dividing the transmission speed of the input selector by the transmission speed of the transmission line output one by one for each transmission line from the input selector and outputting the quotient as the read timing for each output line; A plurality of output terminals corresponding to a plurality of input terminals of the input selector; a plurality of output terminals corresponding to a plurality of input terminals of the input selector; An output selector for selecting one of the plurality of output terminals one by one in synchronization with the input terminal selection process and outputting a read timing via the selected output terminal; and for each of the plurality of output terminals of the output selector The output line counts by one for each cell transmission time required for each output line to transmit one cell, and the count value is determined by the read timing for each output line calculated by the read timing calculation means. If they are equal, a read timing output counter that outputs a read timing signal instructing output of the cell to the corresponding output line, or The read address control means reads the address from the address storage means for each of the output lines in response to the input of the read timing signal output from the read timing output counter, and stores the read address in the cell. The cell switching system according to claim 1, wherein the cell switching system is designated for the means. 4. The transmission line speed detection means further detects a new transmission speed each time the transmission speed of each transmission line changes, and the read timing calculation means further reads a new transmission speed of each transmission line from the transmission line speed detection means. A new read timing is calculated each time a new transmission rate is sent, and the read timing output counter clears the counter value to 0 each time a new read timing is sent from the read timing calculating means. , One for each cell transmission time required for each output line to transmit one cell thereafter.
If the count value becomes equal to the new read timing calculated by the read timing calculation means, a read timing signal instructing output of a cell to a corresponding output line is output. The cell switching system according to claim 2 or 3, wherein: 5. The cell storage device, the destination output line detection device, the address storage device, the read timing directing device and the read address control device are provided in the cell switching device, while the transmission line speed detection device is connected to the output line. The cell switching system according to claim 2, wherein the cell switching system is provided in a transmission line connection device for each output line for connecting to a transmission line.