KR100208933B1 - The method and system for cell delay using head table address of conection less server in atm - Google Patents

Abstract

The present invention eliminates the load of the head table processing, the control unit and the virtual connection cell reception processing unit required to process the message identifier without using the message identifier, makes the cell's identifier area available for other purposes, and occurs when comparing message identifiers. In order to implement a connectionless server by eliminating delays and additional control circuits, which are possible, the address of a header table having a different transmission path is used for delaying header processing of a cell of the connectionless server. The method characterized in that it is configured to indicate whether or not when using the delivery path.

Description

Cell Delaying Method and System using Head Table Address of Connectionless Server in Asynchronous Transfer Mode Network {THE METHOD AND SYSTEM FOR CELL DELAY USING HEAD TABLE ADDRESS OF CONECTION LESS SERVER IN ATM}

The present invention relates to a method of implementing a connectionless server in an asynchronous transfer mode (ATM), in particular, by eliminating the load required to process the message identifier by using no message identifier, and using the cell's message area for other purposes. The present invention relates to a cell delay method and system using a head table address of an unconnected server in an asynchronous transmission mode network that enables the use and eliminates more delays and additional circuits than may be necessary when comparing message identifiers.

With the spread of Asynchronous Transfer Mode (ATM) networks, the acceptance of existing networks such as local area networks (LANs) and public switched telephony networks (PSTNs) has become an important issue. A lot of research is underway to interwork with ATM networks based on connected services.For example, in ATM FORUM, the IETF for LAN emulation to implement high speed ATM-LAN by emulating MAC layer of existing LAN. The Internet Engineering Task Force (AR) addresses AR (Address Resolution) and frame encapsulation methods for delivering IP (Internet Protocol) datagrams to ATM networks, and ITU provides a connectionless broadband data service (CBDS) using a connectionless server. Many studies are underway on each protocol. In particular, the connectionless server converts the connectionless data input through the IWF (Interworking Function) connected one-to-one with the server via a virtual connection in the ATM network to an E.164 destination address value in a manner suitable for public networks. Perform the routing function to transfer to. The connectionless server converts the connectionless data inputted through the IWF (Interworking Function) connected to the server one-to-one through a virtual connection in the ATM network to an E.164 destination address value in a manner suitable for public networks. The structure of the connectionless server for performing the above functions is the physical layer matching unit 101, the cell receiving processing unit 102, the virtual connection processing unit 103 as shown in the example of FIG. Head table processing section 104, head table control section 105, cell transmission processing section 106, VP1 / VCI / MIDCAM section (Virtual Path Identifier / Virtual Channel Identifier / Multiple Identifier Content Access Memory) and VPI / VCI CAM section ( 107), a VPI / VCI table and a destination address CAM unit 108, a head table unit 109, and a processor unit 100.

Description of the function and operation of each part is as follows.

The physical layer matching unit 101 extracts an ATM cell from ATM-connected non-connected data input through an external UNI / NNI, an error check / correction of an HCS (Header Check Sequence), and an idle cell. Performs functions such as Idle Cell Filtering.

The cell receiver 102 checks whether the cell is allowed by comparing the information registered in the VPI / VCI and the VPI / VCI CAM 107 of the head of the non-connected cell input through the physical layer matching unit 101. The cell is discarded for the cells that are not allowed, and the error cells are discarded by checking the CRC (Cycle Redandency Check). In addition, the cell transmitter 102 is a cell to which an input is allowed, and if it is not a CRC error, VPI / VCI The head table address (HT_ADDR: Header Table Address) is searched from the / MID CAM 107, and the type of the input cell is determined and transmitted to the processor unit 100 in the case of an OAM cell. In case of the BOM or SSM cell, 102 transmits the head portion (HT_ADDR, MSG_ID, DA: Destination Address) of the cell (3B) to the virtual connection processor 103, and the entire cell, head table address and Send message identifier (MSG_ID) (E) to head table control unit 105, if COM / EOM The entire cell, the head table address, and the message identifier (MSG_ID) are transmitted to the head table controller 205. The virtual connection processor 103 uses the information input from the cell receiver 102 to determine the destination address CAM and VPI. The new MID available through the / VCI table, the VPI / VCI value to be converted and the connection identifier (CO_ID) are obtained, and the value of (3B) is obtained from the (VPI / VCI / MID, CO_ID, HT_ADDR, MSG_ID) head table processing unit 104. On the other hand, the virtual connection processing unit 103 receives the CO_ID, MID (B-1) input from the head table processing unit 104 to release the MID value according to the CO_ID so that it can be used later.

The head table controller 105 receives the head table address, the MID, and the entire cell transmitted from the cell reception processor 102, and transfers the head table address to the head table processor 104 as shown in Fig. 3E. The head table control unit 105 does not check the MSG_ID when the input cell is COM or EOM, and stores the MSG_ID inside the BOM and SSM cell, and then transfers it through the virtual connection processing unit 103 and the head table processing unit 104. The head table controller 105 determines the delay (VPI / VCI / MID) input from the head table processor 104 from the cell reception processor 102. After exchange with the inputted cell head, it is transmitted to the cell transmission processing unit 106. This is a 2-bit control signal input from the cell transmission processing unit 106, and the head table control unit 105 transmits the control signal D-1. Received, the day of the head table controller 105 in accordance with the control signal Stop the process, and if goes to stand-by state, a 1-bit control signal to the control signal (D-1) is an active start the data processing of the head table processing unit 104 again.

The head table processing unit 104 stores the head table address HT_ADDR and an internal occurrence address among the head values HT_ADDR, MSG_ID, VPI / VCI / MID / CO_ID of the figure 3B input from the virtual connection processing unit 103. The data (VPI / VCI / MID / CO_ID) is recorded in 13 bits of the VIP area of the head table section 109 while being synthesized and stored in the head table section 109 (Done = 1). As shown in Fig. 3E, the head 104 receives data (HT_ADDR, control signal) input from the head table controller 105 and controls the head table according to the cell type. The head table processor 104 inputs the head table. If the control signal 3E is a BOM or a COM cell, the contents of the head table are read and transmitted to the head table controller 105 (3D). If the input control signal is an SSM or EOM cell, the contents of the head table are read. 3D to the head table control unit 105, which is also the head table unit. The contents of the corresponding address (HT_ADDR + internal occurrence address) of step 109 are removed, and the CO_ID and MID corresponding to the removed head table address are sent to the virtual connection processor 103 (3C).

The cell transmission processing unit 106 receives a header exchanged 16-bit cell stream and a 2-bit synchronization signal cell input from the head table control unit 105 and checks the type of the cell (user cell, multicasting cell), thereby validating the multiplier. In the case of the casting cell, the cell is transferred to the processor unit 100 (3G), and in the case of the valid user cell, a CRC (Cycle Redandency Check) is generated and recorded in the CRC area of the cell and transmitted to the physical layer matching unit 101. On the other hand, the cell transmission processing unit 106 receives a multicasting cell or an OAM (Operation Maintenance) cell delivered from the processor unit 100 (3G) and performs a selective CRC according to a cell type to perform a physical layer matching unit. The cell transmission processor 106 may control the head table controller 105 according to the control signal input from the physical layer matching unit 101 and the presence or absence of a cell input from the processor unit 100. To send a control signal.

However, in the above-described configuration, the conventional connectionless server uses the cell reception processing unit 102 to secure the time required for the head processing in the virtual connection processing unit 103 when a cell (BOM, SSM) requiring head processing is input. A message identifier is generated and transmitted to the head table controller 105, and the head table controller 105 is a message identifier transmitted from the cell receiver 102 and the cell receiver 102 to the virtual connection processor 103. The message identifier can be compared with the message identifier only when the message identifier is transmitted to the head table controller 105 again. The delay obtaining method requires an additional controller for processing the message identifier for each path through which the message identifier is transmitted. The area of the cell occupied by the message identifier becomes unavailable. The comparison of the message identifier in the head table controller 105 is shown in Figs. 3A, 3B, and 3D. The delay condition is determined to be satisfactory only when the message identifier passed through the paths (3A), (3B) and (3D) is large by comparing the message identifier passed through the path with the message identifier passed through the path (3F). Since the message identifier is a value of a counter that increases every time the BOM and SSM cells pass in the cell receiving processor 102, the size of the message identifier is limited, and when the BOM and SSM cells are input at the maximum, the finite value is limited. Due to the characteristics of the counter, the value of the counter is changed to the minimum value. In the cell receiving processor 102, the forwarding path of the forwarding message identifier of the path (E) connected to the head table control unit 105 is fast, and therefore, the head table control unit 105 is fast. The drawback was that additional controls were needed to prevent the comparator from malfunctioning due to the message identifier passed in the path.

Accordingly, an object of the present invention is to remove a load of a head table processing, a control unit and a virtual connection cell reception processing unit required to process a message identifier without using the message identifier, and to provide a method and a system for using the cell identifier region for other purposes. In providing.

Another object of the present invention is to provide a method and system for implementing a connectionless server by eliminating delays and additional control circuits that are more than necessary for a head table controller that may occur when comparing message identifiers.

The present invention for achieving the above object eliminates the load required to process the message identifier by using a message identifier using a counter that increases every time the cell is entered to obtain the time delay required to process the head in a connectionless server. It is characterized in that it is configured to enable the use of the message identifier area of the cell for other purposes, and to remove the delay and additional control circuitry that is more than necessary when comparing the message identifier.

1 is a circuit diagram of a conventional connectionless server

2 is a table format diagram of the head table portion 109 of FIG.

3A-3F is a data transmission format diagram between the transmission paths A-G and A-1-G-1 of each part in FIG.

4 is a detailed circuit diagram of the head table processing unit 104 of FIG.

5A-5H are flow charts in accordance with an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a detailed circuit diagram of the head table processing unit 104 of FIG. 1 according to the present invention;

4 is a first receiver 401 which receives an input B from the virtual connection processor 103 of FIGS. 3A-3F,

A second receiver 402 for receiving an input (C-1) from the head table controller 105;

A head table control signal processing unit 406 for processing a head table control input from the processor unit 100;

Head table control signal transmission unit for transmitting the control result of the head table unit 109 by the head table control signal (C-1) input from the head table control unit 105 to the head table control unit 105 ( 405),

After the entry of the head table is removed by the head table control signal C-1 input from the head table control unit 105, the CO_ID and the MID of the removed entry are transmitted via the virtual connection processor 103. A transmission unit 404 for transmitting,

A control priority determination unit 403 for determining the control priority of the head table unit 109 from the head table control input of the processor 100,

An address (HT_ADDR + an internally generated address) for controlling the head table unit 109 and a control signal generator 407 for generating data and a control signal and providing the data to the head table unit 400 are provided.

The head table processing unit 104 receives data (HT_ADDR VPI / VCI / MID / CO_ID) from the virtual connection processing unit 103 through (B) to synthesize a head table address and an internal occurrence address to generate a header table unit ( 109), it indicates that data (VPI / VCI / MID / CO_ID) has been recorded in 13 bits of the VPI area of the head table (done = 1). In addition, the head table controller 105 receives data (HT_ADDR, control signal) input from the head table controller 105 and controls the head table according to the cell type (C-1). However, if the input control signal is a BOM or COM cell, the head table is used. Read the contents of the section 109 (VPI / VCI / MID) and transmit the contents to the head table control section 105 (C). In the case of SSM and EOM cells, the contents of the head table are read and transmitted to the head table control section 105. The contents of the corresponding address (HT_ADDR + internal occurrence address) of the head table are removed (done = 0), and the CO_ID and MID corresponding to the removed head table address are sent to the virtual connection processor 103 (B-1). The cell transmission processing unit 106 receives the cell D exchanged with the head input from the head table control unit 105, and checks the type of the cell (user cell, multicasting cell) and the error, thereby valid multicasting. In the case of the cell, the cell is transmitted to the processor unit 100 (F). In the case of a cell, a CRC (Cycle Redandency Check) is generated and recorded in the CRC area of the cell and transmitted to the physical layer matching unit 101 (G), and transmitted from the processor unit 100 (F-1). It receives the casting cell or OAM (Operation Maintenance) and executes an optional CRC (LSB3 of the third word) according to the cell type and delivers it to the physical layer matching unit 101. The input from the physical layer matching unit 101 is performed. The control signal D-1 is sent to the head table controller 105 according to the control signal G-1 and the presence / absence of a cell input from the processor 100.

5A-5H illustrate the head processing in the virtual connection processing unit 103 and the head table processing unit 104 using the propagation path difference of the head table address without using a message identifier for cell delay according to an embodiment of the present invention. The operation flow chart required for

In the first process, the CPU 100, the virtual connection processing unit 103, and the head table processing unit 104 check the presence or absence of any one of the accesses by going through steps (501, 503, 504) of FIG. 5A. Here, CPU = 1, B = 1 and C-1 = 1 indicate that access is in progress, and CPU = 0, B = 0 and C-1 = 0 indicate that the access is suspended.

In the second process, if there is an input of the CPU 100 and the virtual connection processing unit 103 or the head table control unit 105 is not in access, setting according to the access of the CPU in step 506 to prevent a collision of type forces is performed. In step 507, the head table unit 109 is accessed under the control of the CPU to complete the process, and in step 508, the CPU is stopped.

The third process is input by the virtual connection processing unit 103 in step 501, and in step 502 to prevent a collision of type forces when the CPU 100 or the head table control unit 105 is not being accessed. The virtual connection processor 103 is set according to the access, and the output of the virtual connection processor 103 is read at step 509 to check whether the length of the input synchronization signal is correct at step 510.

If the length of the input synchronization signal does not match in step 510, the fourth process deletes the read B input in step 511, and stops access to the virtual connection processor 103 in step 512. On the other hand, when the length of the input synchronization signal is correct in step 510, the head table HT address and the inner address for the VPI are performed in step 514 in step 514. The generated address reads the VPI of the head table HT.

In the fifth process, if it is determined in step 515 that there is a VPI value in the VPI region read in step 514, the step V5 is set to access VD in step 516, and in step 533 and step 535. If the number of received cells is counted and the number of cells is 15 or more in step 536, the VD is discarded in step 539. If the number of cells is less than 15, the head table unit 109 in step 537. Read VPI from and check whether it is set in step 538.

In step 6B, if there is no VPI value in step 515 of FIG. 5B, the VPI value is set for accessing the VPI in step 517 and the VPI is written to the head table 109 in step 557. In step), the head table for the VCI, MID, and CO-ID are combined with the internal address, and the VCI, MID, and CO-ID are written to the head table unit 109 by going from step 519 to step 521. In step 522, the access of the virtual connection processor 103 is set to be stopped.

In the seventh process, the VD at step 539 stops access, and at step 540 to step 544, the head table address and the internal address for the CO-ID and MID are combined with the head table HT. CO-ID and MID are read and outputted from step 545. After clearing the VPI in step 545, the head table address and the internal address are generated for the new VPI write in step 546. Light it.

The eighth process is input by the head table control unit 105 in step 504, and in step 505 to prevent a collision of type forces if the CPU 100 or the virtual connection processing unit 103 is not being accessed. Set according to the access of the head table controller 105, check whether the cell is a BOM, SSM, EOM, or COM cell from step 561 to step 565, and check whether the cell is DEL when not COM. At step 566, the head table controller 105 stops access.

In the ninth process, the process according to the COM is performed through the steps 561 to 567 in the eighth process, the process according to the DEL is performed through the step 568 to 575, and in step 576. After processing according to the EOM through (587), while clearing the waiting time of step (588) in the case of BOM cell, in step 590, an address for the VPI is generated, and the head table address and the internal address are synthesized. The VPI is read from the head table unit 109 in step 590 to detect whether there is a VPI in step 591.

The tenth step has a sufficient time according to the cell processing in step (5555) in step 592 in step ninth, and then goes through step (593) and step (596) in step 553, and the head table address for the VCI and MID. And VCI and MID are read and the VPI, VCI and MID are output at the same time (597).

In the eleventh process, when the SSM cell is cleared in step 562 of the eighth step, after the waiting time is cleared in step 600, the head table address and the internal address are synthesized from the address for the VPI through the steps 601 and 602. The VPI is read from the head table to detect whether there is a VPI in step 603.

The twelfth process has a sufficient time according to the cell processing in step 606 and waits a predetermined time in step 11, and then goes through the step 606 to 611 and the head table address for the VCI, MID, and CO-ID. After synthesizing the internal addresses, the VCI, MID, and CO-IDs are read, and the VPI and VCI are controlled and output at the same time, the MID and CO-IDs are output in step 612, and the VPI is cleared in step 613. In step 614, the VPI is written to the new head table.

In step 13, when the EOM cell is in step 563 of step 8, the head table address and the internal address are synthesized from the head table by combining the addresses for the VPI, VCI, and MID, from step 576 to step 587. Read and output VPI, VCI and MID, and combine the head table address and internal address for CO-ID and read the CO-ID from it (585) to output MID, CO-ID (step 586). After clearing the VPI in step 5, write the new VPI to the head table in step 587.

In step 14, when the COM cell of step 8 of step 564 is performed, the head table address and the internal address are combined with the address for the VPI, VCI, and MID from step 561 to step 567 in step 567. Read and output the VCI and the MID.

In the fifteenth step, when the DEL cell in step 565 of step 8 is performed, the head table address and the internal address are combined with the address for the CO-ID and MID from step 568 to step 575. -ID and MID are read and output. After clearing the VPI, the new VPI is written to the head table by combining the head table address and the internal address for the VPI.

In step 16, after the fifth process is completed in the ninth process, the access of the head table controller 105 is stopped in step 615. That is, the header table address HT_ADDR generated by the cell receiving processor 102 is terminated. The header table addresses of the BOM and SSM cells are transmitted to the header table processing unit 104 through the paths (A) and (B), and the BOM, COM, EOM, SSM cells and the header table addresses (HT_ADDR) are (E), (A), (B) When the header table address (HT_ADDR) has passed through the path to the header table processing unit 106 (A), ( B) Combining the header table address of the path and the internal occurrence address, select an unused location (BIT13 in the VPIO area of the header table) to indicate that the header table addresses of the paths (A) and (B) have been arrived. Header table addresses and control signals passing through the paths (E) and (C-1) arrive at the header table processing unit 104. (E) and (C-1) header tables. Combining the source and internal occurrence addresses to retrieve the arrival of the header table address (HT_ADDR) via the paths (A) and (B) of the header table. [A], (B) path header table address of the header table If the arrival indication area (done = 1) is displayed, it is determined that the header processing (VPI / VCI / MID / CO_ID) of the virtual connection processing unit 103 and the header table processing unit 104 is completed, and the header table address (HT_ADDR) And the header table corresponding to the internal occurrence address is read and transmitted to the header table controller 105 (C) to exchange the header of the cell.

As described above, in order to obtain a time delay required for processing a header in a connectionless server, a message identifier using a counter that increases every time a BOH, SSH cell is input is used to eliminate the load required to process the message identifier, and The advantage of enabling the message identifier area for other purposes and eliminating delays and additional control circuitry beyond the need of the head table control unit 105, which may occur when comparing message identifiers, results in a simple connectionless server.

Claims (2)

A cell delay method using a head table address of a connectionless server in an asynchronous transmission mode network having a CPU, a virtual connection processing unit, a head table control unit, and a head table unit, A first step of checking whether the CPU, the virtual connection processor, or the head table processor checks any one of the dual accesses in the head table processor; In the first step, if there is an input of the CPU and the virtual connection processing unit or the head table processing unit is not being accessed, a setting is made according to the CPU access to prevent a collision of type forces, and the head table unit is accessed by the control of the CPU. A second process of stopping access of the CPU after completing this; If there is an input of the virtual processing unit in the first step and the CPU or the head table processing unit is not being accessed, a setting according to the access of the virtual processing unit is made in order to prevent a collision of type forces, and an output synchronous signal is read by reading the output of the virtual processing unit. A third step of checking whether the length of the If the length of the input synchronization signal does not match in the third step, the read input is deleted, the access to the virtual processing unit is stopped, and the head table address and the internal address for VPI are synthesized when the length of the input synchronization signal is correct. A fourth process of reading the VPI of the head table by In the VPI region read in the third step, if there is a VPI value, the VD is set to be accessed. If the number of received cells is counted, the VD is discarded. If the number of cells is within the predetermined number, the VPI is determined from the head table. The fifth step of checking whether the setting of In the fifth step, if there is no VPI value, the VPI value is set for access to the VPI, the VPI is written to the head table, the head table for the VCI, MID, and CO-ID is combined with the internal address. A sixth step of setting access to stop the access of the virtual connection processor after writing In the fifth step, the VD stops the access, synthesizes the head table address and the internal address for the CO-ID and MID, reads the CO-ID and MID from the head table, outputs them, clears the VPI, and then writes a new VPI light. A seventh process of writing the head table address and the internal address to write the VPI to the head table; In the first step, if there is an input of the head table processing unit and the CPU or virtual connection processing unit is not being accessed, the cell table is set according to the access of the head table processing unit to prevent the collision of type force and the cell is set to BOM, SSM, EOM, COM. An eighth step of checking whether the cell is applied and stopping access to the head table controller when the DEL is not checked by checking whether the cell is not COM; A ninth step of detecting whether there is a VPI by reading the head table address and the internal address by synthesizing the address for the VPI and then combining the head table address and the internal address when the BOM cell is cleared in the eighth step; A tenth step of synthesizing the head table address and the internal address for the VCI and the MID, reading the VCI and the MID, and outputting the VPI, the VCI and the MID at the same time after the predetermined waiting time in the ninth process; An eleventh step of detecting whether there is a VPI by reading the head table address and the internal address by combining the head table address and the internal address for the VPI after clearing the waiting time in the SSM cell in the eighth step; In the eleventh process, after sufficient time according to the predetermined cell processing, the head table address and the internal address for VCI, MID, and CO-ID are synthesized to lead VCI, MID, and CO-ID, and simultaneously control VPI and VCI. Outputting the MID and CO-ID, clearing the VPI, and writing the VPI to the new head table. In the eighth step, the head table address and the internal address are combined with the head table address and the internal address for the VPI, VCI, and MID, and the VPI, VCI, and MID are read from the head table and output. 13th step of synthesizing the address, reading the CO-ID from it, outputting the MID and CO-ID, clearing the VPI, and writing a new VPI to the head table; A 14th process of combining the head table address and the internal address with the address for VPI, VCI, and MID when the COM cell is performed in the step 8 to read and output the VPI, VCI, and MID from the head table; In the eighth step, the head address for the CO-ID and MID is combined with the head table address and the internal address, and the CO-ID and MID are read from the head table and outputted. A fifteenth step of composing the table address and the internal address to write a new VPI to the head table; The cell delay method using the head table address of the connectionless server in the asynchronous transmission mode network, characterized in that the sixth step of stopping the access to the head table control unit 105 after completing the fifth step in the ninth process. In the asynchronous transmission mode network including the virtual connection processing unit 103, the head table unit 109, the head table control unit 105, the cell receiving unit 102, and the processor unit 100, the head table address of the non-connection server is used. In the cell delay circuit, A first receiver 401 which receives an input B from the virtual connection processor 103; A second receiver 402 for receiving an input (C-1) from the head table controller 105; A head table control signal processing unit 406 for processing a head table control input from the processor unit 100; Head table control signal transmission unit for transmitting the control result of the head table unit 109 by the head table control signal (C-1) input from the head table control unit 105 to the head table control unit 105 ( 405), After the entry of the head table is removed by the head table control signal C-1 input from the head table control unit 105, the CO_ID and the MID of the removed entry are transmitted via the virtual connection processor 103. A transmission unit 404 for transmitting, A control priority determination unit 403 for determining the control priority of the head table unit 109 from the head table control input of the processor 100, An asynchronous transmission, comprising an address (HT_ADDR + an internally generated address) for controlling the head table unit 109 and a control signal generator 407 for generating data and control signals to the head table unit 400. Cell Delay System Using Head Table Address of Non-Connection Server in Modal Network