JP2001526412A - Fabrication of a matrix composed of thin-film transistors with storage capacitors - Google Patents
Fabrication of a matrix composed of thin-film transistors with storage capacitorsInfo
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- JP2001526412A JP2001526412A JP2000524811A JP2000524811A JP2001526412A JP 2001526412 A JP2001526412 A JP 2001526412A JP 2000524811 A JP2000524811 A JP 2000524811A JP 2000524811 A JP2000524811 A JP 2000524811A JP 2001526412 A JP2001526412 A JP 2001526412A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000003860 storage Methods 0.000 title claims abstract description 15
- 239000011159 matrix material Substances 0.000 title claims abstract description 14
- 239000010409 thin film Substances 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 9
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 17
- 229920000642 polymer Polymers 0.000 claims description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 229920001940 conductive polymer Polymers 0.000 claims description 5
- 239000012780 transparent material Substances 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 3
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 241001239379 Calophysus macropterus Species 0.000 description 1
- 229910016024 MoTa Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133357—Planarisation layers
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
(57)【要約】 マトリックスのパッシベーション化のためのプロセス工程数を低減するために、かつ画素電極を製造するためにそれぞれ、光構造化可能な材料を使用する、殊には液晶ディスプレイのための記憶コンデンサを伴う薄膜トランジスタからなるマトリックスの製法を提案している。 (57) Abstract: In order to reduce the number of process steps for the passivation of the matrix and to manufacture the pixel electrodes, respectively, use optically structurable materials, in particular for liquid crystal displays. A method for producing a matrix of thin film transistors with storage capacitors is proposed.
Description
【0001】 本発明は、独立請求項に記載の分野の、殊には液晶ディスプレイのための、記
憶コンデンサを伴う薄膜トランジスタからなるマトリクスの製法から出発する。The invention starts from the process of producing a matrix of thin-film transistors with storage capacitors in the field of the independent claims, in particular for liquid-crystal displays.
【0002】 DE4310640C1及びDE4339721A1からそれぞれ、液晶ディ
スプレイのための記憶コンデンサを伴う薄膜トランジスタからなるマトリクスの
製法は公知であり、その際、フォトリソグラフィによる必要なマスク工程数を3
もしくは4に低減することにより製造経費が節減される。薄膜トランジスタのた
めの半導体として公知の方法では、a−Si:Hが使用される。しかし、他のプ
ロセス工程、例えばエッチング、被覆及び洗浄の省略による薄膜トランジスタマ
トリクスを製造するための製造経費の低減は、この方法では予定されていない。From DE 43 10 640 C1 and DE 43 39 721 A1, respectively, the production of a matrix of thin-film transistors with storage capacitors for a liquid crystal display is known, in which case the number of mask steps required by photolithography is reduced to three.
Alternatively, by reducing the number to 4, manufacturing costs can be reduced. In a known method as a semiconductor for a thin film transistor, a-Si: H is used. However, no reduction in manufacturing costs for manufacturing a thin film transistor matrix by omitting other process steps, such as etching, coating and cleaning, is not planned in this way.
【0003】 本発明の利点 独立請求項に記載の特徴を伴う本発明の方法は公知の方法に対して、より少な
い被覆工程、エッチング工程並びにフォトラッカー除去工程を必要とするという
利点を有する。Advantages of the invention The method of the invention with the features of the independent claims has the advantage over known methods that fewer coating, etching and photo-lacquering steps are required.
【0004】 これは、マトリックスをパッシベーションするために、かつ画素電極を製造す
るためにそれぞれ、光構造化可能な材料を使用することにより達成される。パッ
シベーションとしてSiNxを、かつ画素電極として通常、ITOを使用する公 知の方法に対してこれにより、それぞれ被覆工程、即ちSiNxのためのPEC VD法及びITOのスパッタリングを、それぞれエッチング工程、即ちSiNx の乾式エッチング及びITOの湿式エッチングを、かつそれぞれフォトラッカー
マスクの洗浄のための工程及びそのための装置を省くことができる。This is achieved by using optically structurable materials, respectively, for passivating the matrix and for producing the pixel electrodes. In contrast to known methods using SiN x as passivation and usually ITO as pixel electrodes, respectively, the coating step, namely the PEC VD method for SiN x and the sputtering of ITO, respectively, is now carried out in the etching step, ie in each case using the ITO step. It is possible to omit the dry etching of SiN x and the wet etching of ITO, and a step for cleaning the photo-lacquer mask and a device therefor, respectively.
【0005】 従属請求項に記載の方法により、独立請求項に記載の方法の有利な進展及び改
善が可能である。[0005] Advantageous developments and improvements of the method described in the independent claim are possible with the method described in the dependent claims.
【0006】 例えば、光構造化可能な材料としてポリマーを使用するのが特に有利である。
この場合、パッシベーションのために、高絶縁性の感光性透明ポリマーを、かつ
画素電極の製造のために導電性ポリマーを使用することができる。For example, it is particularly advantageous to use polymers as photostructurable materials.
In this case, a highly insulating photosensitive transparent polymer can be used for passivation, and a conductive polymer can be used for manufacturing a pixel electrode.
【0007】 導電性ポリマーの機械的研磨処理により更に、液晶の配向を行うことができる
ので、付加的な配向層、例えばポリイミドの施与を完全に省くことができる。[0007] The mechanical polishing of the conductive polymer further allows for the alignment of the liquid crystal, so that the application of an additional alignment layer, for example polyimide, can be omitted altogether.
【0008】 有利な1製法では、個々の工程は次のような工程である: − 薄膜トランジスタ−マトリクスの行として、トランジスタのゲート−コンタ
クトとして、かつ記憶コンデンサの電極として、第1の導電層を施与及び構造化
する、 − ゲート−絶縁体を施与する、 − 半導体を施与する、 − トランジスタのドレイン−及びソース−コンタクトとしてP型又はN型ドー
ピングされた半導体を施与する、 − 薄膜トランジスタ−マトリクスの列のために、ドレイン−及びソース−コン
タクト及び記憶コンデンサの対抗電極のために、もう1つの導電性層を施与し、
かつ構造化する、 − ドーピングされた半導体層及びドーピングされていない半導体層を構造化す
る、 − 絶縁性の感光性透明材料を施与し、露光し、かつ現像する、 − 絶縁性の感光性透明材料を施与し、露光する。In one advantageous process, the individual steps are as follows: The first conductive layer is applied as a row of a thin-film transistor matrix, as a gate-contact of a transistor and as an electrode of a storage capacitor. Applying and structuring; applying a gate-insulator; applying a semiconductor; applying a P-type or N-type doped semiconductor as a drain and source contact of the transistor; a thin film transistor; Applying another conductive layer for the columns of the matrix, for the drain and source contacts and the counter electrode of the storage capacitor,
And structuring the doped and undoped semiconductor layers;-applying, exposing and developing an insulating photosensitive transparent material;-an insulating photosensitive transparent. Apply material and expose.
【0009】 この場合有利には、半導体としてa−Siを、かつゲート絶縁層としてSiN x を使用することができる。In this case, advantageously, a-Si is used as the semiconductor and SiN is used as the gate insulating layer. x Can be used.
【0010】 プロセス工程数のかなりの低減により、明らかな経費削減及びそれと同時に収
量の増加を達成することができる。[0010] With a considerable reduction in the number of process steps, a clear cost reduction and at the same time an increase in the yield can be achieved.
【0011】 図面 本発明の実施例を図面に示し、かつ次の記載により詳述する。図1は様々な製
造段階での液晶ディスプレイン画素の断面図を示している。Drawings Embodiments of the present invention are shown in the drawings and are described in detail in the following description. FIG. 1 shows cross-sectional views of a liquid crystal display pixel at various stages of manufacture.
【0012】 図1a)に記載の製造段階では、ガラス基板10上に第1の金属被覆層11、
例えば200nmMoTaがスパッタリングされ、かつ行線として、かつ記憶コ
ンデンサ配線として構造化されている。続いて、ゲート絶縁層12、例えば35
0nmSiNx、真性半導体13、例えば150nmi−a−Si及び高ドーピ ング半導体14、例えば50nm n+−a−Si及び被覆金属化層(Deckmetall
isierung)、例えば200nmMoからなる層系列が施与されている。In the manufacturing stage according to FIG. 1 a), a first metallization layer 11
For example, 200 nm MoTa is sputtered and structured as row lines and as storage capacitor wiring. Subsequently, the gate insulating layer 12, for example, 35
0NmSiN x, intrinsic semiconductor 13, for example 150nmi-a-Si and high-Doping semiconductor 14, for example, 50nm n + -a-Si and the coating metal layer (Deckmetall
iserung), for example a layer sequence of 200 nm Mo is applied.
【0013】 図1b)は、被覆金属化層15及びドーピング層14を列配線、ドレイン/ソ
ースコンタクトD、Sとして、かつ記憶コンデンサCの被覆電極(Deckelektrode
)としてエッチングした後の構造を示している。FIG. 1 b) shows the covering metallization layer 15 and the doping layer 14 as column wiring, drain / source contacts D, S and the covering electrode of the storage capacitor C (Deckelektrode).
) Shows the structure after etching.
【0014】 図1c)の方法段階では、半導体層13及びゲート誘電体12が唯一つのプラ
ズマエッチング工程で、画素の個々の薄膜トランジスタを分割するために、かつ
ゲート配線及び記憶コンデンサ配線の接続領域を露出させるために製造されてい
る。In the method step of FIG. 1c), the semiconductor layer 13 and the gate dielectric 12 are used in a single plasma etching step to divide the individual thin-film transistors of the pixel and to expose the connection areas of the gate lines and the storage capacitor lines. Manufactured to let.
【0015】 図1d)では、高導電性の感光性透明ポリマー16が施与され、感光され、現
像され、かつ熱処理されている。ポリマーとして例えばいわゆるフォト−BCB
を使用することができる。ポリマーの課題は、構造をパッシベーションし、かつ
平坦化することにある。ここでは同時に薄膜トランジスタのドレイン−コンタク
トである記憶コンデンサCの被覆電極及び列線及び行線の接続領域が、ポリマー
の露光工程及び現像工程で再び露出している。In FIG. 1 d), a highly conductive photosensitive transparent polymer 16 has been applied, exposed, developed and heat treated. As a polymer, for example, so-called photo-BCB
Can be used. The challenge with polymers is to passivate and planarize the structure. Here, at the same time, the covering electrode of the storage capacitor C, which is the drain-contact of the thin film transistor, and the connection region of the column line and the row line are exposed again in the polymer exposure step and the development step.
【0016】 図1e)では引き続き、導電性の感光性透明ポリマー17が画素電極として施
与されている。このために例えば、Bayer AG社の商品名PEDT/PSSのポリマーを使
用することができる。フォトマスクを介してUV光を用いて画素電極間の領域を
露光すると、導電性ポリマーが絶縁層に変化する。ポリマーの絶縁領域は図1e
)中で点を打たれて示されている。導電性感光性ポリマーを使用する場合には、
画素電極間の領域を現像液工程により除去することもできる。個々の画素電極は
効果的に、電気的に相互に分離することもできる。画素電極の露光されなかった
領域は、約130℃でのポリマーPEDT/PSSの熱処理工程の後に、面積あたり層抵
抗200〜1000Ω及び乾燥膜厚900nmでは可視領域で>70%の透明度
を有する。乾燥膜厚を低減することにより、透過率を高めることができる。層1
7は引き続き、機械的に研磨されて、液晶の配向をもたらしうる。これにより、
付加的な配向層の施与を省くこともできる。In FIG. 1 e), a conductive photosensitive transparent polymer 17 is subsequently applied as a pixel electrode. For this purpose, for example, a polymer with the trade name PEDT / PSS from Bayer AG can be used. When a region between pixel electrodes is exposed to light using UV light through a photomask, the conductive polymer is changed into an insulating layer. The insulating region of the polymer is shown in FIG.
) Are shown dotted. When using conductive photopolymer,
The region between the pixel electrodes can be removed by a developer step. The individual pixel electrodes can also be effectively and electrically separated from each other. The unexposed regions of the pixel electrode have a transparency of> 70% in the visible region at a layer resistance per area of 200-1000Ω and a dry film thickness of 900 nm after a heat treatment step of the polymer PEDT / PSS at about 130 ° C. By reducing the dry film thickness, the transmittance can be increased. Layer 1
7 may subsequently be mechanically polished to provide liquid crystal alignment. This allows
The application of an additional alignment layer can also be omitted.
【0017】 ゲート誘電体12の構造化は、図示されているようにドーピングされていない
半導体13の構造化と共に、又はマスキングとしてのパッシベーション層16と
も共に付加的なプラズマエッチングプロセスで実施することができる。The structuring of the gate dielectric 12 can be carried out with the structuring of the undoped semiconductor 13 as shown, or with an additional plasma etching process together with the passivation layer 16 as masking. .
【図1】 本発明の1実施態における様々な製造段階での液晶ディスプレイ画素の断面図
を示す図。FIG. 1 illustrates a cross-sectional view of a liquid crystal display pixel at various stages of manufacture according to one embodiment of the present invention.
C 記憶コンデンサ、 D及びS ドレイン及びソース−コンタクト、 G
ゲート−コンタクト、 10 第1の導電層、 12 ゲート絶縁層、 13
ドーピングされていない半導体、 14 p型又はn型ドーピングされた半導体
、 15 もう1つの導電層、 16 高絶縁性の感光性透明材料、 17 導
電性の感光性透明材料C storage capacitor, D and S drain and source-contact, G
Gate-contact, 10 first conductive layer, 12 gate insulating layer, 13
Undoped semiconductor, 14 p-type or n-type doped semiconductor, 15 another conductive layer, 16 highly insulating photosensitive transparent material, 17 conductive photosensitive transparent material
【手続補正書】特許協力条約第34条補正の翻訳文提出書[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty
【提出日】平成12年2月29日(2000.2.29)[Submission date] February 29, 2000 (2000.2.29)
【手続補正1】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Correction target item name] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【特許請求の範囲】[Claims]
───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 2H092 HA06 JB61 JB66 KA05 KA12 KB04 KB24 MA17 MA27 NA01 NA27 NA29 PA02 5F110 AA16 BB01 CC07 DD02 EE06 EE44 FF03 GG02 GG15 GG35 HK04 HK09 HK16 HL01 NN02 NN27 NN73 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 HA06 JB61 JB66 KA05 KA12 KB04 KB24 MA17 MA27 NA01 NA27 NA29 PA02 5F110 AA16 BB01 CC07 DD02 EE06 EE44 FF03 GG02 GG15 GG35 HK04 HK09 HK16 HL01 NN02 NN27 NN27 NN27
Claims (7)
伴う薄膜トランジスタからなるマトリクスの製法において、マトリクスのパッシ
ベーションのために、かつ画素電極の製造のためにそれぞれ、光構造化可能な材
料(16、17)を使用することを特徴とする、記憶コンデンサを伴う薄膜トラ
ンジスタからなるマトリクスの製法。1. A method for producing a matrix comprising thin-film transistors with storage capacitors (C), in particular for liquid crystal displays, in each case being optically structurable for the passivation of the matrix and for the production of the pixel electrodes. A method for producing a matrix comprising thin film transistors with storage capacitors, characterized in that the use of a simple material (16, 17).
する、請求項1に記載の製法。2. The method according to claim 1, wherein the photostructurable material is a polymer.
16)を、かつ画素電極の製造のために導電性ポリマー(17)を使用する、請
求項2に記載の製法。3. A highly insulating photosensitive transparent polymer for passivation.
The method according to claim 2, wherein the conductive polymer (17) is used for the production of the pixel electrode.
向を行う、請求項3に記載の製法。4. The method according to claim 3, wherein the liquid crystal is aligned by mechanically polishing the conductive polymer (17).
クト(G)として、かつ記憶コンデンサ(C)の電極として、第1の導電層(1
0)を施与及び構造化する、 − ゲート−絶縁体(12)を施与する、 − 半導体(13)を施与する、 − トランジスタのドレイン−及びソース−コンタクト(D、S)としてP型又
はN型ドーピングされた半導体(14)を施与する、 − 薄膜トランジスタ−マトリクスの列のために、ドレイン−及びソース−コン
タクト(D、S)及び記憶コンデンサ(C)の対抗電極のために、もう1つの導
電性層(15)を施与し、かつ構造化する、 − ドーピングされた半導体層(14)及びドーピングされていない半導体層(
13)を構造化する、 − 絶縁性の感光性透明材料(16)を施与し、露光し、かつ現像する、 − 導電性の感光性透明材料(17)を施与し、露光する による、請求項1から4までのいずれか1項に記載の製法。5. The following steps: a first conductive layer (1) as a thin-film transistor matrix row, as a transistor gate-contact (G) and as an electrode of a storage capacitor (C);
0) applying and structuring;-applying a gate-insulator (12);-applying a semiconductor (13);-drain- and source-transistors of the transistor as P-type as contacts (D, S). Or applying an N-doped semiconductor (14), for the columns of the thin film transistor matrix, for the drain and source contacts (D, S) and for the counter electrodes of the storage capacitors (C). Applying and structuring one conductive layer (15), a doped semiconductor layer (14) and an undoped semiconductor layer (
13) structuring,-applying, exposing and developing an insulating photosensitive transparent material (16);-applying and exposing a conductive photosensitive transparent material (17); The method according to any one of claims 1 to 4.
Nxを使用する、請求項5に記載の製法6. A semiconductor device comprising a-Si: H as a semiconductor and Si as a gate insulating layer.
6. The process according to claim 5, wherein Nx is used.
シベーション層(16)と共に別の工程で構造化する、請求項5又は6に記載の
製法。7. The method according to claim 5, wherein the gate insulating layer is structured in a separate step with the photo-structurable passivation layer as a mask.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19754784.2 | 1997-12-10 | ||
DE19754784A DE19754784B4 (en) | 1997-12-10 | 1997-12-10 | Process for producing a matrix from thin-film transistors with storage capacities |
PCT/EP1998/007361 WO1999030352A2 (en) | 1997-12-10 | 1998-11-17 | Method for producing a matrix from thin-film transistors with storage capacities |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001526412A true JP2001526412A (en) | 2001-12-18 |
Family
ID=7851371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000524811A Pending JP2001526412A (en) | 1997-12-10 | 1998-11-17 | Fabrication of a matrix composed of thin-film transistors with storage capacitors |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1038320A2 (en) |
JP (1) | JP2001526412A (en) |
KR (1) | KR20010032940A (en) |
DE (1) | DE19754784B4 (en) |
TW (1) | TW432707B (en) |
WO (1) | WO1999030352A2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19933843B4 (en) * | 1999-07-20 | 2005-02-17 | Robert Bosch Gmbh | A layer containing electrically conductive, transparent material, a method of making such a layer and their use |
KR100485625B1 (en) * | 2001-12-20 | 2005-04-27 | 엘지.필립스 엘시디 주식회사 | Liquid Crystal Display Device and Fabricating Method Thereof |
KR101023292B1 (en) * | 2003-10-28 | 2011-03-18 | 엘지디스플레이 주식회사 | Method for manufacturing lcd |
CN103700673B (en) * | 2013-12-24 | 2017-07-04 | 京东方科技集团股份有限公司 | A kind of display device, array base palte and preparation method thereof |
US11676855B2 (en) * | 2020-02-26 | 2023-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Patterning interconnects and other structures by photo-sensitizing method |
DE102020130905A1 (en) | 2020-02-26 | 2021-08-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structuring of interconnects and other structures using photosensitization processes |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61292183A (en) * | 1985-05-25 | 1986-12-22 | 旭硝子株式会社 | Electrochromic display element |
DE4310640C1 (en) * | 1993-03-31 | 1994-05-11 | Lueder Ernst | Thin-film transistor matrix mfg. system - with subsequent indium-tin oxide layer used as mask for etching prior metallisation mark |
ATE287929T1 (en) * | 1994-05-06 | 2005-02-15 | Bayer Ag | CONDUCTIVE COATINGS MADE FROM MIXTURES CONTAINING POLYTHIOPHENES AND SOLVENTS |
KR970011972A (en) * | 1995-08-11 | 1997-03-29 | 쯔지 하루오 | Transmission type liquid crystal display device and manufacturing method thereof |
JPH0990421A (en) * | 1995-09-27 | 1997-04-04 | Sharp Corp | Liquid crystal display device and its manufacture |
DE69633523T2 (en) * | 1995-11-22 | 2006-02-16 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy Naval Research Laboratory | CONDUCTIVE PATTERNED POLYMER SURFACE, METHOD FOR THE PRODUCTION THEREOF AND METHOD OF CONTAINING THEREOF |
-
1997
- 1997-12-10 DE DE19754784A patent/DE19754784B4/en not_active Expired - Fee Related
-
1998
- 1998-11-17 EP EP98966240A patent/EP1038320A2/en not_active Ceased
- 1998-11-17 JP JP2000524811A patent/JP2001526412A/en active Pending
- 1998-11-17 WO PCT/EP1998/007361 patent/WO1999030352A2/en not_active Application Discontinuation
- 1998-11-17 KR KR1020007006284A patent/KR20010032940A/en not_active Application Discontinuation
- 1998-12-07 TW TW087120245A patent/TW432707B/en active
Also Published As
Publication number | Publication date |
---|---|
DE19754784B4 (en) | 2004-02-12 |
WO1999030352A3 (en) | 1999-12-09 |
KR20010032940A (en) | 2001-04-25 |
EP1038320A2 (en) | 2000-09-27 |
WO1999030352A2 (en) | 1999-06-17 |
DE19754784A1 (en) | 1999-06-24 |
TW432707B (en) | 2001-05-01 |
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