JP2001517866A - Technology for manufacturing and mounting multi-wavelength semiconductor laser array devices (chips) and their application in system architecture - Google Patents

Abstract

  (57) [Summary] Fabricate single or multiple sub-micron pitch linear and curve gratings on wafers / substrates simultaneously, with or without a sharp quarter-wave shift (or gradually changing finer phase shift) A phase mask that can be used to perform This phase mask uses direct writing electron or ion beam lithography at twice the required submicron pitch of linear and curve gratings on commercially available π phase shift material on a quartz substrate, and π It is manufactured using wet or dry etching of a phase shift material. This phase mask can be used for making multi-wavelength laser diode chips. The laser diode has a ridge structure having metal shoulders on both sides of the ridge. Laser diode chips with lasers of different wavelengths are bonded and interfaced to a novel microwave substrate that allows for high signal-to-noise ratio and low crosstalk. This substrate is mounted in a low loss undulating housing for WDM applications.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] This application claims priority to the following US provisional application, the entire disclosure of which is hereby incorporated by reference for all purposes:

“TECHNIQUES FOR FABRICATING AND PAC
KAGING MULTI-WAVELENGTH SEMICONDUCTO
R LASER ARRAY DEVICES (CHIPS) AND TH
EIR APPLICATIONS IN SYSTEM ARCHITECT
Uhams, Mohammad A. U.S.A.
Mazed Application No. 60 / 059,446 (Attorney Dock)
et No. 18579-1), and "TECHNIQUES FOR FABRICATING AND PAC"
KAGING MULTI-WAVELENGTH SEMICONDUCTO
R LASER ARRAY DEVICES (CHIPS) AND TH
EIR APPLICATIONS IN SYSTEM ARCHITECT
Mohammad A, filed October 28, 1997, entitled "URES"
. No. 60 / 063,560 of Mazed (Attorney Doc)
ket No. 18579-1-1).

BACKGROUND OF THE INVENTION [0003] This application relates generally to optical communications, and more particularly, to techniques for manufacturing and packaging multi-wavelength distributed feedback (DFB) semiconductor laser (laser diode) arrays. All patent documents and other publications cited herein are hereby incorporated by reference for all purposes.

[0004] The rapid advances in communication (telephone and computing) technology have fundamentally changed the way people connect through voice, video, and data throughout the world. These technologies can vary greatly in application, but all technologies share common requirements. That is, an ever-increasing demand for 10 Mbit / sec to 100 Gbit / sec and more and faster speeds and more and more bandwidth. The need for increased bandwidth is equally pressing in both wireless and fiber optic networks.

[0005] While wireless technology gives the freedom to communicate without using any wiring, wireless technology can currently be limited to low to medium bandwidth applications. For high bandwidth applications (greater than 10 Gbit / s), at this time, wired fiber optic technology appears to be the only cost-effective solution. 1
For over a century, standard copper cables have been used for telecommunications, but fiber optics (cylindrical glass conduit) transfer voice, video, and data 100 times faster than standard copper cables. Can be transmitted. Unfortunately, only a small portion of the capabilities of fiber optic technology are currently being realized due to limitations in opto-electronic and vice versa conversion methods.

With the invention of the erbium-doped fiber amplifier, the need for opto-electronic conversion in the network is minimized. Therefore, the signal in the optical format is maintained, and the wavelength division multiplex / demultiplex technology (WDM / WDDM) is used.
, Or simply referred to as WDM), i.e., by using a number of different wavelengths (medium bit rates at distinct different wavelengths) over the same optical fiber to achieve a large total bit rate be able to.

To enable uniform amplification over many wavelengths, it is possible to transmit more than 40 wavelengths (100 GHz or 0.8 nm wavelength spacing, each wavelength being 2.5 Gbit / s to 10 Gbit) / S bit rate). WDM systems manufactured today use separate wavelength-specific components (transmitter / multiplexer and filter / demultiplexer).

[0008] The price per wavelength of current average wavelength-averaged WDM systems is of the order of $ 60,000 for very long distance (approximately 600 km) telecommunications applications and short distance (approximately 60 km). In telecommunications applications, it is on the order of $ 25,000. WD
As the cost of deploying WDM technology becomes economical as the cost of M components decreases, WDM technology can be deployed in the metropolitan, local telephone, home fiber, and data communications markets.

[0009] Linear and curve gratings are available at many altitudes such as distributed feedback (DFB) lasers, distributed Bragg reflector (DBR) lasers, unstable cavity lasers with curve gratings, vertically focusing lasers, and filters. It is a key element of active and passive optoelectronic devices. These sophisticated devices play an important role in telephone and computing fiber optic communication systems.

Although there are many known techniques for producing the required type of grating, these techniques are typically characterized by a number of disadvantages. For example, direct write e-beam lithography has the advantages of fine pitch control and the ability to create quarter-wave or finer phase shifts and gratings of any shape. However, direct write e-beam lithography is characterized by high equipment costs and low throughput, causing potential material damage to the wafer due to vigorous electron beam bombardment. Other approaches using binary phase masks have the advantages of high throughput, fine pitch control, and the ability to create quarter-wave or finer phase shifts and arbitrary shaped gratings. However, these approaches can feature complex manufacturing procedures and are limited to grating pitches that correspond to mask pitches (eg, 200 nm).

SUMMARY OF THE INVENTION [0011] The present invention provides a single or multiple simultaneous or multiple wafers / substrates on a wafer / substrate, with or without a sharp quarter-wave shift (or a finer phase shift that changes gradually). A robust process for manufacturing a phase mask that can be used to make linear and curve gratings with submicron pitches (including continuously varying pitches). This allows for practical commercial fabrication of multi-wavelength laser diode arrays (laser chips). The present invention also provides techniques for manufacturing durable and reliable laser chips, efficiently mounting these laser chips, and interfacing these laser chips to laser driver chips. Although laser chips can be fabricated using standard semiconductor processes, embodiments of the present invention further enhance some of such processes to provide high manufacturability and laser chip reliability. .

[0012] The present invention provides for twice the required submicron pitch of linear and curve gratings (with or without phase shift regions) on commercially available π phase shift materials on quartz substrates. Use direct writing electron or ion beam lithography at pitch and wet or dry etching of π phase shifting material. Wet or dry etching of the π phase shift material can be done with a zero-order nulled π phase shifted phase mask (zero-order nulled π).
The exact π needed to create a phase-shift phase mask)
Create a phase shift. In another embodiment, the π phase shift mask writes directly on the quartz substrate and etches the quartz substrate to a very precise depth to cancel the (transmitted and diffracted) zero-order beam, Made. Thus, the present invention alleviates the critical pitch dimension when manufacturing linear and / or curved gratings with a pitch of less than 200 nm by electron or ion beam lithography.

The present invention also provides an improved ridge laser structure having metal shoulders on either side of the active region of the laser. These shoulders are formed on the insulating layer,
One shoulder is electrically connected by a contact metal to the ridge waveguide semiconductor material.

The present invention also provides an improved technique for coupling signals carrying information to a laser chip with very high fidelity. This is because very high frequencies (eg, 10G
Hz) can be achieved by designing a circuit that can carry a large number of signals without interference (known as crosstalk). According to this aspect of the invention, a metallized via hole connects a metal structure above the substrate to a backside ground plane below the substrate. In one embodiment, the metal structure is a ground line interspersed with RF / DC transmission lines on the top surface of the substrate. Metallized vias pass through the ground line. In another embodiment, the vias are RF / D
C may be arranged in pairs distributed along the transmission line, with one via in each pair
On one side of the F / DC transmission line, the other via of the pair is on the other side of the RF / DC transmission line. The metal structure in this case may be an individual wire arch above the RF / DC transmission line and extending into vias on both sides.

A further understanding of the nature and advantages of the present invention may be realized by reference to the drawings and the remainder of the specification.

DESCRIPTION OF SPECIFIC EMBODIMENTS 1.0 Overview of Distributed Feedback (DFB) Laser Structure FIG. 1A is a schematic diagram of a multi-wavelength distributed feedback (DFB) ridge laser diode array 10 according to an embodiment of the present invention. It is. The laser array 10 is sometimes called a laser chip. The laser chip 10 includes multiple ridge laser diode elements on a single substrate, and in the particular embodiment shown, 10a, 10b, 10c,
And four ridge laser diode elements shown as 10d. Each ridge laser diode element, sometimes simply referred to as a laser, is configured to emit light of different wavelengths. This wavelength is denoted as λ ₁ , λ ₂ , λ ₃ , and λ ₄ . The lasers each have an associated grating 15a to 15d, and the respective pitch of the grating determines the respective wavelength of the laser. As described below, the techniques of the present invention facilitate etching different pitch gratings on the same substrate. The number of lasers may be less or more (eg, eight as shown in FIG. 1B).

Although the laser chip 10 is shown in a particular orientation that defines what is referred to as a top and a bottom, as described below, the laser chip is preferably configured to improve heat transfer. It is mounted upside down on the module substrate.

In certain embodiments, the laser wavelength is around 1555 nm, and many current fiber optic communication modules and systems are configured for this wavelength. The wavelengths are spaced about 3.2 nm apart. This interval is about 0.5
It corresponds to a grating pitch spaced by nm. For example, 238.
Embodiments of laser chips having grating pitches of 5 nm, 239.0 nm, 239.5 nm, and 240.0 nm are 1548.82 nm,
Provides operation at wavelengths of 1552.02 nm, 1555.22 nm, and 1558.42 nm. It is also possible to have wavelengths spaced by 0.8 nm or 1.6 nm.

The ability of the present invention to produce gratings of different pitches on the same chip is, in other words, an important advantage, that is, the ability to provide a multi-wavelength DFB laser chip. Depending on the application, the chip may select and operate any one wavelength at a given time, or may operate by transmitting all wavelengths simultaneously. Note that the ability to transmit multiple wavelengths simultaneously from a single chip allows for cost savings in WDM systems.

It is further noted that the ability of the present invention to produce gratings of different pitches on the same chip also provides advantages for producing individual laser diodes. The ability to have multiple pitch gratings on the wafer before scoring the wafer into chips allows the scoring of a single wafer into multi-wavelength laser array chips or single laser chips As a result, lasers having different wavelengths are obtained from the same wafer.

Undesired optical, thermal, and electrical crosstalk between the lasers physically separates the lasers on the laser array chip by about 500 microns and creates isolation trenches 17 between adjacent lasers. By forming, it can be minimized to some extent.

FIG. 1C is an enlarged view showing one of the lasers, for example, laser 10a.
The active region 20 of the laser is formed in a body of semiconductor material. This laser
It is called a ridge laser. Because the body is formed with trenches 22 and 23 on both sides of the active region 20 and the ridge 25 over the grating 15a
Is specified. Outside the trenches 22 and 23 are two metal shoulder pairs.
7a and 27b are formed. Upper contact metal layer 30 (p + contact)
Is on the ridge, and the lower (back side) contact metal layer 32 (n + contact)
Are located on the bottom surface of the chip. The contact metal 30 continues downward, extends through the trench 22 to the outside of the trench 22, and extends over the shoulder 27a to provide a bond pad 35. This figure also schematically shows the various layers of the laser and the active area of the laser. The various layers are the n + substrate 42, the lower cladding layer 4
5, an active (quantum well) layer 47, a grating layer 50, an upper cladding layer 52, a p + contact layer 55, and the like. The grating pattern is etched in selected areas of the grating layer, with each pitch of the grating pattern defining an individual laser wavelength. The grating 15a is shown as a hatched portion of the grating layer 50.

[0023] Representative dimensions of particular embodiments are provided for illustrative purposes only, to provide context for the following detailed description. The laser chip 10 has a length (laser resonator length) of about 0.5 mm and a width of 2.0 mm, so that individual ridge laser diodes are spaced by 0.5 mm (500 microns). While these are macro-sized, the structures shown are micro-structures. For example, ridge 25 has a width of about 4 microns, trenches 22 and 23 have a width of about 30 microns each, and shoulders 27a and 27b have a width of about 20 microns each. The depth of the trench 17 is about 1.5 microns, and the thickness of the shoulder is about 2 microns.

Although the various layers of the chip extend over substantially the entire area of the chip, the grating pattern is formed on only a small area of the grating layer (
For example, a width of about 10 microns), the active area of each laser is under each ridge. The grating has a depth of about 0.05 microns and is located about 0.4 microns below the ridge and about 0.05 microns above the active layer. The thickness of the active layer itself is about 1 micron.

The following sections of the specification describe various aspects of the techniques implemented in the laser array 10. Specifically, the following description describes the manufacture and use of phase masks, the fabrication of gratings using phase masks, the manufacture of laser chips with multiple pitch gratings to support multi-wavelength operation, Includes details on providing and mounting and incorporating the laser chip into the module.

2.0 Phase Mask for Fabricating Grating 2.1 Comparison between Phase Shift Mask and Binary Intensity Mask A phase shift mask is usually called a phase mask, and a grating pattern is formed on a layer 50 of a laser chip. Used for defining. Phase masks can produce masks having a pitch that is twice the pitch of the desired grating features, thereby providing the advantage of allowing a finer grating than otherwise possible. . This can best be understood with reference to the following comparison between a standard binary intensity mask (BIM) and a phase mask. As explained below, the present invention allows only symmetric m = + 1 and m = -1 beams to interfere where the zero-order beam cancels out, and reduces the spatial frequency Use the property of a net π phase shift (based on scalar optics) that causes doubling.

FIG. 2A illustrates the structure and operation of the binary intensity mask 60 in four aligned segments. The first segment in the figure shows the mask 60. The mask 60
An opaque material region 65 such as chromium is deposited on the transparent substrate 62 including a transparent substrate 62 such as quartz. The pattern of opaque material defines the pattern that will be replicated in the layers on the semiconductor device. This pattern is characterized by a pitch or a spatial frequency that can be rephrased as a pitch.

The second segment of the figure is a plot showing the electric field of the mask 60 as a function of distance along the mask surface. As can be seen, the electric field along the direction of the mask 60 has alternating regions of maximum and zero amplitude. These areas correspond to a transparent area and an opaque area, respectively.

[0029] The third segment is a plot of the electric field on the wafer. Due to interference and other effects, the electric field on the wafer is approximately sinusoidal about a positive offset, alternating between zero and maximum amplitude at a spatial frequency equal to the spatial frequency of the mask pattern.

The fourth segment is a plot of the resulting intensity on the wafer. It can be seen that the intensity on the wafer is obtained by the square of the electric field and has the same spatial frequency as the spatial frequency of the pattern on the mask 60.

FIG. 2B illustrates the structure and operation of the phase mask 70 in four aligned corresponding segments. The mask 70 is at least partially transparent over a portion of the surface of the mask 70, but has alternating portions 72 and 7 that represent optical path differences through the mask.
5 is included. The pitch of these alternating parts is indicated by Λ. In certain embodiments, the phase shift is π radians. Therefore, the mask 70 is called a π phase shift mask. Two embodiments of the mask are described below. In one embodiment (shown below as 70P), the mask includes a substrate 77 and the region 75
Defined by a separate layer of phase shift material of predetermined thickness, one embodiment (hereinafter,
70Q), the material is monolithic quartz.

The second segment of the figure is a plot showing the photofield of the mask 70 as a function of distance along the mask surface. As can be seen, the electric field along the direction of the mask 70 alternates around zero at a spatial frequency (ie, a pitch of Λ) corresponding to the spatial frequency of the mask pattern.

[0033] The third segment is a plot of the electric field on the wafer. Due to interference and other effects, the electric field on the wafer is approximately sinusoidal and oscillates around zero at the same spatial frequency.

The fourth segment is a plot of the resulting intensity on the wafer. Since the intensity on the wafer is obtained by the square of the electric field and the electric field oscillates around zero, the intensity is twice the spatial frequency of the pattern on the mask 70 (ie,
(ピ ッ チ / 2 pitch).

2.2 Fabrication of Phase Mask Using Phase-Shift Material FIGS. 3A-3G use the phase-shift material to fabricate a zero-order zeroed π-phase-shift phase mask, designated 70P. 2 shows a manufacturing process of the first method. Blanks of such phase shift materials are commercially available. Suitable materials are
DuPont Photomasks Inc. Embedded phase i-line / 365 nm 6% transmission or 9% transmission phase shift blank, available from S.A.

FIG. 3A is a schematic top view of the phase mask 70 P. Designed in a specific embodiment for use with a two-inch wafer, this mask has a substantially opaque peripheral region 102 and a central region 105 that contains phase mask elements for exposing the grating pattern on the wafer. In this case, only one quarter of the wafer is exposed at a time. In other embodiments, the mask may be large enough to cover the entire wafer. The area containing the grating pattern is indicated at 110 and is called a grating stripe. These areas are schematically indicated by solid lines. 3 because these regions are only a few microns wide (10 microns in certain embodiments) but extend from one edge of the central region 105 to the other. Also, as described above, the grating is at the center of 1/2 mm (500 microns). This means that there are grating stripes on the order of 50, rather than a smaller number as shown, on the portion of the mask. As shown in the enlarged portion, the grating pattern of each stripe extends perpendicular to the direction of the stripe. In certain embodiments, the grating pattern is a continuous pattern of four repetitions corresponding to four wavelengths λ ₁ , λ ₂ , λ ₃ , and λ ₄ . The enlargement also shows that in a very stylized manner, the grating pattern can be made to incorporate a phase shift region, such as a λ / 4 phase shift region. The phase shift regions are schematically shown as being spaced by 0.5 mm, which corresponds to the laser cavity length (as described in detail below, one such phase shift). The region is located at the center of the resonator).

FIG. 3B is a cross-sectional view of a π phase shift blank including a quartz substrate 120 and a phase shift material layer 122 thereon. This figure is along the lines 3B-3B of FIG. 3A (it should be understood that FIG. 3A shows the final phase mask and FIG. 3B shows the initial stages of fabrication.

FIG. 3B shows a phase shift blank coated with a layer 125 of a photosensitive material (such as photoresist), wherein the photoresist is in regions 130 a-130 d
Are written directly using electron or ion beam lithography. These regions 130a to 130d are used to define the grating stripe 110 on the final phase mask. The part of FIG.
This corresponds to a width on the phase mask that is slightly larger than the width of one 4-wavelength chip on the wafer that is exposed using the phase mask. The exposure area (drawn in cross-hatching) is very exaggerated. Because these exposed areas are only about 1
It is 0 microns wide and the center-to-center spacing is about 1/2 millimeter (500 microns). Thus, this figure shows four exposure regions corresponding to the four lasers constituting the four laser chips.

FIG. 3C shows a cross-sectional view along line 3C-3C of FIG. 3B. This figure shows an exposed portion of a region 130a that defines an actual grating. These exposed parts are
130a-1, 130a-2, etc. This figure is also not shown to scale. This is because the feature seen from this angle is submicron (twice the pitch of the grating on the chip). The pitch of the exposed part is shown in FIG.
As in B, it is indicated by Λ. As described above, this pitch corresponds to a pitch of Λ / 2 on the exposed wafer.

One possible realization of this process is to reduce the surface charge of the phase shift material due to the insulating nature of the π phase shift material (on a 90 mil thick quartz substrate) at 950K.
-Layer photoresist composed of 2% to 5% PMMA of a molecular weight of 200 nm (thickness: 200 nm)
５００500 nm) and polymethyl methyl acrylate (polymethy
A single layer photoresist with a 10 nm aluminum metal overcoat on l methyl acrylate (PMMA) may be used. Or,
A tri-layer photoresist including a 200 nm 2% PMMA top layer, a 10 nm deposited germanium or silicon center layer, and a 200 nm photoresist bottom layer baked at 180 ° C. (180 ° C. baked photoresist was first (Spun on) may be deposited on a π phase shift material (on 90 mil thick quartz). The concept of a three-layer photoresist is described in Howard et al., IEEE Trans.
actions of Electron Devices ED-28 (11
1981 pp. 1378-1381.

Direct writing of patterns can be performed in multiple passes with reduced electron or ion beam intensity. The desired pattern can be written on the photoresist by multi-pass electron or ion beam lithography at 50 KV or 100 KV. To reduce non-uniformities and stitching errors during electron or ion beam writing, the full dose may be divided by multiple passes.

FIGS. 3D and 3E are cross-sectional views showing the photoresist-coated phase shift material after developing the photoresist. As can be seen, the photoresist regions exposed by the electron or ion beam have been removed by a development process, leaving bare regions 135a-135d of phase shift layer 122. These bare regions are segmented at the phase mask pitch as shown in FIG. 3E, with the individual segments shown as 135a-1, 135a-2, and so on.

In the case of a single layer PMMA, the aluminum layer can first be etched with an aluminum etching solution, then the PMMA is developed with a 1: 1 volume ratio of methyl isobutyl ketone: isopropanol, and finally, the isopropanol Rinse and dry in nitrogen.

For a three-layer resist process, PMMA is first developed with a 1: 1 volume ratio of methyl isobutyl ketone: isopropanol, rinsed with isopropanol and dried in nitrogen. Then, by etching the sample with deionized water to remove native oxide on the germanium layer, then the germanium or silicon, in pure CF ₄ plasma, a low-pressure reactive (or magnetic enhancement) to ion etching More dry etching. The hard baked photoresist at 180 ° C. is etched by low pressure reactive (or magnetically enhanced) ion etching in pure O ₂ plasma.

FIGS. 3F and 3G are cross-sectional views showing the final phase mask after the bare regions 135 a-135 d of the phase shift layer 122 have been etched and the pattern has been replicated in the phase shift material. ~ 140d are left. These bare regions are segmented at the phase mask pitch as shown in FIG.
The individual segments of 40a are designated 140a-1, 140a-2, and so on.
The etching is preferably performed by a process that etches the phase shift material to the quartz substrate but does not significantly etch the quartz substrate.

In the case of single layer PMMA, the submicron pattern on the π phase shift material can be wet etched using a dilute commercial chromium etchant.
For a three-layer resist, the π phase shift material is Cl ₂ (80%) and O ₂ (20%
3.) Etching in gas mixture plasma by medium pressure reactive ion etching (or magnetic enhancement). Final removal of the 180 ° C. baked photoresist can be performed in a pure O ₂ gas plasma by using high pressure reactive ion etching with a commercial photoresist stripper.

The phase mask is then subjected to a final surface treatment and deposition of a backside anti-reflective coating 142.

If desired, chromium may be deposited over portions of the phase mask other than the grating stripes using standard deposition and lift-off techniques. This can be easily performed after etching the grating pattern. If performed after etching, the etched grating stripe must be covered with photoresist so that the deposited chromium can be lifted off from the area of the grating stripe. When etching a grating pattern using a chromium etchant in the phase shift material etching, it is generally not appropriate to pattern the chromium by depositing, followed by photolithography and etching. This is because the chromium etchant also etches the phase shift material.

2.3 Fabrication of Phase Mask Using Direct Etching FIGS. 4A-4G illustrate fabrication steps of a second method for fabricating a zero order zeroed π phase shift phase mask. This method differs from the first method described above in that the grating pattern is etched into a quartz blank rather than into a phase shift material deposited on a quartz substrate. Quartz blanks are originally chrome plated (similar to binary photomask blanks).

FIG. 4A is a schematic top view of the phase mask 70 Q. The mask is mainly opaque (chrome coating) and grating stripes 145 are located in the central region of the mask. As with the phase mask 70P, only one quarter of the wafer is exposed at a time. Also, as in the above case, the stripes are schematically indicated by solid lines, and as shown in the enlarged portion, the grating pattern of each stripe extends perpendicularly to the direction of the stripe, and the grating pattern is:
4 is a continuous pattern of four repetitions corresponding to four wavelengths λ ₁ , λ ₂ , λ ₃ , and λ ₄ .

FIG. 4B is a schematic diagram of a portion of a chrome-plated quartz blank including a quartz plate 150 and a chrome layer 152 thereon. This figure corresponds to line 4B-4B in FIG. 4A.
(It should be understood that FIG. 4A shows the final phase mask, and FIG. 4B shows the initial stages of manufacturing). FIG. 4B shows the photoresist layer 153.
Shows a blank coated with the photoresist, where the photoresist is in areas 155a-15
Written directly using electron or ion beam lithography to expose 5d. These regions 155a to 155d are used to define the grating stripe 145 on the final phase mask. Mask 7
As in the case of 0P, the part of FIG. 4B corresponds to a width on the phase mask slightly larger than the width of one four-wavelength chip, and the exposed area (depicted by cross-hatching) is very exaggerated. 4 shows four exposure regions corresponding to four lasers formed on the final chip.

The process begins by preparing 5% PMMA (500 nm) with a molecular weight of 950 K on a 90 mil thick chrome plated quartz plate (the 90 mil thickness was chosen because the quartz plate was Because it does not bend much with time and temperature). Electron or ion beam lithography may be used to directly write edge alignment cross marks and stripe openings (10 microns wide, about 10 mm long) at selected locations on the chrome coated blank. The alignment cross mark and the stripe opening may be wet-etched using a commercially available chromium etchant. In order to obtain high-contrast alignment cross marks in the case of electron beam lithography, Cr and Au (5 nm / 100 nm) may be deposited on selected areas of the alignment marks while carefully shadow masking the stripe opening area. . The Cr and Au alignment marks can be lifted off and a chrome coated blank
Rinsed with isopropanol, and then plasma ashing using O ₂ gas, it is possible to remove any surface residues of the photoresist.

FIG. 4C is a cross-sectional view of the blank portion after the photoresist 157 has been developed and the exposed chromium has been etched in areas corresponding to the exposed areas 155a-155d of the photoresist. The chrome portion remaining between the stripe regions remains on the final phase mask.

Next, as described above with respect to the manufacture of the mask 70 P, the chromium-removed blank in the stripe region is coated with a photoresist, and a grating pattern is written on the photoresist.

Using the three-layer photoresist concept described in Howard et al., Supra,
A three-layer photoresist procedure can be prepared on a 90 mil thick quartz substrate as follows. 200 nm thinned AZ 5214E photoresist (AZ
5214E diluted in photoresist thinner is baked at 180 ° C. for 1 hour, and then 10 nm thick germanium or silicon is deposited in a high vacuum evaporation system, followed by spin-on 950K molecular weight 2% PMMA (
(Thickness: 200 nm) and baked again at 160 ° C. for 30 minutes. Electron or ion beam lithography may be used to directly write the desired pattern at twice the required actual grating pitch.

As in the above case, direct writing of the pattern is preferably performed in multiple passes with reduced electron or ionic strength. Specifically, instead of writing the grating with a complete electron or ion beam dose in one pass, multiple passes of the electron or ion beam dose (at least at 1 / (number of passes) of the full dose) (at least Write the grating in 4) to minimize field and / or subfield stitching errors in the grating. The irradiation dose may be varied from the chromium / quartz boundary to the center of the quartz to obtain a uniform grating pattern. The exposed PMMA can be developed with a 1: 1 volume ratio of methyl isobutyl ketone: isopropanol developer, finally rinsed with isopropanol and dried in nitrogen gas.

FIGS. 4D and 4E are cross-sectional views showing a photoresist-coated blank after developing the photoresist. As can be seen, the photoresist areas exposed by the electron or ion beam are removed by a development step,
The bare regions 157a to 157d of the quartz substrate 150 are left. These bare areas are
Segmented at the phase mask pitch as shown in FIG. 3E, the individual segments are denoted by 157a-1, 157a-2, etc.

FIGS. 4F and 4G are cross-sectional views showing the final phase mask after the quartz bare regions 157 a-157 d have been etched to replicate the pattern of photoresist 153, showing shallower substrate regions 160 a-160 d Is leaving. These etched regions are segmented at the phase mask pitch as shown in FIG. 4G, and the individual etched segments of etched region 160a are 16
0a-1, 160a-2, etc. The etching is preferably performed by a process of etching the quartz substrate to a depth corresponding to the π phase shift. Etched regions 160a1, etc., and alternating unetched regions of quartz material between the etched regions ultimately define the grating.

In the case of a germanium-based three-layer photoresist, the quartz plate can be briefly etched with deionized water and dried in nitrogen to remove native germanium oxide on germanium. it can. In both germanium-based and silicon-based three-layer photoresists, germanium or silicon can be etched with a low pressure reactive ion (or magnetically enhanced) etcher (etc) using CF ₄ gas plasma.
her). The underlayer of hard baked photoresist can be continuously etched in a low pressure reactive ion (or magnetically enhanced) etcher using an O ₂ gas plasma. Quartz was etched to the desired precise depth to obtain the desired π phase shift in a low pressure reactive ion etcher (or magnetically enhanced reactive ion etcher) using a CF ₄ —Ar mixture. The depth can be controlled by monitoring the etch time and profiling the etch depth of the test signature area during the etch and the emission spectra of etch gas by-products. Final removal of the 180 ° C. baked photoresist was achieved by using a commercially available photoresist stripper, high pressure reactive ion etching in pure O ₂ gas plasma, and commercially available nanostrips. can do.

The phase mask is then subjected to a final surface treatment and deposition of a backside anti-reflective coating 162.

3.0 Grating Manufacture and Possible Geometries FIG. 5A shows a phase mask 70 that can be manufactured as shown above. This phase mask 70 is vertically incident (normally inci
Dent) Wafer 16 coated with photoresist (eg, 40 nm thick photoresist) using a coherent or non-coherent light beam
3 used for exposing. This exposure and subsequent processing are for forming a grating pattern on the grating layer 50 (FIG. 1C) of the laser chip. The phase mask is in contact with, or almost in contact with, the wafer (the case of almost being in contact is clearly shown). m = 0 order diffraction beam 16
Various diffraction orders are also shown, including the 5a, m = -1st order diffracted beam 165b, and the m = + 1st order diffracted beam 165c. Due to the π phase shift, the m = 0th order diffracted beam is canceled and the primary beams 165b and 165c interfere to form an image. As described above, the nature of the phase mask is that the pattern on the wafer has a spatial frequency that is twice the spatial frequency of the pattern on the phase mask. That is, the pitch of the grating pattern on the phase mask is twice the desired / designed grating pitch. After exposure, the photoresist is developed and the grating pattern is etched into the wafer using a standard wet or dry etching process.

The advantages of using a phase mask with vertically incident radiation, in addition to achieving finer patterns, the ability to make gratings of different pitches on the same substrate, and making curve gratings Capabilities.

FIG. 5B shows four different possible grating configurations that can be made using the process according to the present invention. Linear grating 1 having segments 172 and 173 of constant pitch さ れ る separated by λ / 4 phase shift region 175
70 is shown. Embodiments of the laser chip according to the present invention include multiple linear gratings, each having a λ / 4 phase shift region, each grating having a different pitch to support multi-wavelength operation.

A curve grating 180 having constant pitch curve grating segments 182 and 183 separated by a λ / 4 phase shift region 185 is shown. Shown is a linear grating 190 having first constant pitch segments 192 and 193 indicated by Λ _small , separated by larger pitch segments 195 indicated by Λ _large . A curve grating 200 is shown having first pitch Λ _small car grating segments 202 and 203 separated by a larger pitch Λ _large car grating area 205.

FIGS. 5C and 5D show typical applications of curve gratings. As described above, the laser chip shown in FIG. 1A uses four straight gratings of different pitches, each having a λ / 4 phase shift region.
5C and 5D can be used with many different types of lasers, in which case the grating is outside the laser cavity. FIG. 5C has a laser diode 210 and a curve grating 212,
5 illustrates a vertically focusing laser diode configuration that focuses at spot 213.
FIG. 5D shows a high power unstable resonator laser diode configuration with a laser diode 215 (with curve mirrors 216a and 216b) and a pair of curve gratings 217a and 217b.

4.0 Laser Chip Manufacture 4.1 Patterning and Etching Process In current implementations, laser chip manufacture involves the use of laser diode wafers commercially available from suppliers such as EPI in Londonderry, NH. Start with purchase. Wafers may also be obtained from Semia, San Francisco, California. A commercially available laser diode wafer includes, for example, the following layers in order from the top.

P + -doped top metal contact (InGaAs) p-doped upper cladding (InP / InGaAsP) grating layer (InGaAsP) multilayer active layer (alternate quantum well and barrier layers) n-doped lower cladding (InP / InGaAsP) n + doped Substrate (InP) FIGS. 6A to 6H show a manufacturing process for manufacturing a ridge laser array. These drawings are not shown to scale, for example, thicknesses are greatly exaggerated. In certain implementations, the laser chips are fabricated on a 2 inch wafer. These wafers may be purchased with or without some or all of the layers above the grating layer. Depending on the particular wafer, the grating is etched into the grating layer (the overlying layers have been removed, if present at the outset) and the overlying layers are regrown.

The grating pattern is etched using phase mask 70 and standard photolithography. The exposure of the grating pattern using the phase mask has been described above. As described above, the exposure may be performed using coherent light or may be performed using incoherent light. At this point, the gratings are completely covered, but the exact locations of these gratings must be known in order to form a ridge laser structure over the gratings.

FIG. 6A is a schematic top view showing the portion of the laser wafer 250 where the grating indicated by 255 has been etched, and the semiconductor material 257 (eg, I
(nGaAsP / InP / InGaAs) has been regrown and the wafer has been edge-opened photolithographically and wet-etched to locate the grating. The region containing the grating pattern is called a grating stripe and is schematically indicated by a solid line. Because these areas are only a few microns (in certain embodiments, 10 microns) wide,
This is because it extends across the wafer. Also, as described above, the grating is at the center of 1/2 mm (500 microns). This means that there are grating stripes on the wafer, on the order of 100, rather than a smaller number as shown. As shown in the enlarged portion, the grating pattern of each stripe extends perpendicular to the direction of the stripe.

FIG. 6B shows the portion of the wafer after depositing an insulating layer, such as silicon nitride or silicon dioxide, on the wafer and forming alignment marks 260 by photolithography and etching of the insulating layer. The alignment mark is ×
Shown as indicia and located at various locations on the wafer. In certain embodiments, the alignment marks are placed every 10 or 20 chips. Since the active area of the laser structure occupies a small 2 mm wide portion of the chip, it is easy to place an alignment mark on the part of the chip that is removed from the active area (eg, near one of the isolation trenches). Is the thing.

FIG. 6C is a schematic sectional view showing a portion of the laser wafer 250 corresponding to a width slightly larger than the width of one laser chip. Since the wafer is not separated into individual chips, the structure whose structure will now be described extends from one edge of the chip to the other (aligned with the grating stripe). The grating stripe is shown directly below the regrown material 257.

FIG. 6D shows trenches 22 and 23 (FIG. 1C) to define a ridge waveguide.
FIG. 2B shows the portion of the wafer after etching the substrate and etching deeper between the active regions of the laser to define isolation trenches 17 (FIG. 1A). The trench is
Using a combination of reactive or magnetron enhanced reactive ion etching (methane and hydrogen gas mixture at room temperature or chlorine or argon gas mixture at 300 ° C.) and wet etching in hydrochloric acid and water at a volume ratio of 4: 1 It may be etched.

FIG. 6E shows a more localized portion of the wafer after the conformal insulating layer 270 has been deposited and then annealed to densify and reduce the stress of the insulating material. This insulating layer 270 may be made of a material such as silicon nitride, silicon dioxide, or cycloten.

FIG. 6F illustrates patterning and etching of insulating layer 270 to form ridge 2.
5 shows a more localized portion of the wafer after removal of the portion of the insulating layer above 5 exposing regions 275 of underlying semiconductor material. CF ₄ (98%) and O ₂ (2%
A) A 2 micron wide opening can be created just above a 4 micron wide ridge waveguide (using alignment marks) by reactive ion etching with a gas mixture.

Prior to upper metallization, the semiconductor surface is rinsed in a low power O ₂ plasma and buffered hydrofluoric acid and rinsed with deionized water to remove any native oxide on the semiconductor surface, And you may dry in nitrogen gas.

Similarly, to remove any native oxide on the semiconductor surface prior to the deposition of the shoulder metal and the deposition of the p-metal contact, a low power wide area argon ion beam or low energy low pressure electron cyclotron resonance ( A continuous hydrogen, nitrogen and argon plasma by ECR) may be used for a short period of time in situ in vacuum.

FIG. 6G shows a more localized portion of the wafer after metallization along the outer edges of trenches 22 and 23 to define shoulders 27a and 27b (see also FIG. 1C).

FIG. 6H shows a more localized portion of the wafer after depositing contact metal 30 covering region 275 (top of the ridge), the inner surface of trench 22 and shoulder 27a. This selective metallization is performed by photolithography and metal etching or metal lift-off according to well-known processes. At this point in the process, only the contact metal 30 that extends to the bonding metal 35 contacts the semiconductor material at the top of the ridge, but the contact metal 30 has an insulating layer 270 (FIG.
E), it is insulated from the inner surface of trench 22 by shoulders 27a and 27
It should be recognized that b rests on the insulating layer 270. As described above, the contact metal 30 can be extended so as to cover the shoulder 27b.

The shoulders 27 a and 27 b and the contact metal 30 are sequentially deposited by either electron beam evaporation or sputtering, each having a thickness of 20 nm,
60 nm and 200 nm of conventional (Ti / Pt / Au) metal may be included. This can be used as a shoulder or contact p-metal. An improved sputtered p-metal contact (Ti / TiN / Pt / A) with successive thicknesses of 20 nm, 40 nm, 40 nm, and 200 nm, respectively.
u) may be used.

A new metallization scheme can be used to increase the reliability and lifetime of laser diode devices. To prevent the gold (Au) of the contacts from diffusing into the ridge, an alternating four-layer structure of TiN and Pt layers can be used between Au and the semiconductor. This is considered to greatly improve the operating life of the laser chip.

The wafer is then thinned (wrapped and polished on the back side) to the desired dimensions. This dimension is 110 microns in one embodiment. In one embodiment, the native oxide on the back side of the very fragile wafer is removed in buffered hydrofluoric acid, rinsed very carefully with deionized water, and dried with N ₂ before metallizing the back side. Immediately, it may be placed in an electron beam evaporation apparatus or sputtering system to make a backside n-metal contact. Low power wide area argon ion beam or low energy / low pressure electron cyclotron resonance (ECR) to remove any native oxide on the semiconductor surface prior to deposition of the n-metal contact deposit
A continuous hydrogen, nitrogen and argon plasma may be used in vacuum / in situ for a very short time.

The back side n + contact metal layer 32 (FIG. 1C) has a thickness of 5 nm and 25 nm, respectively.
, 50 nm, 5 nm, 60 nm, and 200 nm Ni / Ge / Au / Ni /
It may be made of Ag / Au. This can be deposited sequentially either by electron beam evaporation or sputtering and is very reliable. Clearly more reliable other backside metallizations are 20 nm, 5 nm, 5
nm, 50 nm, 5 nm, 50 nm, 200 nm sequentially sputtered G
_{e / Au / Ni / WSi 2} / Ti / WSi 2 / Au may be metallization, which is considered to be a preferred arrangement. The backside n-metal contact was rapidly thermal alloyed at 325 ° C. in a nitrogen gas environment. Additional bonding metal (Ti / Au 50 nm / 200 nm) may be deposited for better bonding.

Next, the wafer is scribed and cut into laser bars. Each laser bar has a length of 1/2 mm (laser cavity length of the last chip), but includes a number of wafer chips and is the same width as the width of the wafer at that location. In one embodiment, the emission surface of the laser bar is then briefly cleaned with a very low power, wide area argon ion beam or continuous hydrogen, nitrogen and argon plasma by low energy and low pressure electron cyclotron resonance (ECR). However, any native oxide on both sides of the laser array was removed without causing any crystal damage to these sides.

At this point, the front and back surfaces of the laser bar are coated with an anti-reflective coating. In various embodiments, these coatings are durable dense single-layer gallium gadolinium garnet (GGG) or Sc ₂ O ₃ (scandium oxide). In the presently preferred embodiment, the multilayer Ta ₂ O ₅ (
Tantalum oxide) and Al ₂ O ₃ (aluminum oxide) dielectrics, at high deposition temperatures for the antireflective coating is less than 0.1% was deposited by ion beam accelerated electron beam evaporation or sputtering. In one example, the thicknesses of tantalum oxide and aluminum oxide were 120 nm and 136 nm, respectively. A durable, dense coating of single layer GGG or Sc ₂ O ₃ or multiple layers of Ta ₂ O ₅ and Al ₂ O ₃ can increase the reliability and life of the laser chip.

The laser bar is then scored and cut into individual laser chips.
The size of the 4-laser multi-wavelength DFB ridge laser array chip is about 2 mm x 0.5
mm (4 mm x 0.5 mm for 8 laser chips) and is susceptible to damage during processing, testing and mounting. Damage from this type of handling can cause severe yield loss during burn-in and can cause reliability problems in the field. After significant experimentation, it has been found that a shoulder metal overlayer can significantly minimize this damage and protect the active layer from damage during processing, testing and mounting.

4.2 Summary of Process The laser chip manufacturing process can be summarized as follows. The manufacturing steps selected from these manufacturing steps have been described above with respect to FIGS. 6A-6H.

1. 1. Design of multiple quantum well laser materials; 2. epitaxial growth; 3. production of a multi-pitch grating using a phase mask; 4. Regrowth on the grating; 5. Identification of the location of the grating (photolithography and etching); 6. deposition of insulator (SiN _x or SiO ₂ ); 7. Definition of SiN _x or SiO ₂ alignment marks (photolithography and etching); 8. Defining ridges and isolation trenches above the grating using SiN _x or SiO ₂ alignment marks (photolithography and etching); 9. deposition of low stress, dense conformal SiN _x or SiO ₂ or cyclothene; Contact openings SiN _x or SiO ₂ or Cyclotene® on top of the ridge (photolithography and etching), 11. 11. definition of shoulder metal (photolithography and etching or lift-off); 12. Define secure contact metal on top of ridge (photolithography and etching or lift-off); 13. Au plating to improve p-metal step coverage; 14. lapping / thinning and polishing of the substrate; 15. Surface treatment of thinned substrate; 16. backside metallization, Metal alloying, 18. 18. Scribing the wafer to make a laser bar; Coating the surface of the laser bar to improve performance and reliability, and 20. Mark the laser bar to make a laser chip.

4.3 Specific Laser Structure Specific Quantum Well (MQW) Separated Confinement Heterostructure (SCH)
The InP / InGaAsP material structure is fully optimized (composition and thickness) for DFB ridge laser array applications. In a buried heterostructure laser, the active layer has a width of about 1 micron, whereas the active layer of a ridge laser has a width of 3 microns. Slight changes to the active layer of the ridge laser do not significantly change the wavelength accuracy of WDM applications. In the case of a ridge laser, the etching is stopped above the active layer, and in the case of a buried heterostructure, the active layer is completely etched. Therefore, ridge lasers tend to provide better reliability and higher wavelength yield. However, note that the undesirable threshold current of the ridge laser is higher than that of the buried heterostructure. The quantum well has a 1% compressive strain,
The barrier is 1% tensile strain. This distortion compensation provides higher reliability and improves the life of the laser array die device. The thickness and composition of the separate confinement layers are also optimized for optimal grating coupling, higher bit rate devices, and optimal far-field imaging of laser array devices for coupling to single mode optical fibers. Be transformed into

Specific implementations of multiple quantum well (MQW) isolated confinement heterostructure (SCH) laser chips are shown in Tables 1-4 below.

[0090]

[Table 1]

[0091]

[Table 2]

[0092]

[Table 3]

[0093]

[Table 4] The main difference between the two designs shown above is in the thickness of the grating layers (single layer 5 in design # 1 and layers 6 and 7 in design # 2). Unlike the combined thickness of design # 2 (0.17 microns), the thinner layer of design # 1 (0.10 micron)
Microns) tend to provide faster device speeds, but tend to couple less output light into the fiber.

5.0 Laser Chip Module 5.1 Outline of Module FIGS. 7A and 7B are an upper cross-sectional view and a side cross-sectional view showing the laser chip 10 incorporated in the mounted module 300, respectively. It is drawn to scale. A preferred package is a high speed multi-fiber port "butterfly style" high speed ceramic package. The specific package shown is 50
It has pins spaced by mills. A suitable package is Kyocera Amer, located in Aliso Viejo, California.
ica, Inc. And can be obtained from a number of private vendors.

In the present embodiment, the laser driver chip (not shown) is outside the module, and the RF modulation signal of the laser driver chip superimposed on the DC bias by the bias tee (not shown) RF / realized as metal trace
It is transmitted to the laser via the DC transmission line 305. In one embodiment, the modulation current is on the order of 65 ma, while the DC bias current is on the order of 25 ma.
This implementation illustrates a simplified RF / DC shielding scheme, where the RF / DC transmission lines 305 are bounded by ground lines 310, which themselves also contact the backside through the substrate. Implemented as traces on substrate 307 with via holes extending to ground 315. The transmission and ground lines may be of constant width, or one or more may be tapered, as shown in FIG. 7C, for optimal impedance matching and minimal return loss. May be.

Additional elements within the module include a thermistor pair 320a and 320b located on either side of the laser chip 10, a PIN photodiode 325, and a high heat removal thermoelectric cooler (TEC) 330 mounted on the back side of the substrate. ,including.

The thermistor is coupled to a temperature sensing circuit (not shown), which provides a signal to a temperature control circuit (not shown), which provides an appropriate voltage to TEC 330. Thus, a desired detection temperature for stable operation is maintained. The PIN photodiode is a rear surface monitor to provide a signal representative of the average light power emitted through the rear surface. In this embodiment, there is a λ / 4 phase shift region on the grating, the front and back surfaces are very transparent, and the grating provides a feedback mechanism. Thus, the light power through the front and back surfaces must be the same, and the back surface measurement provides a measure of the light power emitted through the front surface.

The substrate 307 is preferably a high efficiency heat spreader, such as AlN, which is then bonded to another high efficiency heat spreader, such as diamond, and then on the TEC 330 for accurate temperature control. Bonding. The thin film substrate incorporating the microwave transmission line may be the same heat spreader,
There may be a suitable separate substrate (embedding the microwave transmission lines) bonded on a common heat spreader. In this approach, it is possible to place the laser driver chip on a separate printed circuit board outside the laser module package.

[0099] Optical fibers 340a-d that receive light output from the individual lasers of laser chip 10 and carry the light out of the module through fiber tube pairs 342a and 342b are also shown in the figure. Each tube contains a fiber pair. Once out of the module, the fiber may be coupled to external optics, such as a wavelength multiplexer.

FIG. 7C shows another configuration for passing the fiber out of the package.
It is a partial top view of the module shown by 00 '. In this implementation, which represents the current implementation, a single tube 345 containing all the fibers is used instead of the tube pairs 342a and 342b shown in FIGS. 7A and 7B.

FIG. 8A is a top plan view showing another realization of the laser chip module and its external optical connection. In this figure, the sizes of the various elements are exaggerated for clarity. Elements that correspond to elements of the realization of FIGS. 7A and 7B are denoted by the same reference numerals. The implementation shown in this figure uses a more advanced isolation scheme for the RF / DC transmission line, here designated by reference numeral 350.

Note that the laser chip is mounted face down on the substrate 307. The electrode structure under each laser location on the laser chip 10 includes bonding electrodes 355 and 360. Bonding electrode 355 communicates with ground plane 315 by vias (not separately shown). The back side of the laser chip 10 is wire bonded to the bonding electrode 355 to provide the back side ground. The bonding electrode 360 includes a large portion to which the bonding metal 35 of the laser chip is bonded and a small portion to be wire-bonded to the end of the active electrode of the RF / DC transmission line 350.

5.2 Microwave Shielding In order to modulate the laser at a high bit rate, it is preferable to match the impedance of the laser to the laser driver chip. The RF / DC signal line is matched to the impedance of the laser driver and terminated with a suitable thin film resistor. Further, as noted above, it is desirable to provide some electrical isolation between the various RF / DC signal lines to avoid crosstalk between different signal channels driving individual lasers. In the embodiment shown in FIG. 7A, isolation is provided by inserting a ground line between the RF / DC transmission lines 305. Figure 8 shows a more aggressive separation scheme.
A, where the metal transmission line on the substrate 307 has a grounded air bridge U-shaped wire that provides a continuum of arches that actually serves as a partial coaxial shield.

FIG. 8B is a partial detail view showing metal traces 380 running along substrate 307 having metalized via holes 382a and 382b on each side. The hole pairs are repeated along the length of the signal trace 380 to provide shielding.

FIG. 8C is a further refinement of this where the area of the substrate below the metal traces has been etched to form a channel filled with dielectric 385,
A dielectric film 387 extends slightly outside the edge of the dielectric fill channel 385.

The microwave substrate material has a high frequency (5 GHz to 20 GHz) and a high power (1 GHz).
(Watts to 10 Watts) applications are thermally conductive and low loss. The laser chip uses gold-tin solder (for example, a typical layer thickness of 40/60/2000/40).
/ 100/40/3000 nm Ti / Pt / Au / Ti / Pt / TiN / Ti
/ AuSn) using low stress metallization on the microwave substrate. Microwave simulations up to 10 GHz show that the crosstalk is about -35 dB.

5.3 External Optical Interface In a typical optical scheme, the output of each laser is coupled to one of the fibers 340a-d. Couple the output of the laser to the fiber using a microlens array because single-mode fiber pigtails to the laser array are much more difficult than multimode fiber pigtails to the laser array due to optical mode mismatch I do. Thus, the output of each laser is collected and collimated by the collimating lens 370, and the focusing lens 372 focuses the collimated light onto the fiber. The figure further shows fibers 340a-d fused to the respective input ports of wavelength multiplexer 375. The output port of the multiplexer 375 is shown as being melt bonded to the composite isolation block to reduce back reflection to the laser chip. The separation block includes three lens pairs on both sides of the optical isolator 395.
It is shown as having 90 and 392. Light is focused by lens 392 to the end of a segment 397 of the fiber. Segment 397 is connected to a standard fiber connector 390.

FIG. 8D is a partial perspective view showing another external configuration, and an in-line optical isolator 395 is used instead of the composite separation block shown in FIG. 8A.

5.4 Configuration with Laser Driver Inside Module FIG. 9 is an exploded perspective view of another configuration of the laser chip module, indicated at 300 ″. This figure is also not shown to scale. Elements that correspond to elements of the implementation of Figures 7A, 7B, and 8A are designated by the same reference numerals.
In this implementation, the laser driver chip, indicated at 410, is located very close to the laser chip 10 (less than 2 mm) in the module.

This arrangement has the advantage that the laser module is very compact. However, the laser driver chip can generate a large amount of heat, so in this close proximity (2 mm) to the laser chip, despite the use of the TEC 330 for accurate laser temperature control. Heat generated from the laser driver can affect the thermal and optical parameters of the multi-wavelength laser chip. To solve this problem, separate thermal paths for the laser chip and laser driver were used. Accordingly, the laser driver chip is mounted on a separate heat spreader 420, which is mounted on the substrate 307 by a set of thermal isolation elements 425.

5.5 Laser Driver Multi-wavelength DFB laser arrays have a common substrate (InP) for lasers.
It is therefore difficult to drive individual lasers due to this common cathode configuration. This can be solved by using a commercially available laser driver circuit with an external current mirror circuit. This external current mirror circuit serves as a current source and allows the cathode of the laser diode to be at ground potential.

FIG. 10A shows a commercially available laser driver circuit 4 with a bias circuit 455 connected to one of the lasers, for example, the laser 10a, in the laser chip.
50 is shown. In this implementation, the bias circuit 455 is a current source, and a PNP drive transistor configured as a current mirror serves as this current source.
The current source supplies a maximum operating current to the laser. When the laser driver output transistor is on, the current to the laser is reduced by shunting through this transistor. This causes the optical signal to be inverted with respect to the optical signal normally obtained from the laser driver circuit. Therefore, the off-state laser current is the difference between the current of the current source and the current of the laser driver. The above approach represents a cost-effective and efficient way of driving a laser diode fabricated on an n + substrate.

FIG. 10B shows another approach in which the bias circuit shown at 455 ′ includes an inductor and a resistor. This approach is appropriate where active components are to be avoided.

An existing feedback control input to the laser driver circuit can be used, as well as an appropriately selected bias value. This circuit not only provides excellent driving capability, but also allows the use of existing drivers in this application, if desired.

6.0 System Application The multi-wavelength laser chip of the present invention offers many advantages in WDM system applications. As mentioned above, individual laser chips may have individual wavelengths tuned as a function of temperature. However, due to the expense of wavelength monitoring, monitoring a subset of wavelengths in a WDM system may be spared. If the individual lasers of a multi-wavelength laser chip are manufactured under the same conditions and operate under tightly coupled conditions, monitoring the wavelength of only one of the lasers of the multi-wavelength chip can be achieved by monitoring the individual lasers. It is likely to be more appropriate and reliable than monitoring a subset of the wavelengths.

FIG. 11 shows an embodiment of a multi-wavelength laser array module in a metropolitan telephone network, and FIG. 12 shows an embodiment of a multi-wavelength laser array module in a local area network. These are only representative of the possible system deployment of the multi-wavelength laser chip of the present invention.

[0117] 7.0 (herein, incorporated by reference) references the United States Patent Document: Patent Number year author assignee US 4,517,280 1985 Okamoto et al Sumitomo US 4,748,132 1988 Fukuzawa et al Hitachi US 4,846,552 1989 Vieldkamp et al. US Air Force US 5,413,884 1995 Koch et al. AT & T Foreign Patent Literature (herein incorporated by reference): 323845410/1991 Japan Non-Patent Publications (herein incorporated by reference): M. Okai et al., "Novel method to fabricat."
e correlation for a 1 / 4-shifted dist
ribbed feedback laser using a grati
ng photo mask ”, Applied Physics Lette
r 55 (5); 415-417.

[0118] 2. C. E. FIG. Zah et al., “1.5 mm compressive stra
ined multiquantum well 20-wavelength
distributed feedback laser arrays ",
Electronics Letters 28, 23 April 1992
Pp. 824-826.

[0119] 3. D. Tennant et al., "Characterization of n.
ear-field holography gratings mask f
or optoelectronics fabricated by element
ctron beam lithography ", Journal of V
ac. Technology B 10, November / December
1992; 2530-2535.

[0120] 4. G. FIG. Pakulski et al., "Fused silica mask fo
r printing uniform and phase adjust
d gratings for distributed feedback
lasers ", Applied Physics Letter 62 (3)
, 18 January 1993, pp. 222-224.

[0120] 5. Howard et al., IEEE Transactions of Elec.
tron Devices ED-28 (11) 1981, pp. 1378-1
381.

8.0 Conclusion In conclusion, it can be seen that the present invention provides a sophisticated technique for reducing the manufacturing costs of multi-wavelength semiconductor laser chips and modules. The present invention provides these advantages generally within known semiconductor processing techniques. The use of a phase mask with perpendicular illumination provides great flexibility in grating construction while allowing very fine features to be created.

While the above description is a complete description of particular embodiments of the present invention, various modifications, alternative constructions, and equivalents may be used. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.

[Brief description of the drawings]

FIG. 1A shows a multi-wavelength distributed feedback (DFB) ridge laser array according to a four laser embodiment of the present invention.

FIG. 1B shows an eight laser embodiment.

FIG. 1C is a more detailed view of one of the DFB ridge lasers in the array.

FIG. 2A shows the structure and operation of a binary intensity mask.

FIG. 2B shows the structure and operation of a π phase shift phase mask.

FIG. 3A shows a manufacturing step of a first method of manufacturing a π phase shift phase mask.

FIG. 3B shows a manufacturing step of a first method for manufacturing a π-phase shift phase mask.

FIG. 3C shows a manufacturing step of a first method for manufacturing a π-phase shift phase mask.

FIG. 3D shows a manufacturing step of a first method of manufacturing a π-phase shift phase mask.

FIG. 3E shows a manufacturing step of a first method for manufacturing a π-phase shift phase mask.

FIG. 3F shows a manufacturing step of a first method of manufacturing a π phase shift phase mask.

FIG. 3G shows a manufacturing step of a first method for manufacturing a π-phase shift phase mask.

FIG. 4A shows a manufacturing step of a second method for manufacturing a π-phase shift phase mask.

FIG. 4B shows a manufacturing step of a second method for manufacturing a π-phase shift phase mask.

FIG. 4C shows a manufacturing step of a second method for manufacturing a π-phase shift phase mask.

FIG. 4D shows a manufacturing step of a second method for manufacturing a π-phase shift phase mask.

FIG. 4E shows a manufacturing step of a second method for manufacturing a π-phase shift phase mask.

FIG. 4F shows a manufacturing step of a second method for manufacturing a π-phase shift phase mask.

FIG. 4G shows a manufacturing step of a second method for manufacturing a π-phase shift phase mask.

FIG. 5A illustrates the use of a π-phase shifted phase mask to expose a substrate.

FIG. 5B shows constant pitch and variable pitch linear and curve gratings that can be fabricated using a π phase shift phase mask.

FIG. 5C shows an application of a curve grating.

FIG. 5D shows an application of a curve grating.

FIG. 6A shows a manufacturing step of a laser chip manufacturing method.

FIG. 6B shows a manufacturing step of the laser chip manufacturing method.

FIG. 6C shows a manufacturing step of the laser chip manufacturing method.

FIG. 6D shows a manufacturing step of the laser chip manufacturing method.

FIG. 6E shows a manufacturing step of the laser chip manufacturing method.

FIG. 6F shows a manufacturing step of the laser chip manufacturing method.

FIG. 6G shows a manufacturing step of the laser chip manufacturing method.

FIG. 6H shows a manufacturing step of the laser chip manufacturing method.

FIG. 7A is a top sectional view of a laser chip module.

FIG. 7B is a side sectional view of the laser chip module.

FIG. 7C shows a tapered transmission line.

FIG. 7D is a partial top view showing another fiber tube configuration.

FIG. 8A is a top plan view showing an additional realization of a laser chip module.

FIG. 8B is a detailed view of an implementation of RF / DC transmission line separation.

FIG. 8C is a detailed diagram of an implementation of RF / DC transmission line separation.

FIG. 8D is a partial top plan view illustrating another external light separation scheme.

FIG. 9 is an exploded perspective view showing another embodiment of the laser chip module.

FIG. 10A is a schematic circuit diagram showing a laser driving system.

FIG. 10B shows another scheme for electrically driving a laser array.

FIG. 11 illustrates an embodiment of a multi-wavelength laser array module in a metropolitan telephone network.

FIG. 12 illustrates an embodiment of a multi-wavelength laser array module in a local area network.

[Procedure amendment]

[Submission date] May 19, 2000 (2000.5.19)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G03F 7/40 521 H01L 21/302 B (31) Priority claim number 09 / 031,496 (32) Priority date February 26, 1998 (Feb. 26, 1998) (33) Priority Claimed States United States (US) (81) Designated States EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), CA, JP, USF terms (reference) 2H095 BB03 BB09 BB10 2H096 AA25 AA28 EA06 EA08 EA23 HA23 2H097 AA03 CA11 CA16 LA10 LA17 5F004 BA04 BA11 BA13 BA14 DA00 DA01 DA04 DA23 DA24 DA25 DA26 DB19 DB22 EB04 5F073 AA22 AA45 AA64 AA74 AA77 AB06 BA02 CA07 CA12 CB22 DA25

Claims (50)

[Claims] 1. A method for forming a phase mask for use with light of a specific wavelength, comprising: providing a substrate having a phase shift material layer thereon; and coating the phase shift material layer with a resist material. Patterning the resist material using electron beam or ion beam lithography to define a sub-micron pitch mask grating pattern; etching the exposed phase shift material to expose a substrate material; Removing the resist material to reveal regions of phase shift material that alternate with regions of exposed substrate material according to the mask grating pattern. 2. The phase-shifting material layer, wherein the phase of the specific wavelength light passing through the substrate and a given region of the phase-shifting material passes through an adjacent region of the exposed substrate. The method according to claim 1, wherein the phase of the light of a specific wavelength is shifted by 180 degrees. 3. The method according to claim 1, wherein the resist material has a multilayer structure. 4. The method of claim 1, wherein said mask grating pattern comprises a plurality of mask grating pitches. 5. The method of claim 4, wherein the plurality of mask grating pitches are in discrete regions of the phase mask. 6. The method of claim 1, wherein said mask grating pattern includes a phase shift corresponding to half of said mask grating pitch. 7. The method of claim 1, wherein said mask grating pattern comprises at least one curve grating pattern or at least one grating of continuously varying pitch. 8. The method of claim 1, wherein the patterning step is performed using multiple passes at partial doses to reduce subfield and field stitching errors. 9. The method of claim 1, wherein the etching step comprises performing a submicron anisotropic reactive ion (magnetron enhanced) etch of the exposed phase shift material using a gas mixture comprising chlorine and oxygen. Item 1. The method according to Item 1. 10. The gas mixture according to claim 1, wherein said gas mixture comprises from 80% to 90% chlorine and from 10% to 2%.
10. The method of claim 9, comprising 0% oxygen. 11. The resist material includes germanium, and the patterning step removes native germanium oxide using deionized water, and then uses carbon tetrafluoride gas to form an isotropic reactive ion of germanium. The method of claim 1, comprising performing an etch. 12. The method of claim 1, wherein said resist material comprises silicon, and wherein said patterning step comprises performing isotropic reactive ion etching of silicon using carbon tetrafluoride gas. 13. The method of claim 1, wherein said patterning step comprises etching said resist material using oxygen gas. 14. The method of claim 1, wherein said sub-micron pitch is less than 400 nm. 15. A method for forming a phase mask for use with light of a specific wavelength, comprising: providing a substrate; coating the substrate with a resist material; and using electron beam or ion beam lithography. Patterning the resist material to define a sub-micron pitch mask grating pattern; etching the exposed substrate to a specific depth; removing the resist material and following the mask grating pattern Revealing regions of the etched substrate that alternate with regions of the substrate material that have not been etched, wherein the specific depth passes through a given region of the etched substrate. Phase of light at a particular wavelength passes through an adjacent region of the substrate that has not been etched. The depth is 180 degrees out of phase. 16. The method according to claim 15, wherein the resist material has a multilayer structure. 17. The method of claim 15, wherein said mask grating pattern includes a plurality of mask grating pitches. 18. The method of claim 17, wherein the plurality of mask grating pitches are in discrete regions of the phase mask. 19. The method of claim 15, wherein said mask grating pattern includes a phase shift corresponding to half of said mask grating pitch. 20. The method of claim 15, wherein said mask grating pattern comprises at least one curve grating pattern. 21. The method of claim 15, wherein the patterning step is performed using multiple passes at a partial dose to reduce subfield and field stitching errors. 22. The method of claim 15, wherein said etching step comprises reactive ion etching using a gas mixture comprising carbon tetrafluoride and argon. 23. The method of claim 15, wherein said gas mixture comprises 95% to 98% carbon tetrafluoride and 2% to 5% argon. 24. A method of fabricating a desired device grating structure in a semiconductor optical device, the device grating structure having features characterized by one or more desired pitch values, the method comprising: Providing a phase mask having a corresponding mask grating structure having features corresponding to the desired device grating structure, the features being characterized by one or more pitch values, wherein each pitch of the mask grating structure is provided. The value is twice the corresponding pitch value of the desired device grating structure, wherein the features of the mask grating structure are defined by alternating regions having alternating first and second optical thicknesses; Providing a substrate on which at least a portion of the semiconductor device is formed, wherein the substrate is covered with a photoresist material. Depositing the phase mask close to or in contact with the substrate; and irradiating the phase mask with vertically incident light of a specific wavelength to expose the photoresist on the substrate. And wherein the particular wavelength comprises a phase of light of the particular wavelength passing through one of the alternating regions of the phase mask and an adjacent region of the alternating region of the phase mask. Wherein the wavelength of the light passing therethrough is such that the wavelength deviates by 180 degrees, and the light impinging on the photoresist is characterized by an intensity distribution having a pitch value that is half of the corresponding pitch value of the mask grating feature; Corresponding to the desired device grating structure, further comprising: developing the photoresist; and etching the substrate to provide the desired device grating structure on the substrate. The, way. 25. The phase mask feature of claim 24, wherein the phase mask features are defined by alternating regions of (a) a phase shift material on the substrate material and (b) the substrate material without the phase shift material. the method of. 26. The phase mask feature is defined by etched areas of the mask material that alternate with unetched areas of the mask material.
A method according to claim 24. 27. Each of the desired device grating structures having a pitch value of 20
25. The method of claim 24, wherein the distance is less than 0 nm. 28. The light of claim 2, wherein the vertically incident light is coherent.
4. The method according to 4. 29. The method of claim 24, wherein the normally incident light is incoherent. 30. A high power unstable resonator laser comprising a curve grating manufactured by the method of claim 24 in combination with a laser diode having a curved surface. 31. A vertically focused laser for emitting light into a remote optical fiber, the laser comprising a curve grating manufactured in accordance with the method of claim 24 in combination with a laser diode. 32. A method of fabricating a semiconductor laser diode chip having a semiconductor substrate and a multilayer laser structure formed on the substrate, wherein the improvement comprises using a plasma enhanced CVD process to reduce the stress and density of the low hydrogen. Producing a silicon nitride layer in a content. 33. A method of manufacturing a semiconductor laser diode chip having a semiconductor substrate and a multilayer laser structure formed on the substrate, wherein the improvement comprises the step of forming an organic cyclotene layer as an insulating layer. . 34. A method for establishing a reliable metal content in a p-doped semiconductor, comprising sequentially depositing layers of titanium, titanium nitride, platinum, and gold.
Method. 35. A method for establishing a reliable metal content in an n-doped semiconductor material, comprising sequentially depositing layers of nickel, germanium, gold, nickel, silver, and gold. 36. A method for establishing a reliable metal content in an n-doped semiconductor material, comprising sequentially depositing layers of germanium, gold, nickel, tungsten silicide, titanium, and gold. . 37. In the manufacture of a semiconductor laser having at least one light-transmitting surface, native oxide on said surface is removed using a low-power wide-area argon ion beam or using low-energy low-pressure electron cyclotron resonance. An improvement comprising removing and producing a continuous hydrogen, nitrogen and argon plasma. 38. A laser diode chip, comprising: a semiconductor substrate; and a multilayer laser structure formed on the substrate, wherein the laser structure defines first and second ridge waveguides therebetween. Wherein the ridge waveguide extends along the direction of light propagation and is formed on the outer surface at a location adjacent to the trench, and the ridge waveguide is defined by the trench. A laser diode chip further comprising first and second metal shoulders separated from the ridge waveguide, wherein the shoulder extends over the top surface to protect the ridge waveguide. 39. The laser structure includes a grating disposed below the ridge waveguide, wherein the grating is disposed in a plane parallel to the upper surface and extends in a direction perpendicular to the light propagation direction. 39. The method of claim 38, wherein
4. A laser diode chip according to item 1. 40. The laser diode chip according to claim 39, wherein the laser grating structure includes a phase shift region corresponding to a half of a grating pitch. 41. Another laser structure formed on said substrate, said another laser structure comprising another ridge waveguide and another ridge waveguide disposed below said another ridge waveguide. 40. The laser diode chip of claim 39, comprising: a grating; and wherein the another grating has a different pitch than the first mentioned grating. 42. An anti-reflective coating for a laser diode surface comprising Ta ₂ O ₅ (tantalum oxide) and Al ₂ O ₃ (aluminum oxide). 43. A laser chip module, comprising: a housing, the housing having a plurality of pins for transmitting signals from outside the housing to the inside of the housing, and a dielectric substrate attached to the housing. Further comprising: the substrate having a top surface;
A laser chip having a metallized lower surface, mounted on the upper surface of the substrate, and first and second conductive signal lines on the upper surface of the substrate, wherein the signal line comprises a specific The substrate extends from the first and second input pins to a respective location on or near the laser chip, the substrate having a metallized via hole electrically connected to the metallized lower surface. The via holes are formed such that each of the signal lines has a plurality of via holes on both sides, and at least some of the via holes are disposed between the signal lines. The laser chip module further comprising a metal structure forming a pattern, disposed on the substrate, and electrically connected to the metallized lower surface by the via hole. 44. The laser chip module according to claim 43, wherein the transmission line has a constant width. 45. The laser chip module according to claim 43, wherein said metal structure comprises a metallized trace on said substrate, said trace contacting said via hole. 46. The laser chip module according to claim 44, wherein the metallized trace has a constant width. 47. The laser chip module according to claim 44, wherein at least one of said metallized traces is tapered. 48. The pattern of via holes includes a pair of via holes distributed along each of the signal lines, and wherein the metal structure includes a pair of via holes on one side of the signal lines, wherein 5. A wire arch which extends to each via hole on the other side.
4. The laser chip module according to 3. 49. The laser chip module according to claim 43, wherein the number of laser diodes is eight or more. 50. A network comprising nodes connected by fiber optic links, wherein at least one link is terminated at a node having a WDM device, wherein in an improvement, a terminal device is optically coupled to the WDM device; A network comprising a multi-wavelength laser module having a multi-wavelength ridge laser diode array chip for providing independently modulated light at a plurality of wavelengths.