JP2953449B2 - Optical semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device having a diffraction grating inside a semiconductor and a method of manufacturing the same, and more particularly, to a distributed feedback laser diode (DFB-L) having a diffraction grating inside the semiconductor.
D).

[0002]

2. Description of the Related Art The present invention is a technique widely applied to an optical semiconductor device having a diffraction grating inside a semiconductor.
The prior art and the present invention will be described using a distributed feedback semiconductor laser. Distributed feedback semiconductor lasers that oscillate in a single-axis mode have been widely used for optical fiber communication. However, distributed feedback semiconductor lasers used in digital optical fiber communications require both higher single-axis mode and higher optical output due to the need to transmit large amounts of information over long distances. The analog distributed feedback semiconductor laser used is required to have both lower intermodulation distortion characteristics and higher optical output.

A general distributed feedback semiconductor laser currently in practical use forms a uniform diffraction grating below or above an active layer and embeds it with a different composition to form a periodic refractive index in a waveguide. , The threshold gain difference between the modes is obtained. In order to obtain high single-axis mode characteristics, it is common to use a diffraction grating having a so-called λ / 4 shift structure in which the phase of the diffraction grating is shifted by π inside the resonator. In order to obtain high light output while maintaining high single-axis mode, it is necessary to control the phase of the diffraction grating at both end faces (for example, IEEE JOURNAL QUANTUM ELECTRONICS.
Vol. QE-22, No. 7 july 1986 pp. 1042-1051).

For analog applications, a uniform diffraction grating is often used to obtain a higher light output, and a front end face is coated with a non-reflective film and a rear end face is coated with a highly reflective multilayer film.
In this case, it is known that the light intensity distribution in the axial direction, which greatly affects the threshold gain difference and the intermodulation distortion characteristics, depends extremely strongly on the phase of the diffraction grating on the rear end face (for example, see Japanese Patent Application Laid-Open No. 64456). That is, the characteristics such as the threshold gain difference of the oscillation mode, the linearity and threshold of the IL curve, and the slope efficiency depend strongly on the end face phase of the diffraction grating. Therefore, in such an optical semiconductor device, controlling the phase of the end face of the diffraction grating is an important problem.

Next, a method of manufacturing a conventional DFB-LD will be described. In the case of λ / 4 shift DFB-LD, n
-A marker indicating a λ / 4 shift position is formed on the InP substrate by photolithography and etching. Marker width is 5 μm
And the depth is about 3 μm. Then, a phase shift film is formed in accordance with the marker, and a diffraction grating is formed using interference exposure and wet etching.

Next, metal organic chemical vapor deposition (MOVPE)
For example, n-InGaAsP guide layer, non-doped In
A GaAsP-based MOW active layer and a p-InP cladding layer are formed. Next, a waveguide having an active layer width of 1.5 μm is formed by photolithography and wet etching, and then p-InP and n-InP
Is grown, and finally the whole is p-InP
Buried growth with p-InGaAs as a contact layer
grow s.

To form an electrode on this wafer, λ / 4
It is necessary to transfer the shift position to the wafer surface. λ / 4
This is because if the shift position is not set at an accurate position in the center of the chip, the single-mode property is deteriorated. Therefore, the substrate is etched by selective etching to expose the λ / 4 shift position marker, and this marker is aligned to form a reference marker indicating the λ / 4 shift position on the wafer surface. Subsequent high-speed mesa formation, contact window formation,
An electrode forming process such as patterning of the electrode metal is performed using the reference markers on the wafer surface.

After the electrode is formed, the wafer is cleaved into a bar after being damaged at the cleavage position at the edge of the wafer so that the λ / 4 shift position is located at the center of the chip based on the reference marker. In this case, the cleavage position is determined only with respect to the phase shift position, so that the phase of the diffraction grating on the cleavage plane becomes completely random. Subsequently, an anti-reflection coat is applied to the end face of each bar, and pelletized to form one λ / 4 shift DF.
A B-LD is manufactured.

In the case of a uniform diffraction grating, the diffraction grating is formed directly on the substrate by interference exposure and wet etching without providing a marker. Subsequent crystal growth is the same as the λ / 4 shift, electrode formation is performed completely independently of the phase of the diffraction grating, and cleavage is performed after recognizing the electrode pattern and damaging the cleavage position at the edge of the wafer. Become a bar. Then, a non-reflective coat and a high-reflective coat are applied to the end face of each bar, and pelletized to produce one DFB-LD. A conventional DFB-LD is manufactured as described above,
Despite the importance of controlling the phase of the grating end face, λ
The phase of the diffraction grating on the cleavage plane becomes completely random regardless of whether it has a / 4 shift diffraction grating or a uniform diffraction grating.

[0010]

As described above, the conventional optical semiconductor device having a diffraction grating inside a semiconductor has a problem that the phase at the end surface of the diffraction grating is not taken into consideration and is random. As described above, since the phase at the end face of the diffraction grating is random, for example, despite having a strong influence on the characteristics of the DFB-LD, the production yield does not increase.
Problems such as a difference in threshold gain between the main mode and the sub mode cannot be obtained, uniformity of characteristics cannot be obtained, and linearity of the IL curve cannot be controlled. Therefore, it is necessary to control the phase at the end face of the diffraction grating. For example, an electron beam (EB)
Even if a marker indicating the phase of the diffraction grating is formed by the exposure method, it is almost impossible to control the end face phase by using the marker to cut and cleave. The reason is that the pitch of the diffraction grating of the DFB laser used for ordinary optical communication is about 0.2 to 0.24 μm, and in order to control the phase of the diffraction grating with an accuracy of π / 2, a 0.05 μm marker is transferred. Accuracy and cleavage position accuracy are required, which is difficult in practice.

The present invention has been made to solve such a problem, and an object of the present invention is to provide an optical semiconductor device in which the phase of a diffraction grating at an end face is controlled to a desired phase, and a method of manufacturing the same.

[0012]

SUMMARY OF THE INVENTION An optical semiconductor device according to the present invention is a semiconductor device having a diffraction grating inside a semiconductor and selecting a wavelength by using its transmission characteristic or reflection characteristic. A wafer on which a plurality of optical semiconductor elements are formed is provided with a cleavage V-groove in which the phase of the diffraction grating at the end face of the optical semiconductor element is determined by adjusting the width of the wafer.

In an optical semiconductor device having a diffraction grating inside a semiconductor and selecting a wavelength using its transmission characteristics or reflection characteristics, a plurality of distributed feedback semiconductor lasers are formed as the optical semiconductor device by being cleaved. The wafer is provided with a cleavage V-groove in which the phase of the diffraction grating on the end face of the distributed feedback semiconductor laser is determined by adjusting the width of the wafer.

The width of the cleavage V-groove is adjusted based on the width and repetition number of the electron beam exposure pattern on the resist that defines the diffraction grating, and the resist is exposed to the electron beam and formed on the resist. It is characterized by being performed.

Further, the cleavage V-groove is provided for each optical semiconductor element on the wafer on which the plurality of optical semiconductor elements are formed.

Further, the cleavage V-groove is provided for each of a plurality of optical semiconductor elements on the wafer on which the plurality of optical semiconductor elements are formed.

In the method of manufacturing an optical semiconductor device according to the present invention, a diffraction grating pattern is exposed on a resist by an electron beam exposure method to select a wavelength in a semiconductor using its transmission characteristic or reflection characteristic. In the method of manufacturing an optical semiconductor element in which a grating is formed, at least in the step of exposing the diffraction grating pattern on a resist of a wafer on which a plurality of the optical semiconductor elements are formed, based on the pattern width and the number of repetitions. A step of exposing the cleavage V-groove whose width is adjusted to the resist is provided.

A distributed feedback semiconductor laser in which a diffraction grating pattern is formed on a resist by exposing a diffraction grating pattern on a resist by an electron beam exposure method, and a diffraction grating for selecting a wavelength using its transmission characteristics or reflection characteristics is formed inside the semiconductor. In the method of manufacturing an optical semiconductor device, at least, in the step of exposing the diffraction grating pattern on a resist of a wafer on which the plurality of distributed feedback semiconductor lasers are formed, based on the width and the number of repetitions of the pattern. A step of exposing the cleavage V-groove whose width is adjusted to the resist is provided.

The optical semiconductor device and the method of manufacturing the same according to the present invention can control the phase of the diffraction grating at the end face of the optical semiconductor device formed by cleavage by employing the above-described configuration.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of the present invention will be described. FIG. 1 shows the phase of the diffraction grating (FIG. 1A) and the bottom of the cleavage V-groove (FIG. 1) for explaining the operation principle of the present invention.
FIG. 3B is a diagram illustrating a relationship with (b)), where 101 is a diffraction grating,
102 denotes a cleavage V-groove, and 51 denotes a SiO ₂ dielectric film. In the present invention, the pattern of the cleavage V-groove is exposed using the EB exposure method in the same step as the exposure of the pattern of the diffraction grating. At this time, EB is adjusted according to the pattern of the diffraction grating.
In this case, when the dimension width of the pattern of the cleavage V-groove is determined to be a length obtained by adding an even multiple of the mask width to an odd multiple of the pass-through width of the diffraction grating pattern, for example,
As shown by the solid line in FIG. 1, the bottom of the formed cleavage V-groove can be matched with the valley of the diffraction grating. When the dimensional width of the cleavage V-groove is set to, for example, a length obtained by adding an odd multiple of the mask width to an even multiple of the pass-through width of the diffraction grating pattern, FIG.
The bottom of the cleavage V-groove can coincide with the peak of the diffraction grating as shown by the wavy line.

Therefore, when forming the pattern of the cleavage V-groove,
If the point at which the B exposure is started is determined with reference to the position of the diffraction grating pattern, and the width to be exposed is determined and the EB exposure is performed,
With the determined width, the phase of the diffraction grating at the end face of the cleaved bar can be set to a desired phase. The present invention is to obtain an optical semiconductor device in which the phase of the diffraction grating at the end face is set to a desired phase by using this principle.

Embodiment 1 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows Embodiment 1 of the present invention.
FIG. 7 is a diagram illustrating a part of the semiconductor substrate 1 on which a diffraction grating 101 and a cleavage V-groove 102 have been formed by EB exposure and wet etching. A cross pattern 201 shown in the drawing indicates an EB marker, and a region surrounded by a dotted line indicates one element. In addition, FIG.
(F) is a diagram showing a process of forming the diffraction grating 101 and the V-groove 102 in the AA ′ and BB ′ cross sections of FIG. 2, respectively.

As shown in FIG. 3, a semiconductor substrate 1 is covered with a dielectric thin film 51, an EB resist 52 is applied thereon, and a pattern of a diffraction grating and a pattern of a V-groove for cleavage are formed by EB exposure. Exposure and development are performed in a positional relationship as shown in FIG.
That is, as described above, the point at which EB exposure is started in this step is determined based on the position of the diffraction grating pattern,
In addition, the width to be exposed is determined so that the phase of the diffraction grating on the cleavage end face becomes a desired phase (whether a peak or a valley or between the peaks), and the determined width (for example, the width determined to be a valley) is exposed and developed. .

Next, this resist pattern is transferred to the dielectric thin film 51 (FIG. 2B), and then wet etching is performed to form a part of the diffraction grating and V-groove (FIG. 2C). .
Then, the whole is covered with a resist 53 and patterned so that only the V-groove is exposed (FIG. 2D). Next, a V-groove is formed completely by performing wet etching (FIG. 2E).
By removing the resist and the dielectric thin film, it is possible to obtain a diffraction grating and a V-groove in which the trough of the diffraction grating coincides with the bottom of the V-groove (FIG. 2 (f)).

Embodiment 1 Hereinafter, the present invention will be described using a λ / 4 shift D
First Embodiment A case in which the present invention is applied to an FB-LD will be described with reference to FIGS. FIGS. 4A to 4D are diagrams illustrating a λ / 4 shift DFB-LD. A diffraction grating 101 and a cleavage V-groove 102 are provided on an n-InP substrate 1 and λ /
The 4 shift position 103 is located at the center of the element, the bottom of the V-groove coincides with the valley of the diffraction grating, and the diffraction grating at the end face is a valley. Assuming that the phase of the diffraction grating at the center of the element is 0, the phase of this end face is shifted by π.

On this diffraction grating, a guide layer 2 made of InGaAsP, an MQW active layer 3, and a p-InP clad layer 4 are formed. Except for the active layer waveguide, p-InP
Embedded in the block layer 5 and the n-InP block layer 6,
The whole is covered with a p-InP buried layer 7 and a p-InGaAs contact layer 8. The active layer waveguide section has a mesa 9
The SiO ₂ film 10 electrically separates the other portions of the chip from each other, thereby reducing the element capacitance. In addition, the p-side electrode of the current injection electrode 11 is patterned so that the element capacitance is also reduced.

Next, a λ / 4 shift DFB-LD shown in FIG.
A method of manufacturing the device will be described. First, as shown in FIG. 5A, a marker 201 is formed on a 100 n-InP substrate 1 at a position 202 ′ parallel to a (011) plane 202 by a contact exposure method and dry etching. This marker 201 has a length
70μm, 5μm thick, 2μm deep cross pattern, 300μ
They are arranged at m pitches (Fig. 5 (b)). This marker 201
Is a marker at the time of EB exposure.

Next, the whole is covered with SiO ₂ and an EB resist 52 is applied (not shown). Next, at EB exposure,
The pattern of the / 4 shift diffraction grating and the pattern for the V groove are exposed and developed in a positional relationship as shown in FIG. That is, assuming that the exposure positions for the diffraction grating are numbered in order from the λ / 4 shift position as 1, 2, 3,..., For example, the exposure for the V-groove is started at the 733rd position.
If the exposure is performed up to the 747th position, the length becomes the sum of an odd multiple (× 15) of the aperture width of the diffraction grating pattern and an even multiple (× 14) of the mask width, and the bottom of the V-groove is a valley of the diffraction grating. Will match. For example, the pitch of the diffraction grating is 2027 °, and the width of forming the diffraction grating is 10 μm.
On the other hand, one V-groove has a width of about 3 μm and a length of 160 μm.

Next, the pattern of this resist was changed to SiO ₂ 5
2 (see FIG. 2B) and wet etching is performed to form a part of the diffraction grating 101 and the V groove 102 (FIG. 2).
(C)). Then, the whole is covered with a resist 53 and patterned so that only the V-groove portion is exposed (see FIG. 2D). Next, a V-groove is formed completely by wet etching (see FIG. 2 (e)), the resist and the dielectric thin film are removed, and the diffraction grating and the V-shape whose valleys coincide with the bottom of the V-groove are formed.
A groove is obtained (see FIG. 2 (f)). Then, a waveguide including an active layer is directly formed by a selective vapor deposition method.

FIGS. 7A to 7H are views showing the process of forming the active portion and the V-groove in the cross section taken along the line CC 'and the line DD' in FIG. The entire substrate on which the diffraction grating and the V-groove are formed as described above is covered with SiO ₂ , and a pair of SiO ₂ stripe masks 21 are formed in the [011] direction immediately above the diffraction grating 101, and the V-groove portion 102 is formed. Patterning is performed with the coating (FIG. 6A). The opening width 31 of the SiO ₂ stripe mask is, for example, 1.5 μm, and the mask width is 5 μm.
m. The SiO ₂ covering the V-groove is 5 μm
With a margin of Next, a waveguide layer having a strained quantum well as an active layer is formed in the opening portion 31 by using a metal organic chemical vapor deposition method. In order to control the height of the diffraction grating, the temperature is increased by using AsH ₃ together with PH _3. I do.

Then, n-InGaAs having a wavelength composition of 1.05 μm
After growing the sP guide layer 2 (thickness 90 nm, concentration 1 × 10 ¹⁸ cm ⁻³ ), the wavelength composition 1.27 μm separated by the InGaAsP barrier layer (thickness 10 nm, non-doped) having the wavelength composition 1.13 μm.
An MQW active layer 3 in which seven quantum well layers (non-doped, 5 nm thick) in which 1% compressive strain is introduced into InGaAsP having a thickness of m and a p-InP cladding layer 4 (thickness 0.2 μm, concentration 7)
× 10 ¹⁷ cm ⁻³ ) to form a waveguide (FIG. 6).
(B)). Naturally, crystal growth does not occur in the V groove,
The V-groove remains preserved.

Next, the whole is again covered with SiO ₂ 22 (FIG. 6C). By utilizing the fact that the film thickness of SiO ₂ is different slant portion and the flat part, as only the inclined surface portion is exposed SiO ₂
The film is etched, and the waveguide portion and the V-groove portion are resisted.
(FIG. 6D). Then, other SiO ₂ is removed (FIG. 6E). At this time, if the adhesion between the resist and the semiconductor is sufficient, the S
It is possible to leave the iO ₂ mask.

Next, p-In was applied to portions other than immediately above the waveguide portion and the V-groove portion.
P blocking layer 5 (thickness 0.6 μm, concentration 3 × 10 ¹⁷ cm ⁻³ ) and i-InP layer 6 (thickness 0.3 mm, non-doped) n-In
Embedding is performed with a P block layer 7 (thickness: 0.6 μm, concentration: 1 × 10 ¹⁸ cm ⁻³ ) (FIG. 6F). Next, resist 2 is applied only to the V groove.
4 (FIG. 6 (g)), the SiO ₂ mask immediately above the waveguide layer is removed, and the whole is buried with a p-InP buried layer 7 (thickness 5 μm, concentration 7 × 10 ¹⁷ cm ⁻³ ). InGaAs cap layer 8 (1 μm thick, concentration 3 × 10
¹⁸ cm ^-3 ) (FIG. 6 (h)).

Thus, an epitaxial wafer having a cleavage V-groove having phase information of a diffraction grating can be manufactured. The following electrode process may be performed in the same manner as in the related art. However, if the overhang formed in the V-groove during the selective growth is a concern, the overhang may be etched off first. Then, by cleaving using the V-groove portion as a guide, a bar in which the phase of the end face of the diffraction grating is controlled to a desired phase can be obtained. Then, an AR coat of SiN (reflectance of 1% or less) is applied to both end surfaces to complete a λ / 4 shift DFB-LD.

When the optical output characteristics of the completed λ / 4 shift DFB-LD were measured, a threshold value of 8 mA at room temperature and a lobe efficiency of 0.35 W / A or more were obtained, and the front-to-back output ratio was 1.3.
Double mode suppression ratio (SMSR) at optical output 5mW is 48d
B or more. S with slope efficiency of 0.33W / A or more
The ratio of the high-efficiency, high single-axis mode element having an MSR of 45 dB or more is the same as that of the conventional λ / 4 shift DF having a random end face phase
B increased from 40% to 80%.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a view for explaining the second embodiment of the present invention, and shows a part of the semiconductor substrate 1 on which the diffraction grating 101 and the cleavage V-groove 102 have been formed by EB exposure and wet etching. Diffraction grating 1
01, having the cleavage V-groove 102 as in the first embodiment, but the cleavage V-groove 102 is formed not on each element but on a part of the wafer to improve the EB exposure throughput. It has special features.

When cleavage is performed using the V-groove 102 as a guide, if each element has a V-groove as in the first embodiment,
It is sufficient if the length of the groove is about 100 μm. However, as shown in FIG. 8, when cleaving from a partially formed V-groove as a starting point, the length of the V-groove must be 300 μm or more, preferably 450 μm or more. Is desirable. In consideration of the fact that the portion where the V-shaped groove 102 is formed cannot be used as an element, the thickness is preferably 600 μm or less.

Embodiment 2 FIG. FIG. 8 shows a part of the semiconductor substrate 1 on which the diffraction grating 101 and the cleavage V-groove 102 have been formed by EB exposure and wet etching. The manufacturing method is the same as that of the first embodiment. The V-shaped groove 102 is formed over the area of two elements, and has a length of 560 μm. The ratio of the portion where the V groove is formed is 2 for 40 elements.
It is equivalent to an element. By forming the V-groove in this way, EB
Exposure throughput can be improved. Compared with the first embodiment, the area for forming the V groove is about 1/10 or less.

In the above embodiments and examples, the case where the bottom of the V-groove coincides with the valley of the diffraction grating has been described. However, the present invention sets the phase of the diffraction grating at the end face to a desired phase. This does not mean that the bottom of the V-groove must necessarily coincide with the peak or valley of the diffraction grating. In the description of the above-described embodiment, the waveguide including the active layer and the buried growth are performed by the MOVE method. However, the growth method is not limited as long as the crystal can be grown while protecting the V-groove.

[0040]

As described above, the optical semiconductor device and the method of manufacturing the same according to the present invention have an effect that the phase of the end face of the optical semiconductor device having the diffraction grating inside the semiconductor can be set to a desired phase. . Therefore, when the present invention is applied to a DFB-LD, characteristics such as a threshold gain difference of an oscillation mode, a linearity and a threshold of an IL curve, and a slope efficiency which strongly depend on an end face phase of the diffraction grating are controlled by controlling a phase of the diffraction grating. This makes it possible to obtain a DFB-LD having superior single-axis mode characteristics and intermodulation distortion characteristics as compared with the conventional DFB-LD, and to improve the production yield. .

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention.

FIG. 2 is a diagram for explaining Embodiment 1 of the present invention.

FIG. 3 is a diagram for describing Embodiment 1 of the present invention.

FIG. 4 is a diagram for explaining the first embodiment of the present invention.

FIG. 5 is a diagram for explaining the first embodiment of the present invention.

FIG. 6 is a diagram for explaining Example 1 of the present invention.

FIG. 7 is a diagram for explaining the first embodiment of the present invention.

FIG. 8 is a diagram for explaining Embodiment 2 and Example 2 of the present invention.

[Explanation of symbols]

Reference Signs List 1 compound semiconductor substrate (100 n-InP substrate) 2 n-InGaAsP guide layer 3 MQW layer 4 p-InP clad layer 5 p-InP block layer 6 n-InP block layer 7 p-InP buried layer 8 p-InGaAs contact layer Reference Signs List 9 Mesa groove for high-speed response 10, 21, 22 SiO ₂ film 11 Electrode 15 Diffraction grating 23, 52, 52 Resist 51 Dielectric thin film (SiO ₂ film) 101 Diffraction grating 102 V groove 201 Marker for EB 202 011 surface

Claims (7)

(57) [Claims] 1. An optical semiconductor device having a diffraction grating inside a semiconductor and selecting a wavelength by using its transmission characteristic or reflection characteristic. An optical semiconductor device comprising: a cleavage V-groove for determining a phase of the diffraction grating at an end face of the optical semiconductor device by adjusting dimensions. 2. An optical semiconductor device having a diffraction grating inside a semiconductor and selecting a wavelength using its transmission characteristics or reflection characteristics, wherein a plurality of distributed feedback semiconductor lasers are cleaved and formed as the optical semiconductor device. An optical semiconductor device, comprising: a wafer having a cleavage V-groove in which the phase of the diffraction grating at the end face of the distributed feedback semiconductor laser is determined by adjusting the width of the wafer. 3. The cleavage V-groove whose width is adjusted based on the width and the number of repetitions of an electron beam exposure pattern on a resist that defines the diffraction grating, is exposed to an electron beam on the resist. The optical semiconductor device according to claim 1, wherein the optical semiconductor device is formed. 4. The semiconductor device according to claim 1, wherein said cleavage V-groove is provided for each optical semiconductor element on said wafer on which a plurality of said optical semiconductor elements are formed. The optical semiconductor device according to any one of the above. 5. The semiconductor device according to claim 1, wherein the cleavage V-groove is provided for each of the plurality of optical semiconductor elements on the wafer on which the plurality of optical semiconductor elements are formed. The optical semiconductor device according to any one of the above. 6. An optical semiconductor device in which a diffraction grating for selecting a wavelength using a transmission characteristic or a reflection characteristic thereof is formed in a semiconductor by exposing a diffraction grating pattern on a resist by an electron beam exposure method. In the manufacturing method, at least in the step of exposing the diffraction grating pattern on a resist of a wafer on which a plurality of the optical semiconductor elements are formed, the cleavage V whose lateral width is adjusted based on the width and the number of repetitions of the pattern. A method for manufacturing an optical semiconductor device, comprising a step of exposing a groove on the resist. 7. A distributed feedback semiconductor in which a diffraction grating pattern is formed on a resist by exposing a diffraction grating pattern onto a resist by an electron beam exposure method, and a diffraction grating for selecting a wavelength is formed in the semiconductor using its transmission characteristics or reflection characteristics. In the method for manufacturing an optical semiconductor device for manufacturing a laser, at least a step of exposing the diffraction grating pattern on a resist of a wafer on which a plurality of the distributed feedback semiconductor lasers are formed, based on a width of the pattern and the number of repetitions. Exposing the cleavage V-groove having its width dimension adjusted on the resist.