JP2001507846A - ロックを伴うキャッシュ置換方法 - Google Patents

ロックを伴うキャッシュ置換方法

Info

Publication number
JP2001507846A
JP2001507846A JP52577499A JP52577499A JP2001507846A JP 2001507846 A JP2001507846 A JP 2001507846A JP 52577499 A JP52577499 A JP 52577499A JP 52577499 A JP52577499 A JP 52577499A JP 2001507846 A JP2001507846 A JP 2001507846A
Authority
JP
Japan
Prior art keywords
cache
memory
lock
cache memory
locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP52577499A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001507846A5 (enExample
Inventor
エイノ ジェイコブス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of JP2001507846A publication Critical patent/JP2001507846A/ja
Publication of JP2001507846A5 publication Critical patent/JP2001507846A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1466—Key-lock mechanism
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP52577499A 1997-10-31 1998-09-24 ロックを伴うキャッシュ置換方法 Pending JP2001507846A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/961,965 1997-10-31
US08/961,965 US6047358A (en) 1997-10-31 1997-10-31 Computer system, cache memory and process for cache entry replacement with selective locking of elements in different ways and groups
PCT/IB1998/001484 WO1999023567A1 (en) 1997-10-31 1998-09-24 Cache replacement policy with locking

Publications (2)

Publication Number Publication Date
JP2001507846A true JP2001507846A (ja) 2001-06-12
JP2001507846A5 JP2001507846A5 (enExample) 2006-02-02

Family

ID=25505244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52577499A Pending JP2001507846A (ja) 1997-10-31 1998-09-24 ロックを伴うキャッシュ置換方法

Country Status (6)

Country Link
US (1) US6047358A (enExample)
EP (1) EP0950223B1 (enExample)
JP (1) JP2001507846A (enExample)
KR (1) KR100637610B1 (enExample)
DE (1) DE69840960D1 (enExample)
WO (1) WO1999023567A1 (enExample)

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JP2005044341A (ja) * 2003-07-24 2005-02-17 Samsung Electronics Co Ltd 書き込み防止可能なバッファメモリを有するメモリ装置及びそれを含む情報処理システム
JP2006338371A (ja) * 2005-06-02 2006-12-14 Toshiba Corp メモリシステム

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US6591347B2 (en) * 1998-10-09 2003-07-08 National Semiconductor Corporation Dynamic replacement technique in a shared cache
US6801207B1 (en) 1998-10-09 2004-10-05 Advanced Micro Devices, Inc. Multimedia processor employing a shared CPU-graphics cache
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US6405287B1 (en) * 1999-11-17 2002-06-11 Hewlett-Packard Company Cache line replacement using cache status to bias way selection
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JP4603753B2 (ja) * 2000-02-01 2010-12-22 シラス ロジック、インコーポレイテッド キャッシュされた情報を安全にする方法および回路
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US6986003B1 (en) 2001-08-09 2006-01-10 Unisys Corporation Method for processing communal locks
US6922744B1 (en) * 2001-08-09 2005-07-26 Unisys Corporation Communal lock processing system for multiprocessor computer system
US6823426B2 (en) * 2001-12-20 2004-11-23 Intel Corporation System and method of data replacement in cache ways
US7073030B2 (en) * 2002-05-22 2006-07-04 International Business Machines Corporation Method and apparatus providing non level one information caching using prefetch to increase a hit ratio
US6816952B1 (en) 2002-05-31 2004-11-09 Unisys Corporation Lock management system and method for use in a data processing system
US6912623B2 (en) * 2002-06-04 2005-06-28 Sandbridge Technologies, Inc. Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy
US6901483B2 (en) * 2002-10-24 2005-05-31 International Business Machines Corporation Prioritizing and locking removed and subsequently reloaded cache lines
GB0400569D0 (en) * 2004-01-12 2004-02-11 Lightfoot Solutions Ltd System & methodology for identifying statistically signifcant events in monitored process
US9268831B2 (en) * 2004-01-12 2016-02-23 Lightfoot Solutions Group Limited System and method for extracting user selected data from a database
US7321954B2 (en) * 2004-08-11 2008-01-22 International Business Machines Corporation Method for software controllable dynamically lockable cache line replacement system
KR100617875B1 (ko) 2004-10-28 2006-09-13 장성태 다중 캐쉬 구조의 다중 프로세서 시스템 및 그 원격캐쉬의 교체 방법
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US7523260B2 (en) 2005-12-22 2009-04-21 International Business Machines Corporation Propagating data using mirrored lock caches
US7461210B1 (en) * 2006-04-14 2008-12-02 Tilera Corporation Managing set associative cache memory according to entry type
US20080147989A1 (en) * 2006-12-14 2008-06-19 Arm Limited Lockdown control of a multi-way set associative cache memory
US8438003B2 (en) * 2007-04-12 2013-05-07 Cadence Design Systems, Inc. Methods for improved simulation of integrated circuit designs
US8060880B2 (en) * 2007-05-04 2011-11-15 Microsoft Corporation System using backward inter-procedural analysis for determining alternative coarser grained lock when finer grained locks exceeding threshold
US8180969B2 (en) * 2008-01-15 2012-05-15 Freescale Semiconductor, Inc. Cache using pseudo least recently used (PLRU) cache replacement with locking
US20100057926A1 (en) * 2008-08-28 2010-03-04 Sycamore Networks, Inc. Digital custom data content injection mechanism for a content delivery network
US9208104B2 (en) 2008-08-28 2015-12-08 Citrix Systems, Inc. Content replacement and refresh policy implementation for a content distribution network
US8271610B2 (en) 2008-08-28 2012-09-18 Sycamore Networks, Inc. Distributed content caching solution for a mobile wireless network
KR101355892B1 (ko) * 2013-01-15 2014-01-28 한밭대학교 산학협력단 실시간 단일 메모리 동시 입출력을 위한 영상데이터 처리방법
JP6209689B2 (ja) * 2014-12-14 2017-10-04 ヴィア アライアンス セミコンダクター カンパニー リミテッド モードに応じてウェイの全部又はサブセットに選択的に割り当てるように動的に構成可能であるマルチモード・セット・アソシエイティブ・キャッシュ・メモリ
EP3066571B1 (en) 2014-12-14 2018-06-13 VIA Alliance Semiconductor Co., Ltd. Cache memory budgeted by ways on memory access type
JP6207765B2 (ja) 2014-12-14 2017-10-04 ヴィア アライアンス セミコンダクター カンパニー リミテッド モードに応じてセットの１つ又は複数を選択的に選択するように動的に構成可能であるマルチモード・セット・アソシエイティブ・キャッシュ・メモリ
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JP2005044341A (ja) * 2003-07-24 2005-02-17 Samsung Electronics Co Ltd 書き込み防止可能なバッファメモリを有するメモリ装置及びそれを含む情報処理システム
JP2006338371A (ja) * 2005-06-02 2006-12-14 Toshiba Corp メモリシステム

Also Published As

Publication number Publication date
EP0950223A1 (en) 1999-10-20
US6047358A (en) 2000-04-04
KR20000069836A (ko) 2000-11-25
WO1999023567A1 (en) 1999-05-14
EP0950223B1 (en) 2009-07-08
DE69840960D1 (de) 2009-08-20
KR100637610B1 (ko) 2006-10-24

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