JP2001501381A - Method for forming an adhesive bond between an electronic device and a support substrate - Google Patents

Method for forming an adhesive bond between an electronic device and a support substrate

Info

Publication number
JP2001501381A
JP2001501381A JP11507956A JP50795699A JP2001501381A JP 2001501381 A JP2001501381 A JP 2001501381A JP 11507956 A JP11507956 A JP 11507956A JP 50795699 A JP50795699 A JP 50795699A JP 2001501381 A JP2001501381 A JP 2001501381A
Authority
JP
Japan
Prior art keywords
support substrate
adhesive
opening
gap
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11507956A
Other languages
Japanese (ja)
Inventor
コッホ マルクス
シュツ ライナー
ジャン ホンクァン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of JP2001501381A publication Critical patent/JP2001501381A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10189—Non-printed connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】 電子素子と支持基板との間の接着結合を形成するための方法であって、片面側に多量の接触エレメントを備えた、少なくとも１つの素子特にフリップ・チップ素子を、前記接触エレメントに対応するように整列された、支持基板の接触面と導電接続し、ディスペンス装置によって、毛細管現象に従って接触エレメントの周囲を流れる接着剤を、素子と支持基板との間のギャップ内に侵入させる方法において、接着結合を形成するために必要な時間を短縮するために、支持基板に被着された素子の下側で、支持基板を貫通する少なくとも１つの開口を設け、毛細管現象に従って流動する接着剤を、これが少なくとも１つの開口と接触エレメントとの間で広がるように、支持基板上に施す。 (57) Abstract: A method for forming an adhesive bond between an electronic device and a supporting substrate, comprising the steps of: providing at least one device, in particular a flip-chip device, having a large number of contact elements on one side. A conductive connection is made with the contact surface of the support substrate, which is aligned to correspond to the contact element, and the dispensing device penetrates the adhesive flowing around the contact element according to capillary action into the gap between the element and the support substrate. In the method, at least one opening penetrating the support substrate is provided below the element attached to the support substrate to reduce the time required to form an adhesive bond, and flows according to capillary action. An adhesive is applied on the support substrate such that it spreads between the at least one opening and the contact element.

Description

【発明の詳細な説明】 電子素子と支持基板との間の接着結合を形成するための方法 本発明は、請求項１の上位概念に記載した、電子素子と支持基板との間の接着 結合を形成するための方法に関する。 電子素子を、いわゆるフリップ・チップ技術で、支持基板上に被着することは 既に公知である。フリップ・チップ技術で被着された素子は、はんだ付け、等方 性で導電性の接着又は熱圧着結合のための接触エレメントを有している。フリッ プ・チップはんだ付けにおいては、チップの接続面側に、はんだ盛り(Loetoecke r)よりも小さく構成された多数の接触エレメント例えば「ソルダーバンプ；sold er bumps」を備え、次いで、この接続面側を下になるようにチップをひっくり返 して、接触面を備えた支持基板上に載せる。この際に、支持基板上の接触面の配 置が、チップ上のはんだ盛りのパターンに相当している。次いで、はんだ盛りを リフローはんだ付け法で、支持基板上の接触面にはんだ付けする。フリップチッ プ法によれば、チップと電子回路を備えた支持基板とのワイヤレスの多数の導電 接続を、有利な形式で１回の作業段階で形成することができる。チップ（シリコ ン；Silicium）及び支持基 板（プリント基板材料）の異なる膨張率に基づいて、いわゆる「アンダーフィル プロセス;Undefillprozess（下方注入工程）」で、接着剤をチップと支持基板と の間に注入し、これによってはんだ付け箇所が、温度変化負荷の影響を受けない ようにする必要がある。このために、特に毛細管現象に従って流動性である接着 剤が、ディスペンス装置によって、少なくとも１つのチップ縁部に沿って支持基 板上に施されるようになっている。毛細管現象に基づいて接着剤が、チップと基 板との間の狭いギャップ内に流入する。接着剤は硬化後に、機械的な応力を吸収 して、それによってはんだ結合部を保護し、はんだ結合部の耐用年数を高める。 その他のフリップ・フリップ技術によれば、チップに接触エレメントを備え、 この接触エレメントに、等方性(isotrop)で導電性の接着剤を施し、次いで支持 基板の接触面上に接着するようになっている。この技術においても、チップと支 持基板との電気的な結合部を形成した後で、アンダーフィルプロセスによって接 着剤を施し、この接着剤が、等方性で導電性の接着結合部を保護するようになっ ている。 さらにまた、チップに接触エレメントを備え、このチップを熱圧着結合法で支 持基板の接触面上に被着する、フリップ・チップ技術が公知である。この方法に おいても、結合部の十分に機械的な形状安定性を保証するために、アンダーフィ ルプロセスが必要である。 空気が閉じこめられないようにするために、上記の方法においては、接着剤を １つ又は２つのチップ縁部に施し、この際に、接着剤は、チップの反対側までつ まりチップの下側まで広がるようにすることが知られている。すべての接着剤量 を１つのチップ縁部に塗布することはできないので、最終的にすべての接触エレ メントが接着剤によって取り囲まれるまで、前記塗布作業が何回も繰り返さなけ ればならない。このような方法は、例えばSolid State Technology,１９９７年 ４月、Alec．J．Babiarzによる論文“Key process controls for underfilling flip chips（アンダーフィリングによるフリップチップのためのキープロセスコ ントロール）”に記載されている。この場合、各塗布作業段階の間に常に接着剤 の流れ時間に基づいて休止時間を入れる必要があり、またチップと基板との間の 全ギャップが最終的に充填されるまで、新たな接着剤を施さなければならない、 という欠点がある。従って特に大きいチップにおいては、退屈な待機時間を考慮 しなければならない。長い待機時間によって、製造時間は著しく長くなり、これ によって製造コストが再び著しく高くなる。 発明の利点 これに対して、請求項１の特徴部に記載した特徴を有する、本発明による、電 子素子と支持基板との間の接着結合を形成するための方法は、接着結合を形成す るために必要な全接着剤量を１回の作業段階でディスペンス装置によって施すこ とができるという利点を有している。これによって接着剤の流れ時間に基づく待 機時間は有利な形式で避けられ、これによって、結合部を形成するための製造コ ストは著しく低減される。本発明による方法は、特に３ｃｍまでの縁部長さを有 する大きいチップにおいて接着結合を形成するために非常に有利である。 本発明の別の有利な構成及び変化実施例は、従属請求項に記載した手段によっ て可能である。 毛細管現象に従って流動性の接着剤を、素子の外周を巡って延びる閉じた経路 に沿って、素子の直ぐ近くに施し、次いで素子の縁部に位置するすべての接触エ レメントの周囲に接着が流れるようにすれば、特に有利である。次いで、閉じた 接着剤先端部が、素子と支持基板との間のギャップの毛細管現象によって、少な くとも１つの開口まで広がり、この際に、ギャップ内に存在する空気が少なくと も１つの開口を通って外部に押し出されるようになっている。このような方法に よって、素子の接触エレメントと、支持基板の接触面との間のはんだ付け結合部 、接着結合部又はボンディング結合部を最適に保護することができる。 接着剤を塗布する前に、支持基板を、被着した素子を下にしてひっくり返し、 接着剤を、ディスペンス装置によって支持基板の後側で、支持基板に設けられた 開口上に塗布すれば、特に簡単である。接着剤は毛細管現象に従って、開口内に 及び、素子と支持基板との間のギャップ内に侵入し、次いで、素子の周囲に配置 された接触エレメントの周囲に流れ込む。 さらに、素子の下側で中央に配置された孔の形状の開口を設ければ、有利であ る。何故ならば、こうすれば接着剤は、素子の下側で、中央の孔と接触エレメン トとの間で特に均一に広がるからである。 接着剤は、素子を備えた側に塗布され、従って接着剤はまず接触エレメントの 周囲を取り囲むように流れ込み、次いで少なくとも１つの開口まで広がるので、 接着剤先端部は、一部が開口に達するが、他の部分はまだ開口に達しない。すべ ての空気がギャプから押し出される前に、接着剤が開口内に早期に侵入すること は、支持基板の、素子を装着した側にコーティングを設けることによって避けら れる。このコーティングは、開口の縁部を取り囲んで施され、接着剤によって濡 らしにくい材料より成っている。このコーティングは、有利には銅又は金より成 る金属被覆である。 コーティングの代わりに、支持基板の、素子を備えた側で、開口の縁部を取り 囲むように、段付けされた段状の突起を設けても良い。この突起は、金属被覆の ように、接着剤が開口内に早期に侵入することを妨げる。 図面 本発明の１実施例が図面に示されていて、以下に詳しく説明されている。 第１図から第３図には、基板とフリップ・チップ素子との接着結合を形成する ための、本発明による方法の第１実施例が示されており、第４図のａから第４図 のｄには、第１図から第３図に示された実施例における、接着剤先端部の広がり の種々異なる段階が示されている。 第５図及び第６図には、基板とフリップ・チップ素子との接着結合を形成する ための、本発明による方法の第２実施例が示されている。 実施例の説明 第１図から第３図に示された、素子と支持基板との間の接着結合を形成するた めの本発明の方法の第１実施例が示されている。例えばＦＲ４基板から成るプリ ント基板、セラミック支持体、チップ支持体・素子又はその他の適して基板であ ってよい、支持基板１上に、フリップ・チップ素子２が公知の形式ではんだ付け される。ケーシングで取り囲まれていないフリップ・チップの代わりに、例えば マルチ・チップモジュール内に収容されたフリップ・チップ素子、又はいわゆる チップ・スケールパッケージを、支持基板上に被着してもよい。さらにまた、１ つ以上の素子を同じ形式で支持基板上に被着することも勿論可能である。図示の 実施例は、簡略化のために１つの素子だけに限定した 。第２図に示されているように、素子２は、その接続側で、周方向に分配して配 置された複数の接触エレメント３を備えており、この接触エレメント３ははんだ 盛り（いわゆる”solder bumps“）として構成されている。フリップ・チップ技 術で、はんだ盛り３を備えた素子２が、支持基板１の接触面４の対応するラスタ 上に載せられ、リフローはんだ付けステーションで支持基板１にはんだ付けされ る。リフローはんだ付け後に、素子２は、支持基板１の接触面４と、第２図に示 された形式で電気的に接続される。フリップ・チップ素子が、接触エレメント３ 上に塗布された等方性(isotrop)で導電性の接着剤によって接触面４に接着され るか、又は熱圧縮法で接触面上に溶接される。接触エレメント３と接触面４との 間の電気的な接続を形成するために、素子２と基板１との間に、狭い約３０μｍ から大きい２００μｍまでのギャップ８が存在する。 さらに第２図に示されているように、支持基板１には、素子２の下側で円形横 断面を有する中央の開口５が設けられており、この開口５は、支持基板の装着側 から反対側まで延びている。中央の開口の代わりに、多数の開口を素子の下側で 支持基板内に設けてもよい。開口５は例えば、素子２を取り付ける前に穿孔され るか又は、貫通接触を製造するために公知のプロセスによって支持基板内にもた らすことができる。 リフローはんだ付け後に、毛細管現象で流動可能な 接着剤例えばＳiＯ2充填材を有するエポキシ樹脂接着剤が、特別な下方注入工程 若しくはアンダーフィル(Undefill)プロセスで、素子２と支持基板１との間のキ ャップ８内にもたらされる。接着剤１０は、ディスペンス装置によって素子２の 縁部で支持基板１上に塗布される。この場合、公知のアンダーフィルプロセスに おけるのとは別に、接着結合部を形成するための必要な全接着剤量は、図１に実 線の矢印で示された１本の線に沿って塗布される。素子の全部で４つの側に塗布 された毛細管・接着剤１０は、直ちにはんだ盛り３間のスペース内に侵入して、 図２及び図４のａに示されているように、すべてのはんだ盛り３の周囲に流れ込 み、次いで矢印方向でギャップ８内の開口５まで広がる。この際に、ギャップ内 に存在する空気は、開口５を通って外方に押しやられる。次いで、ギャップ８全 体は接着剤で満たされ、接着剤は、図３に示されているように開口５内に侵入す る。接着剤の塗布後に接着剤を塗布するためのその他の段階は必要ないので、デ ィスペンス装置は、次の接着結合部を形成するために直ちに投入することができ る。図４には、図２に示したギャップ８の横断面が示されている。図４のａ〜図 ４のｄには、ギャップ８内での接着剤１０の広がりが特に良く分かるように示さ れている。接着剤１０の塗布後に、接着剤はまずはんだ盛り３の周囲に流れ込み 、閉じた接着剤先端部を形成し、この接着剤先端部 が、矢印方向で開口５に向かって寄せ集められる。図４のｂに示されるように、 接着剤先端部の一部は、その他の部分よりも早く開口５に達する。接着剤が早期 に開口５内に侵入することによって残りの空気がギャップ８から漏れ出るのを妨 げることがないようにするために、環状のコーティング９が支持基板１上で開口 ５の周囲に塗布される。コーティングは、基盤を製造するためのプリント基板技 術から公知のプロセスによって製造され、接着剤がつきにくい材料より成ってい る。このコーティングとしては有利な形式で、銅又は金から成る金属被覆が流し 込まれる。有機的なプリント基板材料は接着剤によって迅速に濡らされるので、 金属被覆は、接着剤先端部の流れ速度を次のように調節する。つまり、接着剤先 端部が、図４のｃに示されているように、まず完全に金属被覆の周囲に引き寄せ られ、次いで金属被覆が濡らされ、図４のｄに示されているように開口５内に侵 入するように、調節する。これによって確実に、ギャップ８内に気泡が封じ込め られないようになっている。特に有利には、この実施例においては、まず素子２ の縁部に配置されたはんだ盛り３が接着剤によって取り囲まれ、それによって保 護されるようになっている。 別の実施例では、コーティング９の代わりに、素子２に向かって段付けされた リング状の突起部が支持基板上に設けられる。この支持基板は、開口５の上縁部 を環状に取り囲んでいる。段状の突起部の環状の縁部には、第４図のｃに示した 前記実施例におけるように、接着剤先端部が集まり、こうして段状の突起部の上 側を濡らして、開口内に侵入する。 本発明による方法の別の実施例は、第５図及び第６図に示されている。素子２ は、前記実施例におけるのと同様に、公知のフリップ・チップ技術で支持基板上 に載せられて、この支持基板にはんだ付けされる。素子２が被着された箇所で開 口５が支持基板１を通って野路手いる。開口５は、接着剤の毛細管状の流動性の ために十分な直径を有している。さらに、この実施例においても、素子２は、開 口５が素子の下側で中央に位置するように、プリント基板上に被着される。第２ 図に示した実施例とは異なり、この実施例では、開口５の縁部を制限する金属被 覆は設けられていない。リフローはんだ付け後に、支持基板１は、第５図に示さ れているように、装着側が下に向けられる。ディスペンス装置によって、アンダ ーフィルプロセスのために必要な、毛細管現象に従って流動性の接着剤１０の全 量が、開口５の領域内で支持基板１の上に向けられた下面に塗布される。通路状 の開口５の毛細管現象によって、接着剤１０は、これがギャップ８内に達するま で開口５内に侵入する。ギャップ８内には、第６図に示されているように、接着 剤１０はそのほぼ円形の接着剤先端部がはんだ盛り３を完全に取り囲むまで広が る。この際に、ギャップ内に存在する空気が、はんだ盛り間の中間スペースを通 って外に押しやられる。第１実施例とは異なり、接着剤１０は、流動過程の最後 にはんだ盛り３間のスペース内に侵入する。Description: The present invention relates to a method for forming an adhesive bond between an electronic element and a support substrate, the method comprising the steps of: A method for forming. It is already known to deposit electronic components on a supporting substrate in a so-called flip-chip technique. Devices applied in flip-chip technology have contact elements for soldering, isotropic and conductive bonding or thermocompression bonding. In flip-chip soldering, the connection side of the chip is provided with a large number of contact elements, for example "solder bumps", which are configured smaller than the solder bumps, and then this connection side is provided. The chip is turned upside down and placed on a support substrate with a contact surface. At this time, the arrangement of the contact surfaces on the support substrate corresponds to the pattern of the solder pile on the chip. Next, the solder pile is soldered to the contact surface on the support substrate by a reflow soldering method. According to the flip-chip method, a large number of wireless, electrically conductive connections between the chip and a supporting substrate with electronic circuits can be made in an advantageous manner in one working step. Based on the different expansion rates of the chip (silicon; silicon) and the support substrate (printed circuit board material), an adhesive is injected between the chip and the support substrate in a so-called “underfill process”. Therefore, it is necessary to prevent the soldering point from being affected by the temperature change load. For this purpose, an adhesive which is flowable, in particular according to capillary action, is applied by means of a dispensing device along at least one chip edge onto the support substrate. Due to the capillary action, the adhesive flows into the narrow gap between the chip and the substrate. After curing, the adhesive absorbs mechanical stresses, thereby protecting the solder joint and increasing the useful life of the solder joint. According to another flip-flip technique, the chip is provided with a contact element, which is applied with an isotropic, electrically conductive adhesive and then glued onto the contact surface of the supporting substrate. ing. Also in this technique, after forming an electrical connection between the chip and the supporting substrate, an adhesive is applied by an underfill process so that the adhesive protects the isotropic and conductive adhesive connection. It has become. Furthermore, flip-chip technology is known, in which the chip is provided with a contact element and the chip is applied on the contact surface of a supporting substrate in a thermocompression bonding method. Also in this method, an underfill process is required to ensure sufficient mechanical shape stability of the joint. In order to prevent air from being trapped, in the method described above, an adhesive is applied to one or two chip edges, the adhesive being applied to the other side of the chip, ie to the underside of the chip. It is known to spread. Since not all adhesive amounts can be applied to one chip edge, the application operation has to be repeated many times until finally all contact elements are surrounded by adhesive. Such a method is described, for example, in Solid State Technology, April 1997, Alec. J. It is described in Babiarz's paper "Key process controls for underfilling flip chips". In this case, it is necessary to always have a pause between each application step, based on the flow time of the glue, and to add new glue until the entire gap between the chip and the substrate is finally filled. Have to be applied. Therefore, for particularly large chips, tedious waiting times must be considered. Due to the long waiting times, the production time is significantly increased, which again increases the production costs significantly. Advantages of the invention In contrast, a method for forming an adhesive bond between an electronic device and a supporting substrate according to the invention, having the features described in the characterizing part of claim 1, for forming an adhesive bond Has the advantage that the total amount of adhesive required for a single operation can be applied by means of a dispensing device. In this way, waiting times due to the flow time of the adhesive are advantageously avoided, whereby the manufacturing costs for forming the connection are significantly reduced. The method according to the invention is very advantageous for forming adhesive bonds, especially in large chips with edge lengths of up to 3 cm. Further advantageous embodiments and variants of the invention are possible with the measures specified in the dependent claims. A flowable adhesive is applied in close proximity to the element along a closed path extending around the perimeter of the element according to capillary action, and then the adhesive flows around all contact elements located at the edge of the element. This is particularly advantageous. The closed adhesive tip then spreads to at least one opening by capillary action of the gap between the element and the support substrate, with air present in the gap passing through the at least one opening to the outside. Is to be extruded. In this way, the solder, adhesive or bonding connection between the contact element of the element and the contact surface of the support substrate can be optimally protected. Before applying the adhesive, the support substrate is turned upside down with the attached element down, and the adhesive is applied to the opening provided on the support substrate behind the support substrate by a dispensing device. Especially simple. The adhesive follows the capillarity, penetrates into the openings and into the gap between the element and the supporting substrate and then flows around the contact elements arranged around the element. Furthermore, it is advantageous to provide an opening in the form of a hole arranged centrally below the element. This is because the adhesive then spreads particularly uniformly between the central hole and the contact element under the element. The glue is applied to the side with the element, so that the glue first flows around the periphery of the contact element and then spreads out to at least one opening, so that the glue tip can reach partly the opening. , Other parts have not yet reached the opening. Premature penetration of the adhesive into the openings before all the air is pushed out of the gap is avoided by providing a coating on the side of the support substrate on which the elements are mounted. The coating is applied around the edge of the opening and is made of a material that is not easily wetted by the adhesive. This coating is a metallization, preferably made of copper or gold. Instead of the coating, a stepped step may be provided so as to surround the edge of the opening on the side of the supporting substrate provided with the element. This protrusion prevents the adhesive from prematurely penetrating into the opening, such as a metal coating. Drawings One embodiment of the present invention is illustrated in the drawings and described in detail below. FIGS. 1 to 3 show a first embodiment of the method according to the invention for forming an adhesive bond between a substrate and a flip-chip device, FIGS. FIG. 3d shows different stages of the spreading of the adhesive tip in the embodiment shown in FIGS. FIGS. 5 and 6 show a second embodiment of the method according to the invention for forming an adhesive bond between a substrate and a flip-chip device. DESCRIPTION OF THE EMBODIMENTS A first embodiment of the method according to the invention for forming an adhesive bond between a device and a supporting substrate, shown in FIGS. 1 to 3, is shown. Flip chip elements 2 are soldered in a known manner onto a support substrate 1, which may be a printed circuit board, for example an FR4 substrate, a ceramic support, a chip support / element or any other suitable substrate. Instead of a flip chip not surrounded by a casing, a flip chip element, for example, housed in a multi-chip module, or a so-called chip scale package, may be applied on the support substrate. Furthermore, it is of course possible to apply one or more elements in the same manner on a supporting substrate. The illustrated embodiment is limited to only one element for simplicity. As shown in FIG. 2, the element 2 has, on its connection side, a plurality of contact elements 3 which are arranged in a circumferential direction and which are arranged in a solder pile (so-called "solder"). bumps "). In flip-chip technology, the element 2 with the solder ridge 3 is mounted on a corresponding raster of the contact surface 4 of the support substrate 1 and soldered to the support substrate 1 at a reflow soldering station. After reflow soldering, the element 2 is electrically connected to the contact surface 4 of the support substrate 1 in the manner shown in FIG. The flip-chip element is glued to the contact surface 4 by means of an isotropically conductive adhesive applied on the contact element 3 or is welded on the contact surface by a thermocompression method. In order to make an electrical connection between the contact element 3 and the contact surface 4, there is a narrow gap 8 between the element 2 and the substrate 1 from about 30 μm to as large as 200 μm. Further, as shown in FIG. 2, the support substrate 1 is provided with a central opening 5 having a circular cross section below the element 2, and this opening 5 is provided from the mounting side of the support substrate. It extends to the other side. Instead of a central opening, multiple openings may be provided in the support substrate below the element. The openings 5 can be drilled, for example, before mounting the element 2, or can be provided in the support substrate by known processes for producing through contacts. After reflow soldering, epoxy resin adhesive having a flowable adhesive eg S i O 2 filler by capillary action is a special lower implantation process or underfill (Undefill) process, the element 2 and the supporting substrate 1 Brought into the cap 8 in between. The adhesive 10 is applied onto the support substrate 1 at the edge of the element 2 by a dispensing device. In this case, apart from in the known underfill process, the total amount of adhesive required to form the adhesive joint is applied along one line, indicated by the solid arrow in FIG. . The capillary / adhesive 10 applied to all four sides of the device immediately penetrates into the space between the solder piles 3 and, as shown in FIGS. 3 and then spreads in the direction of the arrow to the opening 5 in the gap 8. At this time, the air existing in the gap is pushed outward through the opening 5. The entire gap 8 is then filled with adhesive, which penetrates into the opening 5 as shown in FIG. Since no other steps are required to apply the adhesive after the adhesive has been applied, the dispensing device can be turned on immediately to form the next adhesive bond. FIG. 4 shows a cross section of the gap 8 shown in FIG. FIGS. 4 a to 4 d show the spread of the adhesive 10 in the gap 8 so that it can be seen particularly well. After the application of the adhesive 10, the adhesive first flows around the solder pile 3 to form a closed adhesive tip, which is gathered towards the opening 5 in the direction of the arrow. As shown in FIG. 4b, a part of the adhesive tip reaches the opening 5 earlier than the other parts. An annular coating 9 is applied around the perimeter of the opening 5 on the support substrate 1 so as not to prevent the adhesive from penetrating into the opening 5 prematurely so that the remaining air escapes from the gap 8. Is done. The coating is manufactured by a process known from printed circuit board technology for manufacturing the substrate and is made of a material that is difficult to adhere to. The coating is advantageously cast with a metal coating of copper or gold. Since the organic printed circuit board material is quickly wetted by the adhesive, the metallization regulates the flow rate of the adhesive tip as follows. That is, the adhesive tip is first drawn completely around the metallization, as shown in FIG. 4c, then the metallization is wetted, and the opening is opened, as shown in FIG. 4d. Adjust so as to invade 5. This ensures that no air bubbles are trapped in the gap 8. It is particularly advantageous that, in this embodiment, first the solder bumps 3 arranged at the edge of the component 2 are surrounded by an adhesive and are thereby protected. In another embodiment, instead of the coating 9, a ring-shaped protrusion stepped towards the element 2 is provided on the support substrate. This support substrate annularly surrounds the upper edge of the opening 5. At the annular edge of the step-like projection, as in the embodiment shown in FIG. 4c, the adhesive tips gather, thus wetting the upper side of the step-like projection and leaving it in the opening. invade. Another embodiment of the method according to the invention is shown in FIGS. The element 2 is mounted on a support substrate and soldered to the support substrate by the known flip-chip technique as in the previous embodiment. An opening 5 passes through the support substrate 1 at the place where the element 2 is attached. The opening 5 has a diameter sufficient for the capillary flow of the adhesive. Further, also in this embodiment, the element 2 is mounted on the printed circuit board such that the opening 5 is located at the center below the element. Unlike the embodiment shown in FIG. 2, in this embodiment no metal coating is provided to limit the edge of the opening 5. After reflow soldering, the support substrate 1 is turned down on the mounting side as shown in FIG. The dispensing device applies the entire amount of the flowable adhesive 10 according to the capillarity required for the underfill process to the lower surface directed onto the support substrate 1 in the region of the openings 5. Due to the capillary action of the passage-like opening 5, the adhesive 10 penetrates into the opening 5 until it reaches the gap 8. In the gap 8, as shown in FIG. 6, the adhesive 10 spreads out until its substantially circular adhesive tip completely surrounds the solder pile 3. At this time, the air present in the gap is forced out through the intermediate space between the solder piles. Unlike the first embodiment, the adhesive 10 penetrates into the space between the solder piles 3 at the end of the flow process.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 ホンクァン ジャン ドイツ連邦共和国 Ｄ―10551 ベルリン ヴィルヘルムスハーフェナー シュトラ ーセ 58────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Hong Kwan Jiang             Germany D-10551 Berlin               Wilhelmshavener Stra             -58

Claims (1)

【特許請求の範囲】 １．電子素子と支持基板との間の接着結合を形成するための方法であって、片面 側に多量の接触エレメント（３）を備えた、少なくとも１つの素子（２）特にフ リップ・チップ素子を、前記接触エレメントに対応するように整列された、支持 基板（１）の接触面（４）と導電接続し、ディスペンス装置によって、毛細管現 象に従って接触エレメント（３）の周囲を流れる接着剤（１０）を、素子（２） と支持基板（１）との間のギャップ（８）内に侵入させる方法において、 支持基板に被着された素子（２）の下側で、支持基板（１）を貫通する少な くとも１つの開口（５）を設け、毛細管現象に従って流動性である接着剤（１０ ）を、これが少なくとも１つの開口（５）と接触エレメント（３）との間で広が るように、支持基板（１）上に施すことを特徴とする、電子素子と支持基板との 間の接着結合を形成するための方法。 ２．毛細管現象に従って流動性である接着剤（１０）を、素子（２）の外周を巡 って延びる閉じた経路に沿って、素子の直ぐ近くに施し、次いですべての接触エ レメント（３）の周囲に流し入れて、閉じた接着剤先端部が生じるようにし、こ の接着剤先端部が、素子（２）と支持基板（１）との間のギャップ（ ８）の毛細管現象によって、少なくとも１つの開口（５）まで広がり、この際に 、ギャップ（８）内に存在する空気が少なくとも１つの開口（５）を通って外部 に押しやられるようにする、請求項１記載の方法。 ３．支持基板（１）を、被着した素子（２）を下に向けてひっくり返し、次いで 毛細管現象に従って流動性である接着剤（１０）を、ディスペンス装置によって 少なくとも１つの開口（５）の領域内で、この状態で素子（２）とは反対側であ る、支持基板（１）の上面に塗布し、開口（５）の毛細管現象によって、開口を 通ってギャップ（８）まで、及びこのギャップ（８）から接触エレメント（３） まで広がるようにする（第５図）、請求項１記載の方法。 ４．素子（２）の下側で中央に配置された個別の、孔として構成された開口（５ ）を支持基板（１）に設ける、請求項２又は３記載の方法。 ５．支持基板（１）の、素子（２）を備えた側に存在する、開口（５）の縁部を 、毛細管現象に従って流動性である接着剤（１０）によって濡らしにくい材料よ り成るコーティング（９）によって取り囲む（第４図）、請求項３又は４記載の 方法。 ６．コーティング（９）を、有利には銅又は金より成る金属被覆より製造する、 請求項５記載の方法。 ７．支持基板（１）の、素子（２）を備えた側に存在 する、開口（５）の縁部を、段付けされた段状の突起によって取り囲む、請求項 ３又は４記載の方法。[Claims] 1. A method for forming an adhesive bond between an electronic element and a support substrate, comprising: At least one element (2), in particular a fan, with a large number of contact elements (3) on the side. A support for aligning the lip chip element with the contact element It is electrically conductively connected to the contact surface (4) of the substrate (1), and a capillary tube is formed by a dispensing device. An adhesive (10) flowing around the contact element (3) according to the elephant is applied to the element (2). In the gap (8) between the support and the support substrate (1),     Under the element (2) attached to the support substrate, a small amount of At least one opening (5) is provided and the adhesive (10 ) Which extends between at least one opening (5) and the contact element (3). The electronic device and the support substrate, wherein the electronic device and the support substrate are provided on the support substrate (1). Method for forming an adhesive bond between. 2. An adhesive (10) that is fluid according to the capillary phenomenon is applied around the periphery of the element (2). Close to the device, along a closed path extending through Pour it around the element (3) so that a closed adhesive tip forms, Of the adhesive (2) and the gap () between the element (2) and the support substrate (1). Due to the capillary action of 8), it extends to at least one opening (5), The air present in the gap (8) passes through at least one opening (5) to the outside The method of claim 1, wherein the squeeze is performed. 3. The support substrate (1) is turned over with the deposited element (2) facing down, and then An adhesive (10) that is flowable according to capillary action is dispensed by a dispensing device. In the region of at least one opening (5), in this state on the side opposite the element (2) The opening is applied to the upper surface of the supporting substrate (1) by capillary action of the opening (5). Through the gap (8) and from this gap (8) to the contact element (3) 2. The method according to claim 1, wherein the expansion is effected (FIG. 5). 4. An individual, centrally arranged aperture (5) arranged below the element (2) 4. The method according to claim 2, wherein (a) is provided on the support substrate (1). 5. The edge of the opening (5) on the side of the support substrate (1) provided with the element (2) A material which is hardly wetted by the adhesive (10) which is fluid according to the capillary phenomenon. 5. A method according to claim 3, wherein said coating is surrounded by a coating (9) (FIG. 4). Method. 6. The coating (9) is produced from a metallization, preferably consisting of copper or gold; The method of claim 5. 7. Present on the side of the support substrate (1) provided with the element (2) The edge of the opening (5) is surrounded by a stepped step projection. 5. The method according to 3 or 4.
JP11507956A 1997-07-08 1998-03-25 Method for forming an adhesive bond between an electronic device and a support substrate Pending JP2001501381A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19729073.6 1997-07-08
DE19729073A DE19729073A1 (en) 1997-07-08 1997-07-08 Method for producing an adhesive connection between an electronic component and a carrier substrate
PCT/DE1998/000870 WO1999003145A1 (en) 1997-07-08 1998-03-25 Method for making a glued joint between an electronic component and a supporting substrate

Publications (1)

Publication Number Publication Date
JP2001501381A true JP2001501381A (en) 2001-01-30

Family

ID=7834968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11507956A Pending JP2001501381A (en) 1997-07-08 1998-03-25 Method for forming an adhesive bond between an electronic device and a support substrate

Country Status (6)

Country Link
EP (1) EP0923791A1 (en)
JP (1) JP2001501381A (en)
KR (1) KR20000068591A (en)
DE (1) DE19729073A1 (en)
HU (1) HUP0000672A3 (en)
WO (1) WO1999003145A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009044863A1 (en) * 2007-10-03 2009-04-09 Fujikura Ltd. Module, wiring board and module manufacturing method
JP2010153477A (en) * 2008-12-24 2010-07-08 Kyocera Corp Circuit device and electronic device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59809584D1 (en) * 1998-12-24 2003-10-16 Nokia Corp Process for mechanically attaching electrical components to a circuit board and a device produced by this process
DE19902450B4 (en) * 1999-01-22 2006-04-20 Festo Ag & Co. Miniaturized electronic system and method suitable for its production
DE19908474C2 (en) 1999-02-26 2001-02-15 Siemens Ag Method for mounting a semiconductor chip on a base layer
DE10047135B4 (en) * 2000-09-22 2006-08-24 Infineon Technologies Ag Process for producing a plastic-encased component and plastic-coated component
DE10327767A1 (en) * 2003-06-18 2005-01-05 Marconi Communications Gmbh Circuit assembly and manufacturing method therefor
JP2005108950A (en) * 2003-09-29 2005-04-21 Matsushita Electric Ind Co Ltd Ceramic modular component and its manufacturing method
DE102015207893B3 (en) * 2015-04-29 2016-10-13 Robert Bosch Gmbh Electronic assembly, in particular for a transmission control module
US11152226B2 (en) 2019-10-15 2021-10-19 International Business Machines Corporation Structure with controlled capillary coverage
DE102021133671A1 (en) * 2021-12-17 2023-06-22 Jenoptik Optical Systems Gmbh Process for manufacturing a diode laser and diode laser

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4143456A (en) * 1976-06-28 1979-03-13 Citizen Watch Commpany Ltd. Semiconductor device insulation method
CH660551GA3 (en) * 1982-12-27 1987-05-15
US5218234A (en) * 1991-12-23 1993-06-08 Motorola, Inc. Semiconductor device with controlled spread polymeric underfill
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
JP2962385B2 (en) * 1993-01-07 1999-10-12 松下電子工業株式会社 Method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009044863A1 (en) * 2007-10-03 2009-04-09 Fujikura Ltd. Module, wiring board and module manufacturing method
JPWO2009044863A1 (en) * 2007-10-03 2011-02-10 株式会社フジクラ Module, wiring board, and module manufacturing method
JP2010153477A (en) * 2008-12-24 2010-07-08 Kyocera Corp Circuit device and electronic device

Also Published As

Publication number Publication date
DE19729073A1 (en) 1999-01-14
WO1999003145A1 (en) 1999-01-21
HUP0000672A3 (en) 2000-07-28
KR20000068591A (en) 2000-11-25
EP0923791A1 (en) 1999-06-23
HUP0000672A2 (en) 2000-06-28

Similar Documents

Publication Publication Date Title
JP4618260B2 (en) Conductor pattern forming method, semiconductor device manufacturing method, and semiconductor device
US6281046B1 (en) Method of forming an integrated circuit package at a wafer level
US9545013B2 (en) Flip chip interconnect solder mask
US5482736A (en) Method for applying flux to ball grid array package
KR101008891B1 (en) Wiring board, mounting structure for electronic components and semiconductor device
KR20020059851A (en) Integrated circuit package formed at a wafer level
US20080036094A1 (en) Functional device-mounted module and a method for mounting functional device-mounted module
US6107689A (en) Semiconductor device
KR20060084802A (en) Circuit board and manufacturing method therefor and semiconductor package and manufacturing method therefor
JP2001501381A (en) Method for forming an adhesive bond between an electronic device and a support substrate
JP2003007902A (en) Electronic component mounting substrate and mounting structure
JPH08153830A (en) Semiconductor device and manufacture thereof
JP2002373967A (en) Semiconductor device and method for manufacturing the same
JP2870533B1 (en) Semiconductor device and manufacturing method thereof
JP4566915B2 (en) Semiconductor device mounting body and method of manufacturing semiconductor device mounting body
JPH11135552A (en) Manufacture of semiconductor device
JP3325410B2 (en) Method for manufacturing semiconductor device
JPH08153738A (en) Manufacture of semiconductor device
JP2003092382A (en) Semiconductor device and method for manufacturing the same
JP4056816B2 (en) Semiconductor device
JP3349361B2 (en) Semiconductor device and manufacturing method thereof
JP3914332B2 (en) Manufacturing method of semiconductor device
JP2001237534A (en) Electronic component mounting method and substrate for mounting electronic component
JPH05152303A (en) Semiconductor device with protruding electrode, protruding electrode forming method and the semiconductor device mounting body
JP2000208544A (en) Bare ic chip and semiconductor device