JP2001358594A - Crc computing device and crc computing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct a high-speed CRC computation and use flexibly various generating polynominals without excessive increase in circuit scale. SOLUTION: A CRC computing device is comprised of a circuit provided in general with a DSP that is added with several circuits, and it is provided with a generating polynominal supply part 11 which is provided with a first general-purpose register 12 storing an optional generating polynominal or a selector 13 that selects and outputs the generating polynominal or a data having all bits of zero value, a computed data supply part 21 which is provided with a memory 22, a shift register 23, a second general-purpose register 24, and a barrel shifter 25 and outputs a computed data for CRC computation on the basis of the transmission and reception data, a computing part which conducts CRC computation using the generating polynominal and computed data outputted from the generating polynominal supply part 11 and computed data supply part 21, and a computation command execution control part 41 to control the operation of each part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention detects whether or not an error has occurred in transmission / reception data when the transmission / reception data is transmitted via a communication path or when data processing for transmission is performed. CRC which is an error detection code for performing
(Cyclic Redundancy Check) The present invention relates to a CRC operation device and a CRC operation method for generating a code or detecting a code error of transmission / reception data added with such an error detection code.

[0002]

2. Description of the Related Art CRC is an error detection system frequently used in digital communication. This error detection method detects an error as follows. That is, on the transmission side, the transmission data is regarded as a higher-order polynomial, and the remainder obtained by dividing by a predetermined generator polynomial is added to the transmission data as a CRC code (encoding). On the receiving side, division is performed using the same generator polynomial (decoding), and if the remainder is 0, it is determined that there is no error in the transmitted data, while if the remainder is not 0, it is determined that there is an error. (Error detection). As the generator polynomial, for example, the following is used for an actual CRC. (1) CRC-12 (2) CRC-16 (3) CRC-CCITT As an apparatus for performing the above-described encoding and error detection, that is, a CRC operation, there is a CRC operation apparatus for performing a CRC operation by hardware. This uses a divider configured by combining a shift register and an exclusive OR gate. In this type of device, a generator polynomial is determined by how the shift register and the exclusive OR gate are connected. For this reason, the generator polynomial cannot be changed with this type of device. Therefore, it is necessary to use a different device for each applied generator polynomial. In addition, a device to which the same generator polynomial is applied must be used on the transmitting side and the receiving side.

On the other hand, as a CRC operation device to which various generator polynomials can be flexibly applied, a CR operation device by software is used.
There is a device for performing C operation. In such a device, various generator polynomials can be easily applied simply by switching the program or data. However, usually, the CRC calculation is executed by the processor of the communication terminal, and a heavy load is applied to the processor, so that the processing capability of the communication terminal is reduced. Also, C by software
Since the RC operation has a low operation speed, it is not suitable for high-speed communication.

Therefore, as an apparatus which can achieve both the flexibility of the generator polynomial and the high speed of the CRC operation, for example, Japanese Patent Laid-Open No.
As disclosed in JP-A-151007, there is known a device configured by combining a generator polynomial setting register, a shift register, and an exclusive OR gate. Since this device performs a CRC operation by hardware, high-speed processing is possible, and various generator polynomials can be applied by changing the generator polynomial set in the generator polynomial setting register.

[0005]

However, since the above-described CRC operation device uses a dedicated circuit specialized for the CRC operation, the circuit scale of a communication device or the like is increased. Had. Although various types of generator polynomials having the same bit length as the generator polynomial setting register can be applied, application of generator polynomials having different bit lengths has not been considered.

In view of the above, the present invention provides a CRC operation which can perform a high-speed CRC operation without significantly increasing the circuit scale, and which can flexibly apply various generator polynomials. It is intended to provide equipment.

[0007]

In order to achieve the above object, the present invention relates to a CRC operation device, which holds data indicating a generator polynomial, and sets the data indicating the generator polynomial and the value of all bits to 0. A generator polynomial supply means for selectively outputting zero data, a calculation data supply means for outputting calculation data for performing a CRC calculation, an exclusive data of the generation polynomial or zero data, and the calculation data Arithmetic / logic operation means for performing a logical sum operation, wherein the generator polynomial supply means outputs data of the generator polynomial and zero data according to the value of the most significant bit of the operation result by the arithmetic / logic operation means. Configured to make a choice,
The arithmetic data supply means sets the value of a bit lower than the most significant bit of the operation result of the arithmetic and logic operation means to the value of the upper bit, and sets the value of the most significant bit of the data to be subjected to the unprocessed CRC operation to the most significant bit. It is characterized in that it is configured to output data as the value of the lower bit as the operation data.

[0008] Specifically, the generator polynomial supply means includes:
For example, a first register for holding data indicating the generator polynomial, and a selector for selectively outputting the data indicating the generator polynomial or the zero data, the arithmetic data supply means may include: For example, a second register for holding the operation result by the arithmetic and logic operation means, a shifter for shifting the operation result held in the second register left by one bit and outputting the result, and an unprocessed CRC operation A memory for holding the target data; and a part of the unprocessed data to be subjected to the CRC operation transferred from the memory, and outputs the value of the most significant bit of the stored data. And a shift register that shifts the held data left by one bit.

Thus, various generator polynomials can be easily applied flexibly by changing the data indicating the generator polynomial held by the generator polynomial supply means. Further, selection of data indicating a generator polynomial or zero data, which is input to the arithmetic and logic operation means,
Since the generation of the operation data for performing the operation is automatically performed without depending on the execution of the program instruction, a high-speed CRC operation can be performed. Moreover, the generator polynomial supply means, supply means, and arithmetic and logic operation means mainly include
Since the components included in a normal processor can be used, it is possible to suppress an increase in the circuit scale of the entire device including the CRC operation device.

Further, the apparatus further comprises an operation instruction execution control means, wherein the operation instruction execution control means outputs data or zero data indicating the generation polynomial by the generation polynomial supply means in accordance with a predetermined operation instruction. The output of the operation data by the operation data supply unit and the execution of the exclusive OR operation by the arithmetic and logic operation unit may be controlled.

The arithmetic instruction execution control means includes, for example, the generating polynomial supply means for performing the exclusive OR operation by the arithmetic and logical operation means once in accordance with a predetermined arithmetic instruction; The arithmetic and logic unit may be configured to control an operation of the arithmetic and logic unit. The arithmetic and logic unit may perform the arithmetic and logic operation on all of the unprocessed data to be subjected to the CRC operation according to a predetermined operation instruction. The generator may be configured to control the operations of the generator polynomial supply unit, the operation data supply unit, and the arithmetic and logic operation unit for performing the exclusive OR operation by the operation unit. According to the operation instruction, the exclusive OR operation is performed on the values of all the bits held in the shift register by the arithmetic and logical operation means. Of the generating polynomial supply means, the operation data supply means, and it may be configured to control the operation by the arithmetic logic unit.

Thus, the flexibility of the CRC operation process is increased by increasing the degree of freedom of the combination of operation instructions,
It is possible to increase the speed of the CRC operation processing with a small number of operation instructions.

After the exclusive OR operation is performed by the arithmetic and logic means on all of the unprocessed data to be subjected to the CRC operation, the value held in the second register is changed. After the exclusive-OR operation is performed by the arithmetic and logical operation means on all of the unprocessed data to be subjected to the CRC operation, the data is stored in the second register. It may be configured such that it is determined whether or not there is an error in the data to be subjected to the unprocessed CRC calculation, depending on whether or not the held value is 0.

Thus, CRC coding and data error detection can be easily performed.

Further, the generator polynomial supply means fills the data indicating the generator polynomial with a higher-order data when the number of bits of the data indicating the generator polynomial is smaller than the number of bits that the generator polynomial supply means can hold. It may be configured to hold the value and to hold the value of 0 in the lower bit while holding.

Thus, the flexibility of the generator polynomial to be applied can be increased not only with respect to the type of generator polynomial but also the number of bits.

According to another aspect of the present invention, there is provided a CRC operation device, wherein a generator polynomial holding means for holding data indicating a generator polynomial, and a CRC operation is performed based on data indicating the generator polynomial and data to be subjected to a CRC operation. When the number of bits of the data indicating the generator polynomial is smaller than the number of bits that can be held by the generator polynomial holding means, the data indicating the generator polynomial is stored in the generator polynomial holding means. While being held in the stuffing,
The low-order bit is configured to hold a value of 0.

Thus, even when a dedicated circuit specialized for CRC calculation is configured, not only the type of the generator polynomial but also the number of bits thereof, the flexibility of the generator polynomial to be applied can be increased.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) As an embodiment of the present invention, an example of a CRC arithmetic unit provided inside a processor such as a DSP (digital signal processor) will be described with reference to FIG. This device is generally configured by adding some circuits to circuits provided in a DSP.

As shown in FIG. 1, the CRC operation device includes a generator polynomial supply section 11 (generator polynomial supply means) for holding and outputting an arbitrary generator polynomial (data indicating).
An operation data supply unit 21 (operation data supply means) for outputting operation data for CRC operation based on the transmission / reception data, and the generation polynomial supply unit 11 and the generation polynomial and operation data output from the operation data supply unit 21 An operation unit 31 (arithmetic logic operation means) for performing a CRC operation using the same, and an operation instruction execution control unit 41 (operation instruction execution control means) for controlling the operation of each unit are provided.

The generator polynomial supply unit 11 includes a first general-purpose register 12 in which a generator polynomial is stored, and a value (generator polynomial) stored in the first general-purpose register 12 or a value in which all bits are zero. A selector 13 for selecting and outputting data ("0"). The selector 13 is:
More specifically, when the value of the most significant bit (MSB) of the second general-purpose register 24 to be described later is 0, “0” is selected, and when it is 1, the generator polynomial stored in the first general-purpose register 12 is selected. It is supposed to. Note that the selector 13 is actually provided with the first general-purpose register 12.
, And the value of the MSB of the second general-purpose register 24 may be configured by an AND circuit train or the like.

The operation data supply unit 21 includes a memory 22
, A shift register 23 and a second general-purpose register 24
And a barrel shifter 25.

The memory 22 stores transmission / reception data.

The shift register 23 outputs the value of the MSB of the held data to the calculation unit 31 as the value of the LSB of the calculation data for each cycle of the CRC calculation, and then shifts the data left by one bit. It is supposed to. Then, when the values of all the bits of the held data are output, the next data is transferred from the memory 22.

The second general-purpose register 24 holds the data transferred from the memory 22 as an initial value when the CRC operation is started, and thereafter, the second general-purpose register 24 executes the operation unit every one cycle of the CRC operation. The data of the operation result output from the terminal 31 is held.

The barrel shifter 25 shifts the data held in the second general-purpose register 24 to the left by one bit, and sets the value of the bit higher than the LSB as the value of the bit higher than the LSB of the operation data. The data is output to the calculation unit 31. Note that, instead of the MSB value of the shift register 23 being directly input to the operation unit 31 as described above, the MSB value is input to the barrel shifter 25 and becomes the LSB value of the operation data at the time of the left shift. It may be.

The operation unit 31 includes an arithmetic and logic operation unit 32. The operation polynomial or "0" output from the generation polynomial supply unit 11 and the operation data supply unit 21 are provided.
An exclusive-OR operation with the operation data output from is performed. The data of the operation result is stored in the second general-purpose register 24 as described above.

Each of the above sections has a bit width of, for example, M bits.

The operation instruction execution control unit 41 controls the operation of each unit constituting the DSP based on the operation instruction given as a program, and mainly executes the operation of each of the above units based on the operation instruction related to the CRC operation. The operation is controlled.

Here, the first general-purpose register 12, the memory 22, the second general-purpose register 24, the barrel shifter 2
5 and the arithmetic and logic unit 32 may be those normally provided in a processor. That is, particularly provided for the CRC operation are mainly the signal path between the selector 13, the shift register 23, the above-described units, and the like, and the C command in the operation instruction execution control unit 41.
This part has a control function for RC calculation. Therefore, a CRC processor can be configured by simply adding these components to a general processor,
Since the entire CRC operation device is not specialized for the CRC operation, an increase in the overall circuit scale of the DSP or the like can be suppressed.

In the CRC operation device configured as described above, the CRC operation is performed according to the operation instruction given to the operation instruction execution control unit 41. Below, about the operation,
A description will be given based on the flowchart of FIG. (Note that the following steps are for convenience of description and do not necessarily correspond one-to-one with instruction cycles and machine cycles.) (Step S1) First, a first instruction is performed by a transfer instruction. A generator polynomial is set in the general-purpose register 12. Here, assuming that the bit length of the generator polynomial to be set is N, N <M
(M is the bit width of the first general-purpose register 12). In this case, a value in which upper bits are padded by a left shift instruction or the like and 0 is embedded in lower bits is set in the first general-purpose register 12.

(Step S2) Similarly, the first M-bit data (initial data) of the transmission / reception data stored in the memory 22 is set in the second general-purpose register 24 by the transfer command.

(Step S3) Further, the next M bits of data (input data 1 to X) are set in the shift register 23 by the transfer command.

(Step S4) Next, C of M cycles
An RC operation, that is, a CRC operation corresponding to the M-bit transmission / reception data held in the shift register 23 is performed. More specifically, the following operation is performed.

That is, the arithmetic and logic unit 32 calculates the value of the upper M-1 bits and the shift value of the value held in the second general-purpose register 24 from the value shifted and output from the barrel shifter 25 as described above. The operation data of M bits in total with the 1-bit value of the MSB output from the register 23 and the generator polynomial of M bits (including the case of N bits and 0) output from the selector 13 or the value of all bits is 0 The exclusive-OR operation is performed with the data of (i), and the data of the operation result is stored in the second general-purpose register 24. That is,
1-cycle CRC corresponding to 1-bit transmission / reception data
An operation is performed. Further, the value held in the shift register 23 is shifted left by one bit, and 0 is embedded in the LSB. These operations are, for example, a repetition command (a command indicating that a subsequent command is repeated a predetermined number of times),
It is repeated M times in combination with the CRC operation instruction. Thus, for example, one cycle of the CRC operation (and the shift operation of the shift register 23) can be performed in one machine cycle. The same operation as the operation by the combination of the repetition instruction and the CRC operation instruction may be performed by a single instruction. Also, although the processing speed is slow, the value M
May be set and decremented for each CRC operation in one cycle, and the CRC operation may be repeated until the value becomes zero.

(Step S5) When the M-cycle CRC calculation is completed, it is determined whether the remaining transmission / reception data held in the memory 22 is the final data (whether the remaining data is M bits or less). Specifically, this determination may be made, for example, to determine whether or not the value of a pointer (not shown) indicating the address of the transmission / reception data transferred from the memory 22 to the shift register 23 has become the address of the final data. , X = int ((K−M) / M) where the number of CRC operations in M cycles is counted (down-counted), and M is subtracted from the total number of bits K of the transmitted / received data and integer divided by M. For example, it may be determined whether or not the number of times has been repeated. Further, the counting and determination of the number of times of the CRC operation may be performed by a program command, or may be automatically performed by hardware. (Note that M is subtracted from K because the first M bits are set in the second general-purpose register 24 as initial data.) If the remaining data in the memory 22 is not the final data, , Step S3
To S5 are repeated.

(Step S6) In the above step S6,
If it is determined that the transmission / reception data remaining in the memory 22 is the final data, the final data is stored in the shift register 2.
3 is transferred. Here, as shown in FIG. 3, the number of bits of the final data is a remainder L obtained by subtracting M from the total number of bits K of the transmission / reception data and dividing by M, that is, L = (KM) modM. Since this remainder L is smaller than M, the final data is set in the shift register 23 with the upper bits shifted, and 0 is embedded in the lower bits.

(Step S7) Finally, as in step S4, a CRC operation of M + L cycles is performed. As a result, a CRC operation of M × X + M + L = K cycles is performed in total. (Final CR
Arithmetic and logical operation unit 3 adds remainder L to the number of steps of C operation
The reason why the bit width M of 2 is added is that the operation is repeated until the last bit of the transmission / reception data is shifted to a bit higher than the MSB of the arithmetic and logic unit 32 by one.
This is equivalent to multiplying the transmission / reception data by 2 to the Nth power and performing a CRC operation up to the LSB. Therefore, the value held in the second general-purpose register 24 when the CRC operation of M + L cycles (K cycle in total as described above) is completed in step S7 is the result of the CRC operation for the entire transmitted / received data. Become. Therefore, in the case of transmission, the value held in the second general-purpose register 24 is temporarily stored in, for example, the memory 22 and added to the transmission data, thereby obtaining CRC-coded transmission data. In the case of reception, the second general-purpose register 2
4 is determined by determining whether the value held in the second general-purpose register 2 is 0 or not.
Performs an exclusive OR operation on the value held in 4 and zero data in which all the bit values are 0, and checks whether or not an error is included in the received data by checking whether a zero flag register (not shown) is set. Can be determined.

Next, the above operation will be described with reference to FIGS.

First, an example of encoding will be described. In this example, as shown in FIG. 4, the transmission data before encoding is “100000110101 (binary representation)” (the number of bits K = 12), and the generator polynomial is “10101 (binary representation)”.
(The number of bits N = 5). In this case, 5 cycles of C
The number of repetitions X of the RC operation is as follows: X = int ((KM) / M) = int ((12-5)
/ 5) = 1, the number of bits L of the final data is L = (K−M) modM = (12−5) mod5 = 2, and the number of cycles of the final CRC operation is M + L = 5 + 2 = 7. .

(1) When the CRC operation is started, the generator polynomial “10101” is stored in the first general-purpose register 12.
Is set, the first 5-bit value “10000” of the transmission data is set in the second general-purpose register 24, and the subsequent 5-bit value “011” is set in the shift register 23.
01 "is set.

(2) In the first CRC operation cycle 1,
Since the value of the MSB of the second general-purpose register 24 is “1”,
The selector 13 selects the generator polynomial “10101”, and the generator polynomial and the M of the second general register 24 are selected.
4 bits lower than SB (more precisely, barrel shifter 25
"0000" of the upper 4 bits of the LSB after being shifted left by
The arithmetic logic unit 32 performs an exclusive OR operation on the value “0” of B. The calculation result is “10101”, and the calculation result is stored in the second general-purpose register 24.

(3) The value held in the shift register 23 is shifted left by one bit. Here, FIG.
In the example, the value embedded in the LSB is 0, but this may not be 0. (On the other hand, in the final CRC operation, it is necessary to embed 0 in order to cope with the transmission data being multiplied by 2 to the Nth power.) (4) Thereafter, the same operation is repeated and 5 cycles C
When the RC calculation is completed, the 2 stored in the memory 22
The final data “01” of the bit is transferred to the shift register 23 while the lower bit is filled with “0” and the lower bit is filled with “0”.
Hereinafter, the same operations as the above (2) and (3) are repeated seven cycles in the final CRC calculation.

(5) The value "0001" held in the second general-purpose register 24 when the final CRC operation is completed.
"0" is the CRC calculation result. Therefore, as shown in FIG. 5, the CRC operation result is added to the end of the original transmission data as an error detection code, and becomes 17-bit encoded data ("10000011010101000").

On the other hand, when the data encoded as described above is decoded, the operation is as shown in FIG.
This is the same as (1) to (4) for the above encoding. As a result of this decoding, the CRC operation result becomes "0" as shown in FIG.
0000 ", it is determined that there is no error in the data.

In this example, since the error detection code is added as described above and the bit length of the data is 17 bits, the number of repetitions X of the 5-cycle CRC calculation is X = int ( (KM) / M) = int ((17-5)
/ 5) = 2 times, the number L of bits of the final data is as follows: L = (K−M) modM = (17−5) mod5 = 2. Further, the number of cycles of the final CRC operation is M + L = 5 + 2 = 7, but as shown in FIG.
When the same two-cycle CRC operation as in
, The remainder will remain 0,
If it does not become 0, it does not become 0 thereafter, so even if the operation is stopped in two cycles, the result is the same. However, the configuration may be simplified by repeating seven cycles as described above, that is, by performing the same operation in encoding and decoding.

In the above example, the example in which the bit width of each component is the same is shown. However, the present invention is not limited to this. For example, the first general-purpose register 12 and the arithmetic and logic
The bit width may be different from other components,
Or the arithmetic and logic unit 32 may have different bit widths.

Also, an example in which the transmission / reception data is stored in the memory 22 has been described. For example, when the reception data is input as serial data, the shift register 23 is not provided and the reception data is stored in a buffer (FIFO: first in fir
st out) may be directly supplied to the second general-purpose register 24 or the arithmetic and logic unit 32.

Further, in the above-described CRC operation device, the barrel shifter 25 shifts the input data only by one bit, so that a shift register can be used when there is a margin in the cycle time.

In place of the second general-purpose register 24,
When a register dedicated to the CRC operation is provided, the barrel shifter 25 may not be used by shifting the input / output by one bit.

Further, a memory may be used instead of the first general-purpose register 12 and the second general-purpose register 24.

Further, the switching control of the selector 13 is not limited to the above-described operation using the value of the MSB of the second general-purpose register 24. When the exclusive-OR operation is performed by the arithmetic and logic operation unit 32, A flag register that holds the value of the MSB of the operation result may be provided, and control may be performed by the value held in the flag register. In this case, when the CRC operation of the first cycle is performed, the arithmetic and logic unit 32 is not temporarily shifted to the left by the barrel shifter 25 (or is bypassed).
, The value of the first flag register can be set.

Further, the above-described series of CRC operations for all bits of the transmission / reception data is executed by the microprogram incorporated in the operation instruction execution control unit 41, so that one or a small number of program instructions are used. It may be possible to instruct CRC calculation.

(Embodiment 2) As Embodiment 2, an example of a CRC operation device constituted by hardware including a generator polynomial setting register and capable of applying a generator polynomial of an arbitrary bit length will be described.

As shown in FIG. 6, the CRC operation device includes a CRC operation unit 51 and a generator polynomial supply unit 61.

The CRC operation section 51 (CRC operation means)
Are configured such that D-type flip-flops 52 of predetermined M stages (for M bits) are connected via exclusive OR gates 53. The CRC operation unit 51 performs a CRC operation by inputting operation data one bit at a time. The quotient of the operation result is sequentially output from the last D-type flip-flop 52, and the remainder is CR
When the C operation is completed, the data is output from each D-type flip-flop 52.

The generator polynomial supply section 61 has an M-bit width generator polynomial setting register 6 in which the generator polynomial is stored.
2 (generating polynomial holding means), a selector 63, and a higher-order padding unit 64. According to the output from the last-stage D-type flip-flop 52, the selector 63, like the selector 13 of the first embodiment, stores the value (generation polynomial) stored in the generator polynomial setting register 62 or all bits. Is output as data (“0”) having a value of 0. When the number N of bits of the generator polynomial to be applied is smaller than the bit width M of the generator polynomial setting register 62, the higher-order padding unit 64 fills the upper-order of the generator polynomial and pads the lower bits with 0. Is stored in the generator polynomial setting register 62. Specifically, for example, the left shift may be performed by a shift register, or the left shift may be performed by a shift instruction of a program. In addition, the upper-order padding unit 6
Instead of providing 4, a generator polynomial that has been padded in advance may be input.

With the above configuration,
The number of bits N of the generator polynomial is determined by the generator polynomial setting register 62.
When the bit width M is smaller than the bit width M, the generator polynomial setting register 62
Is embedded in the selector 63, regardless of the output from the D-type flip-flop 52 at the last stage.
Is output. Therefore, the same value as the value output from the preceding D-type flip-flop 52 is output from the exclusive OR gate 53 corresponding to the lower-order bit.
Number of bits of generator polynomial and generator polynomial setting register 62
And the number of stages of the D-type flip-flop 52 are equal to each other, the same result can be obtained. Therefore, regarding the number of bits, the flexibility of the applied generator polynomial can be increased.

[0060]

As described above, according to the present invention, usually,
By using components included in a processor or the like, high-speed CRC calculation can be performed without significantly increasing the circuit scale, and various generator polynomials can be flexibly applied. This has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a CRC calculation device according to a first embodiment.

FIG. 2 is a flowchart illustrating an operation of the CRC operation device according to the first embodiment;

FIG. 3 is an explanatory diagram showing an example of data division in the CRC operation device according to the first embodiment;

FIG. 4 is an explanatory diagram showing a specific example of an encoding operation of the CRC operation device according to the first embodiment.

FIG. 5 is an explanatory diagram showing a specific example of a decoding operation of the CRC operation device according to the first embodiment.

FIG. 6 is a block diagram illustrating a configuration of a CRC calculation device according to a second embodiment.

[Explanation of symbols]

 Reference Signs List 11 generator polynomial supply unit 12 first general-purpose register 13 selector 21 operation data supply unit 22 memory 23 shift register 24 second general-purpose register 25 barrel shifter 31 operation unit 32 arithmetic logic unit 41 operation instruction execution control unit 51 CRC operation unit 52 D-type flip-flop 53 Exclusive OR gate 61 Generator polynomial supply unit 62 Generator polynomial setting register 63 Selector 64 Upper-order padding unit

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yamasaki Saki ▼ 1006 Kadoma, Kazumasa, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Kazuhiro Okabayashi 1006 Kadoma, Kazuma, Kadoma, Osaka Matsushita Electric Industrial In-house F term (reference) 5B001 AA04 AB01 AB03 AC01 AD06 AE02 5J065 AC02 AD04 AH04 AH05 AH06 AH09

Claims (11)

[Claims] 1. A generator polynomial supply means for holding data indicating a generator polynomial and selectively outputting data indicating the generator polynomial and zero data in which all bits are 0, and operation data for performing a CRC operation And arithmetic or logic operation means for performing an exclusive-OR operation on the data indicating the generator polynomial and zero data and the operation data, wherein the generator polynomial supply means includes the arithmetic logic The data indicating the generator polynomial and zero data are selected in accordance with the value of the most significant bit of the operation result by the operation means. The operation data supply means is configured to select the operation result by the arithmetic and logic operation means. The value of a bit lower than the most significant bit of the data is defined as the value of the upper bit, and the value of the most significant bit of the data to be subjected to the CRC operation is defined as the value of the least significant bit. A CRC calculation device configured to output data to be processed as the calculation data. 2. The CRC operation device according to claim 1, wherein said generator polynomial supply means selects a first register holding data indicating said generator polynomial, and selects data indicating said generator polynomial or said zero data. An arithmetic data supply means, a second register for holding the operation result by the arithmetic and logic operation means, and a left bit for the operation result held in the second register. A shifter for shifting and outputting, a memory for holding the unprocessed CRC operation target data, and a part of the unprocessed CRC operation target data transferred from the memory, A shift register that outputs the value of the most significant bit of the stored data and shifts the stored data left by one bit. CRC arithmetic unit to symptoms. 3. The CRC operation device according to claim 1, further comprising an operation instruction execution control means, wherein said operation instruction execution control means responds to a predetermined operation instruction by said generation polynomial supply means. Output of data indicating a polynomial or zero data, output of the operation data by the operation data supply means, and execution of the exclusive OR operation by the arithmetic and logic operation means. CRC calculation device. 4. The CRC operation device according to claim 3, wherein said operation instruction execution control means performs said exclusive OR operation once by said arithmetic logic operation means according to a predetermined operation instruction. A CRC operation device configured to control operations of the generator polynomial supply means, the operation data supply means, and the arithmetic and logic operation means. 5. The CRC operation device according to claim 3, wherein said operation instruction execution control means performs an arithmetic logic operation on all of the unprocessed data subjected to the CRC operation in accordance with a predetermined operation instruction. A CRC configured to control operations of the generator polynomial supply unit, the operation data supply unit, and the arithmetic and logic operation unit for performing the exclusive OR operation by the operation unit. Arithmetic unit. 6. The CRC operation device according to claim 2, further comprising an operation instruction execution control means, wherein said operation instruction execution control means stores all of the data stored in said shift register according to a predetermined operation instruction. The exclusive-OR operation by the arithmetic and logical operation means is performed on the bit value of the arithmetic and logical operation means, so that the operations by the generator polynomial supply means, the operation data supply means, and the arithmetic and logic operation means are controlled. A CRC operation device characterized by being constituted. 7. The CRC operation device according to claim 2, wherein said exclusive OR operation is performed by said arithmetic and logic operation means on all of said unprocessed data to be subjected to CRC operation. A CRC arithmetic unit configured to store a value held in a second register in the memory. 8. The CRC operation device according to claim 2, wherein said exclusive OR operation is performed by said arithmetic and logic operation means on all of said unprocessed data to be subjected to CRC operation. The above-mentioned unprocessed CRC is determined by whether the value held in the second register is 0 or not.
A CRC calculation device configured to determine whether data to be calculated has an error. 9. The CRC operation device according to claim 1, wherein said generator polynomial supply means is configured to execute the operation when the number of bits of data indicating the generator polynomial is smaller than the number of bits that the generator polynomial supply means can hold. , The data indicating the generator polynomial is held in the upper bits, and 0 is set in the lower bits.
Characterized in that it is configured to hold the value of 10. A generator polynomial holding means for holding data indicating a generator polynomial; and CRC operation means for performing a CRC operation based on data indicating the generator polynomial and data to be subjected to a CRC operation. When the number of bits of the data to be indicated is smaller than the number of bits that can be held by the generator polynomial holding means, the generator polynomial holding means holds the data indicating the generator polynomial in upper-order justification, and A CRC operation device characterized in that a value of 0 is retained. 11. A generator polynomial supply step for selectively outputting data indicating a generator polynomial and zero data having all bits of 0, an operation data supply step for outputting operation data for performing a CRC operation, An arithmetic and logic operation step of performing an exclusive OR operation on the data or the zero data indicating the generator polynomial and the operation data, wherein the generator polynomial supply step includes a step of calculating an arithmetic result of the preceding arithmetic and logic operation step. In accordance with the value of the high-order bit, data indicating the generator polynomial or zero data is selected, and the operation data supply step sets the value of a bit lower than the most significant bit of the operation result of the arithmetic and logic operation step to an upper bit And the data with the value of the most significant bit of the unprocessed CRC operation target data as the value of the least significant bit A CRC calculation method characterized by outputting as calculation data.