JP2001358577A - Cmos inverter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a CMOS inverter circuit in which off-leak current of individual transistors is prevented, while achieving power consumption, by sensing an input signal and controlling the substrate potential of a transistor forming a CMOS invertet section in real time. SOLUTION: The CMOS inverter circuit comprises a CMOS inverter section 1 comprising a PMOS.Q1 and an NMOS.Q2, and a substrate potential control section 2 being connected between the substrates of Q1 and Q2. The control section 2 comprises a PMOS.Q3, an NMOS.Q4, and a capacitive element Cd wherein off-leak is prevented by increasing the threshold voltage of the transistor Q1 or Q2 on the turn off side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CMOS inverter circuit, and more particularly to a CMOS inverter circuit for controlling a substrate potential such as a low power supply voltage device.

[0002]

2. Description of the Related Art In recent years, the performance and performance of LSIs have been increased due to the miniaturization of processes, and the performance has been improved. However, power consumption of devices has been regarded as a problem.

[0003] In particular, interest in LSI power management is high overseas, and measures are being taken against power consumption in various fields. As an example, a CPU for a mobile PC of a major CPU manufacturer in North America is
The power consumption is reduced by lowering the power supply voltage and operating frequency of the PU and keeping the charge / discharge current of the device low. As described above, as the speed of LSIs increases, reducing power consumption has become an important issue.

[0004] Further, as the process becomes finer and faster,
The device voltage has been rapidly reduced, and the threshold value (Vt) of the transistor has been rapidly reduced. For example, 0.1
In the 8 μm process, the power supply voltage becomes 1.8 V or less,
Since the above-mentioned Vt is close to 0.3 V, the transistor can no longer be completely turned off in the process. That is, the off-leak current is regarded as a problem due to the decrease in Vt.

[0007] Originally, the power consumption of the device should be reduced due to the reduction in the voltage of the device. However, the power consumption itself is in danger due to the off-leak current.

Further, power consumption is increasing to several watts due to high integration (7M gate) and high speed operation (1 GHz) of devices. For this reason, reducing the power consumption while preventing off-leakage is an important issue from the viewpoint of reliability such as migration.

A CMO with such an off-leak measure
The S circuit is known, for example, from Japanese Patent Application Laid-Open No. 7-95032.

FIG. 4 is a CMOS inverter circuit diagram showing an example of such a conventional device. As shown in FIG.
The OS inverter circuit includes a power supply voltage VDD and a ground voltage GN.
P channel MOS with source and substrate connected between D
Transistor Q5 and N-channel MOS transistor Q
6 are connected in this order, each gate is connected to the input terminal IN, and each drain is connected to the output terminal OUT. The inverter circuit further includes an N-channel MOS transistor Q7 having a drain and a substrate connected, a source connected to GND, and a gate connected to an input terminal;
A coupling capacitance element Cs connected between the gates of the channel MOS transistors Q6 and Q7 and the substrate is provided. Note that CL is a load capacitance element.

In this CMOS inverter circuit, when input voltage VIN supplied to input terminal IN falls below threshold voltage (Vt) of N-channel MOS transistor Q7, N-channel MOS transistor Q6 is activated by coupling capacitance element Cs. A negative substrate voltage is applied to the substrate.

The operation of this CMOS inverter circuit will be described below. VDD is 1.8 V, GND is 0
It is assumed that V and Vt of each MOS transistor have the following values. Vbs is a back bias voltage.

Q5: -0.3 V (Vbs = 0 V) Q6: +0.3 V (Vbs = 0 V), +0.6 V (Vb
s = -0.3V) Q7: + 0.3V (Vbs = 0V) Now, the input voltage VIN of the CMOS inverter circuit is 0.3
When the voltage drops to V, the N-channel MOS transistor Q7 is turned off, so that the P-well, which is the substrate of the N-channel MOS transistor Q7, is disconnected from GND and enters a floating state. And the input voltage VIN is 0.3V
When the voltage drops further, the N-channel MOS transistor Q
6 and the capacitance of the gate capacitance C7 and the coupling capacitance Cs of the N-channel MOS transistor Q7, the voltage of the P-well decreases, and the Vt of the N-channel MOS transistor Q6 increases due to the substrate bias effect. Thereby, the source-drain leakage current in the weak inversion region of N-channel MOS transistor Q6 is reduced.

FIG. 5 is a voltage level characteristic diagram of the output terminal and the point B in FIG. As shown in FIG. 5, VOH and VOL are a high-level potential and a low-level potential of the output terminal OUT, respectively, and VB is an N-channel MOS.
This is the substrate potential of the transistor Q6. After the supply of the input potential to the input terminal IN is started, a negative voltage of minus 0.19 V is generated in the substrate potential at 50 μS.
, The negative potential rises from about the point where the voltage drops to about 0.03 V near 94 V at 94 μS. That is, in the circuit shown in FIG. 4 described above, the substrate potential VB increases with time, and the threshold value Vt of the N-channel MOS transistor Q6 returns to the original value.

FIG. 6 is a waveform diagram of spice simulation of off-leak current of the MOS transistor in FIG. As shown in FIG. 6, in the above-described CMOS inverter circuit, the off-leak current Iof obtained by simulation is approximately -0.420 μA.

[0014]

SUMMARY OF THE INVENTION The above-mentioned conventional CMO
The S inverter circuit can generate a negative potential as the substrate potential, but since the negative potential rises halfway and becomes close to 0 V, the threshold value of the transistor returns to the original value. Therefore, it is difficult to completely prevent the off-leak current of the transistor in the CMOS inverter circuit, and at the same time, there is a problem that the power consumption during standby cannot be reduced.

Further, since only a negative potential can be generated in the conventional CMOS inverter circuit, the off-leak current is effective only for a short time when the N-channel MOS transistor Q6 is turned off at a high level.
This cannot be handled when the transistor Q5 is off. Therefore, there is a problem that the effect of off-leakage countermeasures is reduced by half, and the power consumption can be reduced only by about half the circuit of the LSI.

It is an object of the present invention to control a substrate potential of a transistor forming an inverter section in real time by sensing an input signal, thereby preventing an off-leak current of each transistor and realizing a low power consumption CMOS.
An inverter circuit is provided.

[0017]

According to the CMOS inverter circuit of the present invention, a first P-channel MOS transistor and a first N-channel MOS transistor are connected between a power supply and a ground, and the gates of both transistors are commonly connected. CM that supplies an input signal to the input terminal and extracts an output from a commonly connected drain of both transistors
An OS inverter unit, and a substrate potential control unit connected between the substrates of the first P-channel MOS transistor and the first N-channel MOS transistor, wherein the first P-channel MOS transistor or the first The threshold voltage of the off-side transistor of the N-channel MOS transistor is raised to prevent off-leakage.

Further, in the CMOS inverter circuit according to the present invention, the CMOS inverter unit includes the first P-channel MOS transistor and the first N-channel MOS transistor.
The substrate of the OS transistor is formed independently.

In the CMOS inverter circuit according to the present invention, the substrate potential control section connects a source to a power supply and a drain to the substrate of the first P-channel MOS transistor, and supplies the input signal to a gate. A second P-channel MOS transistor, a second N-channel MOS transistor having a source connected to the ground and a drain connected to the substrate of the first N-channel MOS transistor, and supplying the input signal to a gate; P-channel MOS transistor and the N-th
And a capacitor connected between the drains of the P-channel MOS transistors.

In the present invention, the second P-channel MOS transistor and the second N-channel MOS transistor
The S transistor is formed by connecting the drain and the substrate.

In the present invention, the first and second P
Channel MOS transistor and the first and second N
The channel MOS transistors are formed such that the substrate potentials are made equal and the boosted voltage and the step-down voltage generated in the substrate potential control section are held by the capacitance element.

Further, the substrate potential control section in the present invention uses the same power supply voltage as the power supply of the CMOS inverter section to prevent off-leakage of both the first P-channel MOS transistor and the first N-channel MOS transistor. It is formed so that.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS This embodiment includes a first P-channel MOS transistor and a first N-channel MOS transistor connected between a power supply and a ground, and has both gates as input terminals and both drains. Is connected to an output terminal, a normal CMOS inverter section, and this CMOS
And a control unit for controlling the substrate potential of each first MOS transistor in the inverter unit. In addition, the control unit includes a second P-channel MOS transistor having the source connected to the power supply, the drain and the substrate connected to each other, and the gate connected to the input terminal, the source connected to the ground, the drain connected to the substrate and the gate connected to the input terminal. A second N-channel MOS transistor connected to the terminal; and a coupling capacitance element connected between the drains of the second P-channel MOS transistor and the second N-channel MOS transistor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a CMOS inverter circuit diagram showing one embodiment of the present invention. As shown in FIG.
In the present embodiment, the P-channel MOS transistors Q3 and N3 of the control unit 2 are used to control the substrate potential (potential at points A and B) for the normal CMOS inverter unit 1.
Switching is performed by the capacitive element Cd connected between the drains of the channel MOS transistors Q4. At this time, the capacitance element Cd is a P-channel MOS transistor Q3
And the potential difference between the gate of N-channel MOS transistor Q4, that is, input terminal IN and the substrate,
The step-up potential and the step-down potential generated by the control unit 2 can be held for a long time. Then, the P-channel MOS transistors Q1 and N in the normal CMOS inverter section 1
The above-described boost potential and step-down potential are applied to the substrate of the channel MOS transistor Q2 to control the threshold Vt of the P-channel MOS transistor Q1 or the N-channel MOS transistor Q2 which is turned off, thereby preventing an off-leak current. .

Here, CMOS inverter unit 1 includes a P-channel MOS transistor Q1 and an N-channel MOS transistor Q1.
The substrate of the transistor Q2 is formed separately and independently, and the power supplies of the CMOS inverter unit 1 and the substrate potential control unit 2 use the same power supply voltage VDD.

Hereinafter, a specific embodiment will be described with reference to FIG. In this embodiment, the power supply voltage VDD and the ground voltage GND
, A P-channel MOS transistor Q1 and an N-channel MOS transistor Q2 are connected in this order, each gate is connected to an input terminal IN, and each drain is connected to an output terminal O
A CMOS inverter 1 connected to the UT, a gate connected to the input terminal IN, a source connected to VDD, and a drain and substrate connected to the CMOS inverter 1
A P-channel MOS transistor Q3 connected to the substrate of the P-channel MOS transistor Q1, a gate connected to the input terminal IN and a source connected to GND, and a drain and a substrate connected to the N-channel MOS transistor Q2 of the CMOS inverter unit 1. It has an N-channel MOS transistor Q4 connected to the substrate, and a substrate potential control section 2 provided with a drain of the P-channel MOS transistor Q3 and a coupling capacitance element Cd connected between the drains of the N-channel MOS transistor Q4. I have. Such CMO
In the S-inverter circuit, when the input voltage VIN supplied to the input terminal IN falls below the threshold voltage Vt of the N-channel MOS transistor Q4, the substrate of the N-channel MOS transistor Q2 of the CMOS inverter unit 1 becomes negative due to capacitive coupling. Is applied. When the input voltage VIN at the input terminal IN rises above Vt of the P-channel MOS transistor Q3, a substrate voltage higher than VDD is applied to the substrate of the P-channel MOS transistor Q1 of the CMOS inverter unit 1 by capacitive coupling. It was made.

Next, a specific operation of the CMOS inverter circuit will be described. Here, VDD is 1.8 V,
It is assumed that GND is 0 V, and the threshold voltage of each MOS transistor has the following value.

Q1: -0.3V (Vbs = 0V),-
0.6V (Vbs = + 0.3V) Q2: + 0.3V (Vbs = 0V), + 0.6V (Vb
s = -0.3V) Q3: -0.3V (Vbs = 0V) Q4: + 0.3V (Vbs = 0V) Now, the input voltage VIN of the CMOS inverter circuit is 0.3.
When the voltage drops to V, the N-channel MOS transistor Q4 is turned off, and the P-well serving as the substrate of the N-channel MOS transistor Q4 is disconnected from GND and enters a floating state. When the input voltage VIN further decreases, the gate capacitance of the N-channel MOS transistor Q2 (hereinafter, referred to as C2), the gate capacitance of the N-channel MOS transistor Q4 (hereinafter, referred to as C4), and the capacitance of the capacitance element Cd The coupling lowers the voltage on the P-well. As a result, the threshold value Vt of N-channel MOS transistor Q2 increases due to the substrate bias effect. Thereby, the leak current between the source and the drain in the weak inversion region of N-channel MOS transistor Q2, that is, the off-leak current is reduced.

Conversely, when the input voltage VIN rises to 1.5 V, the gate capacitance of the P-channel MOS transistor Q1 (hereinafter referred to as C1) and the gate capacitance of the P-channel MOS transistor Q3 (hereinafter referred to as C3) )
Due to the capacitive coupling with the capacitive element Cd, the voltage of the N well increases. As a result, the substrate voltage of P-channel MOS transistor Q1 increases due to the substrate bias effect, and the source-drain leakage current similarly decreases.

FIG. 2 is a diagram showing the output terminal and voltage level characteristics at points A and B in FIG. As shown in FIG. 2, VOH and VOL are a high level potential and a low level potential of the output terminal OUT, respectively, and VA is a P-channel MOS.
The substrate potential of the transistor Q1, VB is an N-channel MOS
This is the substrate potential of the transistor Q2. Even if the supply of the input potential to the input terminal IN is started, that is, even if the time elapses, the same section (for example, the time of 0.1 to 0.15 m
In the S section or the 0.15 to 0.2 mS section), the substrate potentials VA and VB do not change. Here, a case where VA = 2.09 V and VB = 0.22 V is shown as an example. This allows the substrate potential control unit 2 to raise and lower the voltage, so that the off-leak current can be prevented even when the P-channel MOS transistor Q1 and the N-channel MOS transistor Q2 are off. As described above, in the present embodiment, the threshold voltage Vt of each transistor can be continuously increased because the substrate potential does not change within the same section even after a lapse of time, and therefore, the off-leak current can be prevented. Can be.

As is clear from FIG. 2, the potentials of VA and VB exceed 100 nS and can maintain the reduced potential and the boosted potential even after a lapse of 50 μS. Power consumption during standby can be reduced.

FIG. 3 is a spice simulation waveform diagram of an off-leak current of the MOS transistor in FIG. As shown in FIG. 3, in the above-described CMOS inverter circuit, the output voltage level VOH at the time of the high level is 1.8 V, and the off-leak current Iof obtained by the simulation is approximately −0.110 μA. For this reason, the above-described conventional example of FIG.
Compared with 2 μA), according to the circuit of the present embodiment, it can be reduced by about 74%.

In this embodiment, since the threshold voltage can be controlled for each function block (function block), the conventional LSI (Vt-C
Unlike a circuit that prevents off-leak only at the standby time when the MOS type is not operating, it is possible to prevent off-leakage of the transistor that is not operating not only at the time of standby but also at the time of using the LSI. Power consumption at the time can be reduced. Even when such an LSI is used, it is said that about 30 to 40% of the transistors always operate, and that 0.18 μm
Considering that the off-leak current of a transistor having a gate width of 10 μm in the m process is as large as about 0.4 μA, the effect on an LSI which is becoming larger and more integrated in recent years is enormous.

Further, unlike the Vt-CMOS type which is generally considered, the present embodiment does not require a special power supply for preventing off-leak current, and
An off-leak current can be prevented with a single power supply required for operation.

[0035]

As described above, the CMOS of the present invention is used.
The inverter circuit senses an input signal and controls the substrate potential of the transistor forming the inverter section in real time, thereby preventing off-leak current of each transistor and realizing low power consumption.

[Brief description of the drawings]

FIG. 1 is a CMOS inverter circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing output terminal and voltage level characteristics at points A and B in FIG. 1;

FIG. 3 is a waveform diagram of spice simulation of off-leak current of the MOS transistor in FIG. 1;

FIG. 4 is a CMOS inverter circuit diagram showing an example of the related art.

FIG. 5 is a voltage level characteristic diagram of an output terminal and a point B in FIG.

6 is a waveform diagram of spice simulation of off-leak current of the MOS transistor in FIG.

[Explanation of symbols]

 Reference Signs List 1 CMOS inverter unit 2 Control unit Q1, Q3 P-channel MOS transistor Q2, Q4 N-channel MOS transistor Cd coupling capacitance element VOH output high-level potential VOL output low-level potential VA, VB substrate potential Iof off-leakage current

Claims (6)

[Claims] 1. A first P-channel MOS transistor and a first N-channel MOS transistor are connected between a power supply and a ground, an input signal is supplied to a commonly connected gate of both transistors, and both transistors are commonly used. Extract output from connected drain C
A MOS inverter unit, and a substrate potential control unit connected between the substrates of the first P-channel MOS transistor and the first N-channel MOS transistor, wherein the first P-channel MOS transistor or the first
A threshold voltage of an off-side transistor of the N-channel MOS transistor is increased to prevent off-leakage. 2. The CMOS inverter unit according to claim 1, wherein:
2. The CMOS inverter circuit according to claim 1, wherein the substrates of said P-channel MOS transistor and said first N-channel MOS transistor are formed independently. A second P-channel MOS transistor having a source connected to a power supply and a drain connected to a substrate of the first P-channel MOS transistor, and supplying the input signal to a gate; , The source to ground and the drain to the first N-channel MO.
A second N-channel MOS transistor connected to the substrate of the S transistor and supplying the input signal to the gate; and a capacitor connected between the drains of the second P-channel MOS transistor and the N-th P-channel MOS transistor 2. The CMO according to claim 1, wherein the CMO is formed with an element.
S inverter circuit. 4. The second P-channel MOS transistor and the second N-channel MOS transistor,
4. The CMOS inverter circuit according to claim 3, wherein the drain and the substrate are connected to each other. 5. The first and second P-channel MOS transistors and the first and second N-channel MOS transistors have equal substrate potentials, respectively, and a boosted voltage and a reduced voltage generated by the substrate potential control unit. 4. The CMOS inverter circuit according to claim 3, wherein the voltage is held by the capacitance element. 6. The first potential control section uses the same power supply voltage as the power supply of the CMOS inverter section, and
4. The CMOS inverter circuit according to claim 3, wherein off-leakage of both a channel MOS transistor and said first N-channel MOS transistor is prevented.