JP2001358567A5 - - Google Patents
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- JP2001358567A5 JP2001358567A5 JP2000178426A JP2000178426A JP2001358567A5 JP 2001358567 A5 JP2001358567 A5 JP 2001358567A5 JP 2000178426 A JP2000178426 A JP 2000178426A JP 2000178426 A JP2000178426 A JP 2000178426A JP 2001358567 A5 JP2001358567 A5 JP 2001358567A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000178426A JP2001358567A (ja) | 2000-06-14 | 2000-06-14 | 半導体集積回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000178426A JP2001358567A (ja) | 2000-06-14 | 2000-06-14 | 半導体集積回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001358567A JP2001358567A (ja) | 2001-12-26 |
| JP2001358567A5 true JP2001358567A5 (enExample) | 2005-10-13 |
Family
ID=18679856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000178426A Pending JP2001358567A (ja) | 2000-06-14 | 2000-06-14 | 半導体集積回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001358567A (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102008032876B4 (de) * | 2008-07-14 | 2010-04-08 | Sew-Eurodrive Gmbh & Co. Kg | Verfahren, Schaltungsanordnung und Brückenschaltung |
| JP5530669B2 (ja) * | 2009-07-01 | 2014-06-25 | 三菱電機株式会社 | 半導体回路 |
| US8633745B1 (en) * | 2012-08-30 | 2014-01-21 | Allegro Microsystems, Llc | Circuits and related techniques for driving a high side of a half bridge circuit |
| CN105144584B (zh) * | 2013-04-18 | 2017-07-18 | 夏普株式会社 | 电平移位电路 |
| JP6107698B2 (ja) * | 2014-02-13 | 2017-04-05 | 株式会社デンソー | スイッチング素子駆動装置 |
| JP2018524952A (ja) | 2015-04-21 | 2018-08-30 | ユニバーシティー オブ ロチェスター | クローキングシステム及び方法 |
| US11006090B2 (en) | 2016-08-05 | 2021-05-11 | University Of Rochester | Virtual window |
| US10496238B2 (en) | 2016-08-22 | 2019-12-03 | University Of Rochester | 3D display ray principles and methods, zooming, and real-time demonstration |
| US10230356B2 (en) | 2017-02-27 | 2019-03-12 | Allegro Microsystems, Llc | High-side output transistor circuit |
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2000
- 2000-06-14 JP JP2000178426A patent/JP2001358567A/ja active Pending