JP2001351912A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method, capable of preventing impurities from being separated out on the surface of an interlayer insulating film and short-circuiting between electrodes. SOLUTION: Electrodes are formed on a semiconductor substrate, and a BPSG film containing impurities of first concentration is deposited on a base, on which a slit having an aspect ratio 4 or larger is formed between the electrodes and subjected to a first annealing process, and in succession, another BPSG film, containing impurities of second concentration, is deposited on the former BPSG film and subjected to a second annealing process for the formation of an interlayer insulating film, in a method of manufacturing a semiconductor device. Problems of preventing impurities from being deposited on the surface of an interlayer insulating film and short-circuiting from between electrodes are solved by the above processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an interlayer insulating film in order to prevent deposition of impurities in the interlayer insulating film and short-circuit between electrodes. The present invention relates to a method for manufacturing a semiconductor device having features.

[0002]

2. Description of the Related Art Conventionally, silicon oxide (SiO ₂ ) has been widely used as an insulating film between conductive wirings in a semiconductor device such as an LSI. In particular, as an interlayer insulating film formed below the metal wiring (on the substrate side), phosphorus (P) and boron (B) are used in order to enable flattening by heat treatment.
Doped BPSG film (boro-phospho silicate glas
sfilm) is widely used. However, BPS
When the concentration of the impurities of phosphorus and boron contained in the G film increases, there is a problem that the impurities are deposited on the surface of the BPSG film. To cope with such a problem, a BPSG film containing a high concentration of impurities and having a large thickness is deposited on a substrate, annealed, a polycrystalline polysilicon film is deposited on the BPSG film, and annealing is performed again. A method has been proposed in which impurities are diffused out of the polycrystalline polysilicon film. Hereinafter, this conventional example will be described with reference to FIG.

[0003] First, an electrode wiring 22 and a thermal oxide film (not shown) are formed on a semiconductor substrate 21, and a high concentration of phosphorus (P) and boron (B) (phosphorus concentration 8) is formed as an interlayer insulating film.
(FIG. 3 (a)). Next, by performing a heat treatment at a medium temperature (about 800 ° C.) for 15 minutes, the BPSG film 23 is reflowed and flattened [FIG. 3B]. Next, BPS
A polycrystalline polysilicon film 24 having a thickness of about 200 nm is deposited on the G film 23 by LPCVD (FIG. 3C).
Next, annealing is performed at a medium temperature (about 800 ° C.), and the BPS
The phosphorus (P) and boron (B) doped in the G film 23 are diffused into the polycrystalline polysilicon film 24 [FIG.
(D)]. Next, by removing the polycrystalline polysilicon film 24, the concentration of phosphorus (P) and boron (B) existing near the surface of the BPSG film 23 can be reduced to about 1 to 3 wt% [FIG. (E)]. Thereafter, an Al wiring is formed by a known semiconductor device manufacturing process to
Had been manufactured. As described above, the deposition of impurities such as phosphorus and boron on the surface of the BPSG film was prevented, and a flat interlayer insulating film was formed.

[0004]

However, as the fine processing of the device progresses and the aspect ratio of the slit portion between the electrodes on the semiconductor substrate becomes larger, for example, the aspect ratio becomes 4 or more. In such a case, the above method has a problem that the polycrystalline polysilicon film cannot be completely buried in the slit portion, and impurities cannot be out-diffused in that portion. FIGS. 4 to 6 are provided to explain this problem, and show a high impurity concentration (boron concentration of 5 wt.
%, Phosphorus concentration 8 wt%)
FIG. 9 is a cross-sectional view at the time when the polycrystalline polysilicon film is removed after the SG film is annealed to reduce the impurity concentration on the BPSG film surface 35 by out-diffusing the impurities into the polycrystalline polysilicon film. .

[0005] As can be seen from FIG. 4, when the BPSG film 33 containing a high concentration of impurities is formed thick at a time on a base having an increased aspect ratio of the slit portion,
A void 25 is generated in the slit. In this state, a contact hole is opened, a metal is buried, and a first metal wiring 26, an insulating film 18, a second metal wiring 20, and a protective film 31 are formed (FIG. 5). 25 / Ti / Ti as barrier metal
There is a problem that N or the like is sputtered, and a short circuit occurs between the electrodes W (FIG. 6). The present invention has been made in order to solve such a problem, and does not require a complicated process such as out-diffusion of a high-concentration impurity in a polycrystalline polysilicon film. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing precipitation of impurities on a film surface and preventing a short circuit between electrodes even when an aspect ratio of a slit between electrodes is increased.

[0006]

According to the present invention, a plurality of electrodes are formed on a semiconductor substrate, and a first electrode is formed on a base having a slit having an aspect ratio of 4 or more between the electrodes. Depositing a BPSG film having an impurity concentration,
A semiconductor, wherein a first annealing step is performed, a BPSG film having a second impurity concentration is deposited on the BPSG film, and an interlayer insulating film is formed by the second annealing step. A method for manufacturing a device is provided.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Semiconductor substrates which can be used in the method of the present invention include, for example, elemental semiconductor substrates such as silicon and germanium, substrates made of compound semiconductors such as GaAs and InGaAs, SOI substrates and multilayer SOI substrates.
Various substrates such as an I substrate can be used. Among them, a silicon substrate is preferable. The material of the electrode that can be used in the method of the present invention is not particularly limited as long as it is formed of a conductive material. For example, an amorphous, single crystal, or polycrystalline N-type or P-type elemental semiconductor ( For example, silicon, germanium, etc.) or a compound semiconductor (eg, GaAs, InP, ZnSe, CsS)
Etc.); metals such as gold, platinum, silver, copper, aluminum and copper;
Refractory metals such as titanium, tantalum, and tungsten; silicide and polycide with refractory metals; ITO, Sn
It can be formed of a single-layer film or a laminated film of a transparent conductor such as O ₂ or ZnO. The thickness of the electrode can be set according to its function, for example, 200 to 550 n
m. The shape of the electrode is not particularly limited, and may be various shapes such as a rectangle, a stripe, an island, and a lattice. Further, a sidewall made of a thermal oxide film or a SiN film may be formed on the electrode.

[0008] The slit portion between the electrodes has an aspect ratio of 4 or more. Here, the aspect ratio is obtained by dividing the thickness of the electrode by the width between the electrodes. Needless to say, the width between the electrodes is the distance between the adjacent electrodes. For example, as shown in FIG. 1B, when a sidewall or a thermal oxide film is formed on the electrodes, The width between the sidewalls or between the thermal oxide films is defined as the width between the electrodes. The electrodes are, for example,
A film of a conductive material is formed on the entire surface of a semiconductor substrate by various known methods such as a CVD method, a sputtering method, and a vapor deposition method, and then a film of the conductive material is formed by a known method, for example, a photolithography and etching process. Can be formed by patterning in the shape of

[0009] The interlayer insulating film that can be used in the method of the present invention is formed by laminating a BPSG film having a first impurity concentration and a BPSG film having a second impurity concentration. The BPSG film having the first impurity concentration preferably contains impurities of phosphorus (P) and boron (B) at substantially the same as or higher than the BPSG film having the second impurity concentration described later. Specifically, the phosphorus concentration is about 4.0 to 10 wt%, for example, 4.5,
5.0, 5.5, 6.0, 6.5, 7.0, 7.5,
8.0 wt%. The boron concentration is 3 to 6 wt.
%, For example, 3.5, 4.0, 4.5, 5.0 wt%
It is. The thickness of the BPSG film having the first impurity concentration is preferably about 100 to 250 nm, for example, about 200 nm.
nm. If the thickness is smaller than 100 nm, the slit portion is not embedded, and if the thickness is larger than 250 nm,
It is not preferable because voids are easily generated.

After depositing a BPSG film having a first impurity concentration, a first annealing is performed. The first annealing is preferably performed at substantially the same or a higher temperature as a second annealing described later. Specifically, in a nitrogen atmosphere,
Medium temperature of about 700 to 850 ° C, preferably 725 to 80
Performed at 0 ° C. for about 30 minutes, the BPSG film having the first impurity concentration is reflowed and buried in the slit between the electrodes. The BPSG film having the second impurity concentration removes impurities of phosphorus (P) and boron (B) from the first impurity.
Of the BPSG film having an impurity concentration of about the same as or lower than that of the BPSG film. The thickness of the BPSG film having the second impurity concentration is not particularly limited.
It is preferably about 1500 nm, for example, 1300 nm. After the formation of the BPSG film having the second impurity concentration, a second annealing is performed.

The second annealing is performed, for example, in a nitrogen atmosphere at a low temperature of about 600 to 750 ° C., preferably 625 to 750 ° C.
This is performed at 725 ° C. for about 30 minutes, and the BPSG film having the second impurity concentration is reflowed. The interlayer insulating film that can be used in the method of the present invention includes first and second interlayer insulating films.
Although a BPSG film having a third impurity concentration is laminated, a BPSG film having a third impurity concentration may be further laminated. The BPSG film having the first and second impurity concentrations is formed by a known method such as a normal pressure CVD method or a low pressure CVD method, respectively. Next, a contact is formed in the interlayer insulating film by a known method such as a photolithography and etching process, a first metal wiring is formed on the contact and the interlayer insulating film, and an insulating film is formed on the first metal wiring. , Via contact, second metal wiring and protective film, respectively,
A semiconductor device is manufactured.

As the first and second metal wirings, Au
Cu and the same conductive material as the above-described electrode are used, and the conductive material is formed over the entire surface of the insulating film by various methods such as a CVD method, a sputtering method, and an evaporation method.
For example, a film of a conductive material can be patterned into a desired shape by a known method such as a photolithography and etching process. The insulating film and the protective film can be formed by depositing a silicon oxide film, a PSG film, a BSG film, a BPSG film, or the like by a known method such as a low pressure CVD method or a normal pressure CVD method.

[0013]

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited thereto. Example 1 After forming a gate electrode wiring 2 (“electrode” according to the present invention) on a P-type silicon substrate 1 (“semiconductor substrate” according to the present invention) so that the aspect ratio of the slit portion is 4 or more. Then, a thermal oxide film (not shown) is formed [FIG. 1 (a)].
Next, a SiN film is deposited to a thickness of 70 nm, etched back by anisotropic etching, and a gate electrode wiring 2 is formed.
A sidewall 3 of a SiN film is formed on the sidewall of FIG.
(B)].

Next, an N ⁺ layer for the source / drain of the transistor is formed by ion-implanting phosphorus or arsenic into the P-type silicon substrate 1 (not shown). Next, the impurity concentration is relatively low (boron concentration of 3.5 wt.
%, Phosphorus concentration 4.5 wt%) After the BPSG film 4 having the first impurity concentration is deposited to a thickness of 200 nm by the CVD method (FIG. 1C), the first annealing is performed in a nitrogen atmosphere. At 750 ° C. for 30 minutes, the BPSG film 4 having the first impurity concentration is reflowed and buried in the slit portion of the gate electrode wiring 2 (FIG. 1E).

Subsequently, a BPS having a first impurity concentration
BP having the second impurity concentration of the same impurity concentration as the G film 4 (boron concentration: 3.5 wt%, phosphorus concentration: 4.5 wt%)
An SG film 5 is deposited at a thickness of 1300 nm by a CVD method, and a second annealing is performed at 700 ° C. in a nitrogen atmosphere for 30 minutes.
And the surface is flattened [FIG. 1 (e)]. Thereafter, the contact 6, the first-layer AuCu wiring 12 (the "first metal wiring" in the present invention), the insulating film 8, the via contact 9, and the second-layer AuCu
A semiconductor device is manufactured by sequentially forming the wiring 10 (the “second metal wiring” in the present invention) and the protective film 11 (FIG. 2).

The reason why the first annealing is performed at a temperature higher than the second annealing temperature is that the impurity concentration of the BPSG film 4 having the first impurity concentration is relatively low.
This is to ensure that the melt is completely performed. Since the interlayer insulating film formed according to this embodiment is formed of a BPSG film having a relatively low impurity concentration, the deposition of impurities such as phosphorus and boron does not occur on the surface of the BPSG film. In addition, since the thickness of the BPSG film having the first impurity concentration is reduced, no void is generated, and a short circuit between the electrodes can be suppressed.

Embodiment 2 The impurity concentration of the BPSG film 4 having the first impurity concentration is increased (boron concentration: 5.0 wt%, phosphorus concentration: 8.0 wt%).
%), And a semiconductor device is manufactured in the same manner as in Example 1 except that the first annealing is performed at the same temperature (700 ° C.) as the second annealing temperature. B having the first impurity concentration
Even when the impurity concentration of the PSG film 4 is high, if the first annealing is performed at a temperature approximately equal to the second annealing temperature (700 ° C.), deposition of phosphorus, boron, and the like on the surface of the interlayer insulating film is prevented. be able to.

[0018]

According to the method of the present invention, it is possible to prevent the deposition of impurities on the surface of the interlayer insulating film.
Since an insulating film can be buried in a slit portion having an aspect ratio of 4 or more between electrodes without generating a void, a semiconductor device capable of preventing a short circuit between electrodes can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a step of forming an interlayer insulating film in the present invention.

FIG. 2 is a schematic sectional view of a semiconductor device manufactured by the method of the present invention.

FIG. 3 is a schematic cross-sectional view showing a step of forming an interlayer insulating film in a conventional technique.

FIG. 4 is a schematic sectional view of a semiconductor device showing a problem in a conventional technique.

FIG. 5 is a schematic sectional view of a semiconductor device showing a problem in a conventional technique.

6 is a sectional view taken along line AA in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 21 Semiconductor substrate 2, 22 Electrode wiring 3 SiN side wall 4, BPSG film 5 having the first impurity concentration 5, BPSG film 6 having the second impurity concentration 6, 16 Contact 8, 18 Insulating film 9 Via contact 10, Reference Signs List 20 second metal wiring 11, 31 protective film 12, 26 first metal wiring 23 BPSG film 24 polycrystalline polysilicon film 25 void 33 high concentration BPSG film 34 relatively low concentration BPSG film 35 BPSG film surface

Continued on the front page F-term (reference)

Claims (4)

[Claims] A plurality of electrodes formed on a semiconductor substrate;
Depositing a BPSG film having a first impurity concentration on a base having a slit portion having an aspect ratio of 4 or more between the electrodes and performing a first annealing; BPSG having second impurity concentration
A method for manufacturing a semiconductor device, comprising: depositing a film and forming an interlayer insulating film by performing a second annealing. 2. The method according to claim 1, wherein the BPSG film having the first impurity concentration has substantially the same or a higher impurity concentration as the BPSG film having the second impurity concentration. 3. The method according to claim 1, wherein the first annealing is performed at substantially the same or a higher temperature as the second annealing. 4. A BPSG film having a first impurity concentration is deposited to a thickness of 100 to 250 nm.
The production method according to any one of the above.