JP2001345455A - Optical semiconductor element carrier, and its mounting structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized optical semiconductor element carrier and its mounting structure which is suitable to the highly accurate mounting of such an optical semiconductor element as a surface-received light-emitting semiconductor element and is excellent in its productivity and its high-frequency characteristic. SOLUTION: In an optical semiconductor element carrier C comprising an optical semiconductor element 2 mounted on a base 1 made of single-crystal silicon, the base 1 has an optical semiconductor element mounting surface comprising [110] plane or [100] plane, whereon the optical semiconductor element 2 is mounted and has at least two inclined surfaces A2, A3 comprising [111] plane which are positioned on the rear-surface side of the base 1 in the case of the standing of the base 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor element carrier used in, for example, an optical fiber communication system or a private optical communication system (optical LAN) and a mounting structure thereof.
In particular, the present invention relates to a device using a surface emitting semiconductor device or a surface light receiving semiconductor device as an optical semiconductor device.

[0002]

2. Description of the Related Art In recent years, practical use of optical fiber communication has started in the field of CATV and public communication. Hitherto, high-speed and high-reliability optical semiconductor modules have been realized in a module structure called a coaxial type or a butterfly type, and these have already been put to practical use mainly in a region called a trunk line system.

On the other hand, recently, Si (silicon)
Optical modules using the technology of passively aligning and mounting optical semiconductor elements and fibers on a sub-substrate (or also referred to as a Si platform) made of a single crystal with high mechanical accuracy only have been actively developed. Therefore, a reduction in size, height, and cost is required.

Hereinafter, a conventional photodiode mounting structure will be described.

FIG. 6 shows a base 41 for mounting a photodiode. The base 41 has electrode patterns 411 and 412 for the anode electrode and the cathode electrode of the photodiode formed at least on any two adjacent surfaces, and each of the electrode patterns is electrically connected at the boundary between the surfaces. Is done.

FIG. 7 shows a typical example in which a PIN type photodiode 20 is mounted on the base 41, for example. Although the photodiode 20 varies depending on the application, in this example, it is about 500 μm square, about 200 μm in thickness, and about 200 μm in light receiving diameter.
φ, the electrode 21 on the light receiving surface and the opposite surface (back surface),
22 are formed respectively. Photodiode 20
Is Au-Sn on the electrode pattern 411 with the light receiving surface facing up.
It is connected and fixed by alloy solder or the like, and is electrically connected to the back electrode 22. Further, the electrode pattern 412 and the light receiving surface electrode 21 are electrically connected by the bonding wire 31.

FIGS. 8A to 8C show examples in which the photodiode 2 is mounted on the base 41 and then the base 41 is mounted on the Si substrate S. The light receiving surface of the photodiode 2 is Si
The connection is made perpendicular to the main surface of the substrate S. Thereby, the optical fiber (not shown) mounted in parallel with the main surface of the Si substrate S and the photodiode 2 are optically connected.
Wiring for supplying power to the photodiode 2 is performed by wire bonding to the Si substrate S from an electrode pattern on a surface different from the mounting surface of the photodiode 2.

[0008] Here, the base 41 is generally formed of a paste containing filler on a ceramic body such as alumina, and an electrode pattern is formed on each surface by printing.

A method has also been proposed in which a photodiode is directly mounted on a Si substrate without using the above-described base on the Si substrate (for example, see Japanese Patent Application Laid-Open No. 8-94887). . In this proposal, when mounting an optical fiber in an optical fiber mounting groove on a Si substrate, a slope is formed so as to face an optical fiber emission end, and a photodiode is mounted on the slope. is there. Here, the electrode on the lower surface of the photodiode is brought into direct contact with the electrode formed on the slope, and the electrode on the upper surface of the photodiode is made by wiring.

[0010] Further, the photodiode is placed on a Si substrate with the light receiving surface of the photodiode facing down, and the 90 ° optical path is changed by a total reflection surface formed in a part of an optical path groove formed under the light receiving surface. A method has been proposed in which light emitted from an optical fiber is guided to a light receiving surface (for example, see Japanese Patent Application Laid-Open No. 9-54228).

[0011]

However, in the above mounting structure, in forming the electrode pattern on the base,
Since the relative positioning accuracy of the two patterns depends on the mechanical accuracy of the outer shape, there is a problem that the accuracy is poor.

In pattern formation on two or more surfaces, after the pattern formation on the first surface is completed, when forming the next pattern, it is necessary to handle and align the bases one by one. In addition, there is a problem that productivity is extremely poor, and there is a problem that as the size becomes smaller, the handling becomes more difficult, and the productivity further deteriorates.

When the optical position adjustment between the light receiving portion of the photodiode and the optical fiber is performed only with mechanical accuracy, the light receiving position is limited by the accuracy of the outer shape of the base and the positional accuracy of the electrode pattern with respect to the outer shape of the base. Diameter (diameter of light-receiving part)
However, there is a problem that it is difficult to realize sufficient optical coupling with a photodiode having a small (for example, 50 μm or less).
That is, it is difficult to mount a photodiode having a small light receiving diameter capable of high-speed operation.

As described above, since the size and the cost are in a trade-off relationship, the cost and the size of the base are conventionally extremely high due to the miniaturization and the high performance of the base. However, there are various problems such as difficulty in mounting and poor mounting accuracy.

Further, in the mounting structure, since the wiring surfaces are not on the same plane, the process becomes extremely complicated,
There is a problem in that the light receiving sensitivity of the photodiode and the tolerance of the mounting position alignment accuracy are smaller than when light is received almost perpendicularly to the optical path.

Further, depending on the mounting structure, a decrease in the light receiving sensitivity cannot be avoided.

The present invention has been proposed in view of the above-mentioned conventional problems, and is particularly suitable for mounting an optical semiconductor device such as a surface light emitting / receiving semiconductor device, and is excellent in mass productivity, compact and excellent in high frequency characteristics. It is an object of the present invention to provide an optical semiconductor element carrier that can be mounted with high accuracy and a mounting structure thereof.

[0018]

In order to achieve the above object, an optical semiconductor device carrier according to the present invention comprises an optical semiconductor device disposed on a base made of single-crystal silicon, and the base comprises: An optical semiconductor device disposing surface comprising the {110} surface or the {100} surface, on which the optical semiconductor device is disposed;
At least two inclined surfaces which are made of a 1 ° surface and are lower surfaces when the base is erected. Here, {110} plane, {100} plane, and {11} plane
The 1｝ planes are (110) plane, (100) plane, and (1) plane, respectively.
11) A plane equivalent to a plane.

Further, the optical semiconductor element mounting surface and the
A conductor pattern for energizing the optical semiconductor element is formed on one of the inclined surfaces.

Further, in the mounting structure of the present invention, the optical semiconductor element carrier is disposed on a substrate having a concave portion formed thereon, and the concave portion contacts two inclined surfaces of the optical semiconductor element carrier. It is characterized by having an inclined surface that comes into contact with it.

When the (110) plane is used as the optical semiconductor element mounting surface of the optical semiconductor element carrier, the (100) plane of Si single crystal is used as the main surface for the substrate on which the concave portion is formed, while When the (100) plane is used for the semiconductor element carrier, the (110) plane of Si single crystal is used as the main surface for the substrate, so that the optical semiconductor element arrangement surface is almost completely perpendicular to the substrate. Can be.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the optical semiconductor element carrier and the mounting structure thereof according to the present invention will be described below in detail with reference to the drawings.

FIG. 1A shows, for example, the (100) plane and the (1) plane.
10) On a substrate S made of a Si single crystal having a plane as a main surface,
FIG. 2 is a plan view of an optical module M in which an optical fiber 5 (mounted on a V-groove 6) as an optical waveguide and an optical semiconductor element carrier C provided with an optical semiconductor element to be optically coupled to the optical fiber 5 are shown.
FIG. 1B is a sectional view taken along line AA. FIG.
FIG. 4 is an enlarged view of a portion B of FIG.

Here, as an optical semiconductor element, for example, In
A back-illuminated PIN photodiode 2 in which an InGaAs PIN structure is stacked on a P substrate is used. Also, the substrate S
On the upper side, a conductor pattern (A) for driving the back-illuminated PIN photodiode 2 and the preamplifier 8 to transmit a signal.
u, Cu, or Al and alloys thereof can be used).
4 is formed. Further, concave portions 7 (inclined surfaces 7a and 7b; {111} planes of Si single crystal) are accurately formed in a trapezoidal cross-section by anisotropic etching using an alkaline solution or the like in substrate S in a region where optical semiconductor element carrier C is to be mounted. Have been. The electrode patterns 12, 13, 1 are provided on the inclined surfaces 7a, 7b.
4 is partially formed. In the recess 7, a driving conductor (described later) of the back illuminated PIN photodiode 2 is connected to the electrode pattern of the recess 7, so that the back illuminated PIN photodiode 2 can be driven.

FIG. 2A shows the see-through type PIN photodiode 2 seen through, and FIG. 2B shows the optical semiconductor element carrier base. FIG. 3 shows an optical semiconductor element carrier C.

The base 1 is provided with a back-illuminated PIN photodiode 2 and has a plane A1 on which an optical semiconductor element is provided.
Is formed with respect to the optical semiconductor element mounting surface A1, and the first inclined surface A2 which is the lower surface side when the base 1 is erected is opposed to the optical semiconductor element mounting surface A1 by a distance d. Back A4
And a second inclined surface A3 that forms θ with respect to the rear surface A4 and becomes the lower surface side when the base 1 is erected, and is a driving conductor for the back-illuminated PIN photodiode 2. Electrode patterns 12, 13, and 14 are formed in a region from the optical semiconductor element disposition surface A1 to the first inclined surface A2,
The electrode patterns 16, 17, 18 are formed on the second inclined surface A3. The electrode patterns 12, 13, and 14 constitute a CPW electrode, and have a characteristic impedance of, for example, 50.
Each interval is adjusted to match Ω.

When the back illuminated PIN photodiode 2 does not use a CPW electrode, the electrode pattern 1
The wires 2, 13, and 14 do not need to be CPW electrodes, and may be wiring using wiring. If the electrode pattern provided in the concave portion 7 formed in the substrate S and the driving conductor of the back-illuminated PIN photodiode 2 can be conducted well, the driving conductor formed on the base 1 is not necessarily the first. It is not necessary to form the entirety of the inclined surface A2 and the second inclined surface A3.

Here, θ is (11) of the Si single crystal on the base 1.
35.26 ° when the (0) plane is used, and the (10)
When the 0) plane is used, the angle is 54.74 °.

As shown in FIG. 2A, the back illuminated PI
Since the N photodiode 2 receives light from the AR coating (anti-reflection) film 24 made of, for example, SiN _X formed on the back side of the light receiving unit 23, light is incident on the light receiving unit 23. 2 is mounted on the base 1 with the AR coating film forming surface facing upward, and the CPW electrode pattern 25 formed on the surface layer of the light receiving section 23 and the electrode patterns 12, 13, and 14 of the base 1 are electrically connected. You. The pattern 15 is used for fixing the back-illuminated PIN photodiode 2. The optical connection from the optical fiber 5 to the back illuminated PIN photodiode 2 is made as shown in FIG. In addition, front-illuminated PIN photodiode,
It can also be used for various light receiving semiconductor elements such as avalanche photodiodes.

The surface of the base 1 on which the optical semiconductor elements are provided is S
The (110) plane of the i single crystal is excellent. This is because the {111} plane becomes sharper with respect to the surface on which the optical semiconductor element is provided, and the installation property is improved. However, a (100) plane of Si single crystal may be used. Since Si has a large dielectric loss tangent, it is 1000
It is desirable to use one having a high resistance of about Ω · cm or more. Although the dielectric constant of Si is 11.8, which is larger than that of alumina, which is a conventional general material, since the size can be significantly reduced in the present invention, the parasitic capacitance of the conventional structure is about 11.8.
It can be suppressed to about 0.02 pF, which is much lower than 0.3 pF. Furthermore, a SiO2 film is laminated on Si to about 100 μm,
By forming an electrode layer thereon, transmission loss due to dielectric loss tangent and parasitic capacitance can be reduced.

Next, an example of a method for manufacturing the optical semiconductor element carrier will be described with reference to FIG.

FIG. 5 schematically shows the optical semiconductor element carrier formation region T after the wafer process and before the dicing process.

First, a thermal oxide film is formed on the front and back surfaces of a Si single crystal wafer 30 having a (110) plane as a main surface, and a part of the thermal oxide film is cut into a desired shape by photolithography. A similar pattern is formed on the front and back surfaces of No. 30. Thereafter, the wafer 30 is immersed in an alkaline solution such as an aqueous KOH solution, and the wafer 30 is subjected to anisotropic etching. Thereby, inclined surfaces A2 and A3 of the {111} plane, which forms 35.26 ° with respect to the (110) plane, can be accurately formed.

These series of steps can be performed similarly when a wafer having a (100) plane as a main surface is used.
In this case, 54.74 ° is formed with respect to the (100) plane.
1 ° inclined surfaces A2 and A3 can be accurately formed.

When the back illuminated PIN photodiode 2 is mounted on the substrate S using the optical semiconductor element carrier C shown in FIG. 3, the mounting height of the back illuminated PIN photodiode 2 with respect to the substrate S is based on the upper edge 19. Then
It is determined only by the thickness and the thickness d of the bonding material, that is, only by the thickness accuracy of the wafer 30, and can be controlled well. The accuracy of the V-groove width and depth and the positioning accuracy of the front and back surfaces are determined by the back-illuminated PI
It is not important to the mounting height accuracy of the N photodiode 2, a simple process can be used, and the process management is easy.

Next, electrode patterns 12 to 18 and a not-shown dicing marker pattern are formed by photolithography. At this time, the electrode patterns 12 to 15 on the optical semiconductor element disposition surface are also aligned with the V-groove edge and the dicing marker pattern because they are also used as image recognition markers at the time of mounting the optical semiconductor element described later. A spray coating method can be suitably used for uniformly coating the photoresist on the substrate surface having the groove, and a negative photoresist can be suitably used for the exposure.

Finally, by dicing unnecessary portions along the dicing marker pattern, a plurality of optical semiconductor element carriers can be completed.

According to this method, the linearity and positional accuracy of the pattern are significantly better than those of a process using conventional printing, and the size can be reduced. In addition, a large number of products can be formed on a wafer in a single process, eliminating the complexity of the process of aligning multiple products in the conventional process of printing electrode patterns on multiple planes, greatly improving mass productivity. I do.

Next, an example of mounting the back illuminated PIN photodiode 2 will be described.

First, the back illuminated PIN photodiode 2 is connected to the electrode patterns 12, 1 of the optical semiconductor element carrier C.
It is positioned and heated and fixed on 3, 14, 15 using a flip chip mounting device. This positioning is performed by recognizing an image of the light receiving portion pattern of the back illuminated PIN photodiode 2 and the electrode patterns 12, 13, 14, and 15 and adjusting the positional relationship between them to the design position. As described above, the electrode pattern serving as a marker at the time of mounting is preferably positioned because it has good linearity and positional accuracy. As the fixing material, AuSi-based, AuSn-based, Pb
Sn-based, In-based solder, or the like can be used.

Next, as shown in FIG. 4, the optical semiconductor element carrier C is mounted on the substrate S. The optical semiconductor element carrier C, on which the back-illuminated PIN photodiode 2 is mounted, is vacuum-sucked to a collet, and is loaded into the concave portion 7 formed on the substrate S. Then, the suction of the collet is released, and the collet is pressed and weighted vertically against the substrate S and is fixed by heating. Optical semiconductor element carrier C
When the (110) plane was used as the optical semiconductor element mounting surface, the (100) plane of Si single crystal was used as the main surface for the substrate S, while the (100) plane was used for the optical semiconductor element carrier C. In some cases, the (S) single crystal (110) plane is used as the main surface for the substrate S, so that the optical semiconductor element mounting surface A
1 can be made almost completely perpendicular to the substrate S,
The inclined surfaces A2 and A3 can be brought into good contact with the inclined surfaces 7a and 7b of the concave portion 7 without gaps and can be joined. The back-illuminated PIN photodiode 2 has a thickness d, a thickness of a bonding material, an upper edge 1.
The semiconductor device is mounted at a predetermined height determined by the distance from the optical semiconductor element mounting position 9 to the optical semiconductor element mounting position, and at a predetermined horizontal position determined by the dicing edge 26 from the optical semiconductor element mounting position.

Finally, the optical fiber 5 is mounted on the V groove 6 positioned on the substrate S, and is optically connected to the back illuminated PIN photodiode 2. The relative positional accuracy of the back-illuminated PIN photodiode 2 in a plane perpendicular to the central axis (core axis) of the optical fiber 5 is determined by the optical semiconductor element carrier C.
And the mounting accuracy of the optical semiconductor element on the optical semiconductor element carrier C, and good controllability can be obtained.

[0043]

EXAMPLES Next, more specific examples will be described.

First, a substrate having a resistivity of 1000 Ω · cm having the (110) plane of the Si single crystal as the surface on which the optical semiconductor element is provided was used as a base. The outer shape of the base is, as shown in FIG.
The design is 0.8mm, depth 0.8mm, thickness 0.6mm.

The back illuminated PIN photodiode has a size of 0.6 mm square, a light receiving diameter of 35 μm, and 130 μm on the back illuminated portion.
An AR coating part having a diameter and a CPW electrode configuration was used.

The width of the electrode pattern 13 was 100 μm, and the distance between the electrode pattern 13 and the electrode patterns 12 and 14 was 37 μm. The electrode layer has a total thickness of about 0.5.
An AuSn solder having a total film thickness of 2 μm was further laminated on the photodiode mounting portion using a μm laminated film of Cr and Au.

The method for manufacturing the optical semiconductor element carrier is shown in FIG.
After a V-groove pattern is formed to a depth of about 141 μm by wet etching of a KOH aqueous solution in an arrangement as shown in FIG. 1, an electrode pattern is formed by dry etching to form a Si single crystal wafer having a diameter of about 10 cm ((11
About 6000 optical semiconductor element carrier formation regions were formed on the (0) surface as the main surface).

Next, the process of mounting the back-illuminated PIN photodiode chip in each of the optical semiconductor element carrier regions on the Si wafer is repeated a plurality of times by the number of times.
A substrate on which a plurality of photodiodes were mounted was formed. As a result, the productivity of mounting the optical semiconductor element on the optical semiconductor element carrier has been significantly improved.

Thereafter, the substrate on which the photodiode was mounted was cut from the dicing marker, and a plurality of optical semiconductor element carriers on which the photodiode was mounted were taken out.
Then, the element is set so that the light incident surface is perpendicular to the ground.
It was aligned using a mounter that can be rotated by 0 ° and mounted on a substrate S.

Since the substrate S was formed with the (100) plane of the Si single crystal as the main surface, the relative positional relationship between the optical fiber and the groove for mounting the optical semiconductor element carrier was 12
Accuracy within μm could be achieved. Thereby, good optical coupling was realized.

Further, a photodiode preamplifier was mounted on the substrate S. From the photodiode to the preamplifier, the optical semiconductor element carrier and C formed on the substrate S
The characteristic impedance can be matched to the input impedance of the preamplifier by the PW electrode wiring, and the wiring length can be shortened to about 1 mm.
Wiring with low loss for this signal.

[0052]

According to the optical semiconductor element carrier and its mounting structure of the present invention, the following remarkable effects can be obtained.

Since the surface on which the base can be formed accurately is used as the mounting surface of the optical semiconductor element, the optical semiconductor element can be mounted on the flat board with high precision, and a small-diameter light emitting / receiving section particularly suitable for high-speed operation is provided. Good optical connection can be performed with good work efficiency by passive alignment in the element thus formed.

The optical semiconductor element carrier can be mass-produced from one flat substrate, and the mass productivity is extremely good.

The above-mentioned production can be performed in a batch process;
There is no complicated operation such as handling during the manufacturing process.

The optical semiconductor element can be mounted in the substrate state or in the aligned state after the end of the process (dicing),
Good workability of mounting.

The miniaturization is easy, and the miniaturization can reduce the capacity of the entire optical semiconductor element carrier, which is suitable for high-speed operation.

Since there is no need to wire from the optical semiconductor element carrier, there is an effect of reducing the discontinuity of the characteristic impedance, which is suitable for high-speed operation and has good mounting efficiency.

With the above effects, it is possible to provide an optical semiconductor element carrier having a low cost, small size, high precision, excellent high-frequency characteristics, and significantly improved mass productivity, and a mounting structure thereof.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a mounting structure (optical module) of an optical semiconductor element carrier according to the present invention, and (a).
2 is a plan view, and FIG. 2B is a sectional view taken along line AA in FIG.

FIGS. 2A and 2B are perspective views schematically showing a state where an optical semiconductor element carrier according to the present invention is disassembled, wherein FIG. 2A shows a back-illuminated PIN photodiode, and FIG. Is shown.

FIG. 3 is a perspective view schematically showing an optical semiconductor element carrier according to the present invention.

FIG. 4 is an enlarged view of a portion B in FIG. 1 (b).

5A and 5B are diagrams schematically illustrating a method for manufacturing an optical semiconductor element carrier according to the present invention, wherein FIG. 5A is a plan view showing the entire wafer, FIG. 5B is a side view thereof, and FIG. () Is an enlarged plan view of a portion C, and (d) is a cross-sectional view taken along the line DD.

FIG. 6 is a perspective view schematically showing a conventional optical semiconductor element carrier base.

FIG. 7 is a perspective view schematically showing a conventional optical semiconductor element carrier.

8A and 8B are diagrams schematically illustrating an example in which a conventional optical semiconductor element carrier is mounted on a substrate, wherein FIG. 8A is a partial cross-sectional view on the front side, FIG. 8B is a plan view, and FIG. It is a side surface partly sectional view.

[Explanation of symbols]

 1: base 2: back-illuminated PIN photodiode 3: CPW electrode pattern 1: 4: CPW electrode pattern 2 5: fiber 6: V-groove 7: recess 8: preamplifier 12-18: electrode pattern 20: PIN photodiode 21: Light receiving surface electrode pattern 22: Back surface electrode pattern 23: Light receiving portion 24: AR coating film 25: CPW electrode pattern 30: Si single crystal wafer 31: Wire bond 41: Base substrate 411: First electrode pattern 412: Second Electrode pattern A1: Optical semiconductor element mounting surface A2: First inclined surface A3: Second inclined surface A4: Back surface C: Optical semiconductor element carrier M: Optical module S: Substrate

Claims (3)

[Claims] An optical semiconductor element carrier comprising an optical semiconductor element disposed on a base made of single crystal silicon,
The base comprises a {110} plane or a {100} plane, and a surface on which the optical semiconductor element is disposed, on which the optical semiconductor element is disposed;
An optical semiconductor element carrier comprising at least two inclined surfaces each having an 11 ° plane and serving as a lower surface when the base is erected. 2. The optical semiconductor element carrier according to claim 1, wherein a conductor pattern for energizing the optical semiconductor element is formed on the optical semiconductor element mounting surface and the two inclined surfaces. 3. A mounting structure of an optical semiconductor element carrier, wherein the optical semiconductor element carrier according to claim 1 is disposed on a substrate having a concave portion, wherein the concave portion is formed by the optical semiconductor element. An optical semiconductor device carrier mounting structure, comprising: an inclined surface that abuts two inclined surfaces of a carrier.