JP2001344993A - Testing method of semiconductor device and testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To integrate clocks of a semiconductor device having a SDRAM and an ASIC to one clock. SOLUTION: A LSI tester 20 inputs test data to an ASIC 13 based on an internal clock generated by a clock generating circuit 11 of a SDRAM 12, and takes out test result data from the ASIC 13. A skewness adjusting device 21 is connected to both of a clock wiring 30 and a data wiring 31 at the time of test so that the timing of a clock and data is made the same as internal signal transmitting timing at the time of normal operation, and its equivalent parasitic capacity is adjusted. Clocks of the SDRAM and the ASIC are integrated to one by enabling a test by a common internal clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for testing a semiconductor device, and more particularly, to an SDRAM and an ASIC.
The present invention relates to a test method of a semiconductor device suitable as a test method of a semiconductor user system including:

[0002]

2. Description of the Related Art As a conventional ASIC device, a synchronous DR is used.
There is known a semiconductor user system in which an AM (SDRAM) and an ASIC are integrated on the same semiconductor chip. A
The SIC and the SDRAM operate with a first clock and a second clock, each having a predetermined phase relationship.

In a conventional semiconductor user system, an ASIC
If the DRAM and the DRAM can be operated at the same clock, there is an advantage that the circuit configuration is simplified. like this,
When a user system integrated with a clock is tested by a semiconductor tester, the semiconductor tester and the entire user system can be operated by an internal clock generated by a clock generation circuit of the semiconductor user system.

FIG. 5 shows the connection between the semiconductor user system 10 and the LSI tester 20 when the test is performed as described above. The internal clock generated by the clock generator 11 incorporated in the SDRAM 12 is connected to the ASIC 13 via the buffer 14 inside the user system, and is transmitted from the user system 10 to the LSI tester 2.
0 is also supplied via external wiring. On the other hand, the test data from the semiconductor tester 20 is also supplied to the AS via the external wiring in synchronization with the clock from the clock generator 11.
The test result data is supplied to the IC 13
It is output from C13 to the LSI tester 20.

[0005]

At the time of the above test,
As shown in FIG. 5, the clock wiring 3 from the SDRAM 12 is provided by external wiring and wiring inside the LSI tester 20.
0 and data wiring 31 for supplying data to the ASIC 12
Respectively, have parasitic capacitances C1 and C2 different from those in the normal operation, so that a delay determined by a CR time constant occurs in both the clock and the data. This delay causes a signal timing difference in the output of the clock and data different from the timing difference in the normal operation. This is shown in FIG.

As shown in FIG. 6, for example, when the clock skew (dl_CLK) at the time of a test is much longer than the data skew (dl_data), as shown in FIG. There is a problem that "data A" from the SDRAM to be performed is not taken in. In other words, actually, the output of the user system that performs a normal operation in a normal environment is erroneously determined to be different from the expected value.

The skew generated when transmitting the clock and data depends on the test environment such as the type and format of the external wiring and the LSI tester at the time of the test. Therefore, in the conventional semiconductor user system, as described above, the SDRA
Each of the M and the ASIC is provided with a clock generation circuit, and both operate in synchronization with two different clocks having a predetermined phase relationship. With this configuration, the configuration of the conventional semiconductor user system is complicated.

In view of the above, the present invention provides a test method and a test apparatus for a semiconductor device capable of appropriately performing an operation test of an ASIC of a semiconductor user system using an internal clock generated by an SDRAM. Accordingly, an object of the present invention is to provide a semiconductor user system capable of integrating clocks of an SDRAM and an ASIC.

[0009]

To achieve the above object, the present invention provides a method for testing a semiconductor device, comprising: a clock generating circuit for generating an internal clock signal; and a data transmission circuit for mutually transmitting data in synchronization with the internal clock signal. A method for testing a semiconductor device having a first circuit and a second circuit, wherein test data is input to the first or second circuit in synchronization with the internal clock signal, and When fetching test result data from the first or second circuit, a skew of the test data and the test result data is adjusted in accordance with a skew of the internal clock signal generated during a test.

A test apparatus for a semiconductor device according to the present invention includes a clock generation circuit for generating an internal clock signal;
A test apparatus for testing a semiconductor device having a first circuit and a second circuit that mutually transmit data in synchronization with the internal clock signal, wherein a clock skew for adjusting a skew of the internal clock signal is provided. Adjusting means; data input / output means for inputting test data to the first or second circuit based on the skew-adjusted internal clock signal and extracting test result data from the first or second circuit; Data skew adjusting means for adjusting the skew of the test data and the test result data.

According to the method and the apparatus for testing a semiconductor device according to the present invention, the skew of the internal clock signal and the skew of the data are adjusted at the time of the test, so that the LSI
Since the signal transmission timing between the tester and the first or second circuit can be adjusted to the signal transmission timing between the first circuit and the second circuit during normal operation,
There is no erroneous determination that a normally operating circuit malfunctions during a test.

Here, the method of testing a semiconductor device according to the present invention can be particularly suitably applied to a semiconductor user system in which the first circuit and the second circuit are an SDRAM and an ASIC, respectively.

In a preferred aspect of the semiconductor device test method according to the present invention, the skew adjustment of the data is performed by a dynamic load and / or a load relay resistor connected to a data line transmitting the test data and the test result data. Is In this case, skew adjustment of data is easily performed.

Further, in the test apparatus for a semiconductor device according to the present invention, the clock skew adjusting means and the data skew adjusting means may include a dynamic load on a clock wiring for transmitting the internal clock signal and a data wiring for inputting / outputting data. And / or a buffer for connecting a load relay resistor. In this case, the clock skew and the data skew can be adjusted individually, and the timing difference between the clock and the data at the time of the test can be adjusted optimally.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail based on embodiments of the present invention with reference to the drawings. FIG.
FIG. 3 is a block diagram showing a state when a test method of the semiconductor device according to the first embodiment of the present invention is performed.

The semiconductor user system 10 includes an SDRAM 12 having a clock generation circuit 11 and an ASIC 1
3 as a one-chip semiconductor device. S
Both the DRAM 12 and the ASIC 13 transmit data between each other in synchronization with the internal clock generated by the clock generation circuit 11 during normal operation.

The LSI tester 20 inputs test data to, for example, the ASIC 13 in synchronization with an internal clock generated by the clock generation circuit 11 of the semiconductor user system 10, and outputs test result data from the ASIC 13 in synchronization with the internal clock. The semiconductor user system 10 is extracted and analyzed, and the quality of the operation of the semiconductor user system 10 is determined.

A skew adjustment circuit 21 for adjusting the skew of the internal clock supplied from the semiconductor user system 10 is provided inside the LSI tester 20. Also,
A skew adjustment circuit 21 is also provided on a data wiring 31 for transmitting test data to the semiconductor user system 10 and extracting test result data from the semiconductor user system 10. Both skew adjustment circuits 21 are configured by, for example, a dynamic load.

As shown in FIG. 2, the dynamic load includes two constant current sources 51 and a bridge-connected four current sources.
A parasitic capacitance is equivalently added to the clock wiring 30 or the data wiring 31 connected to the input terminal 53. The value of the equivalent parasitic capacitance can be adjusted by adjusting the current of the constant current source 51.

Here, the case where the data latch at the time of the normal operation is performed at the rising edge of the clock pulse, and when the test is performed by the conventional LSI tester,
As shown in FIG. 5, it is assumed that the delay of the clock signal is large at the time of the test and the data A is not latched. In the LSI tester 20 of the present embodiment,
By setting the equivalent parasitic capacitance of the clock wiring 30 to be small and the equivalent parasitic capacitance of the data wiring 31 to be large, a data latch timing similar to the timing in the normal operation as shown in FIG. 3 is obtained. As a result, the same signal latch timing as that in the normal operation can be obtained during the test. Therefore, it is determined that the semiconductor user system 10 that normally operates normally, which has occurred during the test using the conventional LSI tester 20, erroneously malfunctions. No more.

FIG. 4 shows the configuration of a second embodiment of the present invention in which the skew adjusting device is constituted by a load relay resistor 22. The load relay resistor 22 connects the pull-up resistor line connected to the power supply line to the clock wiring 3.
0 and a switch selectively connected to the data wiring 31. The time constant of the wiring can also be adjusted by the load relay resistor 22, so that the timing between the clock signal and the data can be adjusted.

In the above embodiment, an example has been shown in which the skew adjustment is performed by a dynamic load or a load relay resistor, but other skew adjustment methods conventionally used can be used. Further, the data latch timing is not limited to the example of latching at the rising edge of the clock signal, but may be latched at the falling edge.

As described above, the present invention has been described based on the preferred embodiments. However, the present invention is not limited only to the configuration of the above-described embodiment, and various modifications and changes can be made from the configuration of the above-described embodiment. Changes are possible.

[0024]

As described above, according to the semiconductor device test method and test apparatus of the present invention, a desired skew can be adjusted between a clock signal, test data, and test result data during a semiconductor test. Since test data and test result data are transmitted at the same timing as during normal operation, it is possible to prevent a semiconductor device performing normal operation from being erroneously determined to be malfunctioning. And a semiconductor user system operated by the above clock can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram when a test method according to an embodiment of the present invention is performed.

FIG. 2 is a circuit diagram showing an example of the dynamic load of FIG. 1;

FIG. 3 is a timing chart showing data transmission timing in the test of FIG. 1;

FIG. 4 is a block diagram showing a state when a test method according to a second embodiment of the present invention is performed.

FIG. 5 is a block diagram showing a conventional semiconductor device test method.

FIG. 6 is a timing chart showing signal transmission in the test of FIG. 5;

[Explanation of symbols]

 10: User system 11: Clock generation circuit 12: SDRAM 13: ASIC 14: Buffer 20: LSI tester 21: Skew adjustment device (dynamic load) 22: Load relay resistor 30: Clock wiring 31: Data wiring C1, C2: Parasitic capacitance

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) G11C 11/401 G11C 11/34 371A

Claims (5)

[Claims] 1. A semiconductor device for testing a semiconductor device having a clock generation circuit for generating an internal clock signal, and a first circuit and a second circuit for mutually transmitting data in synchronization with the internal clock signal. In the test method, when inputting test data to the first or second circuit in synchronization with the internal clock signal and extracting test result data from the first or second circuit, the test data and the A method for testing a semiconductor device, comprising: adjusting a skew of test result data in accordance with a skew of the internal clock signal generated during a test. 2. The method according to claim 1, wherein the first circuit and the second circuit are S
2. The method for testing a semiconductor device according to claim 1, wherein the method is a DRAM and an ASIC. 3. The semiconductor according to claim 1, wherein the skew adjustment of the data is performed by a dynamic load and / or a load relay resistor connected to a data line transmitting the test data and the test result data. How to test the equipment. 4. A semiconductor device for testing a semiconductor device having a clock generation circuit for generating an internal clock signal, and a first circuit and a second circuit for mutually transmitting data in synchronization with the internal clock signal A test skew adjusting means for adjusting a skew of the internal clock signal; inputting test data to the first or second circuit based on the skew-adjusted internal clock signal; 2. A test apparatus for a semiconductor device, comprising: a data input / output unit that extracts test result data from a second circuit; and a data skew adjustment unit that adjusts a skew of the test data and the test result data. 5. A buffer in which the clock skew adjusting means and the data skew adjusting means respectively connect a dynamic load and / or a load relay resistor to a clock wiring for transmitting the internal clock signal and a data wiring for inputting / outputting data. The test device for a semiconductor device according to claim 4, further comprising: