JP2001338995A - Semiconductor non-volatile memory and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor non-volatile memory having the number of the many times of electric writing. SOLUTION: A hollow structure 10 is formed between the lower part of a floating gate 9 and the impurity area of a P-type board 1, and a control gate 12 is formed on the surface of the floating gate 9 through an inter- polysilicon insulation film 11. High voltage is applied on both-end electrodes of the hollow structure 10 to generate Fowler-Nordheim tunnel current, and a semiconductor non-volatile memory writing and deleting information is made by injecting and discharging electrons. The hollow structure 10 forms a gate insulation film 4 existing just under the floating gate electrode 9 as the floating gate electrode 9 is made a mask by etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a Fowler-Nordheim
(FN) Rewrite information using tunnel current,
The present invention relates to a FLOTOX type or FLASH type semiconductor nonvolatile memory having a polysilicon gate electrode structure having a single layer structure or a multilayer structure having two or more layers.

[0002]

2. Description of the Related Art FIG.
FIG. 3 is a cross-sectional view of a layer polysilicon gate electrode structure FLOTOX type semiconductor nonvolatile memory. In this FLOTOX type semiconductor nonvolatile memory, an N-type tunnel drain region 402 of a second conductivity type is formed on a part of a P-type semiconductor substrate 401 of a first conductivity type. Is provided with a tunnel insulating film 403 of 8 to 12 nm, and the gate insulating film 40 including the tunnel insulating film is provided.
4, a first-layer polysilicon electrode exists as a floating gate 405. A second-layer polysilicon electrode is formed on the floating gate 405 via the inter-polysilicon insulating film 406 by a control gate 407.
It is formed as. In order to electrically rewrite information, a high electric field is applied between the tunnel drain region 402 and the floating gate 405 which is capacitively coupled by the control gate 407 and the inter-polysilicon insulating film 406.

[0003]

At this time, in the conventional semiconductor non-volatile memory, the threshold voltage of the memory cell transistor is changed by flowing an FN tunnel current through the tunnel insulating film to inject or emit electrons into the floating gate. Let me remember the information. When this FN tunnel current flows through the tunnel insulating film, holes and electrons are captured at the interface between the floating gate and the tunnel insulating film, and the amount of captured electrons increases as the number of times of rewriting increases. An increase in the amount of trapped electrons causes a decrease in the amount of charge transferred to the floating gate, thereby limiting the number of times of rewriting. Alternatively, dielectric breakdown of the tunnel insulating film itself occurs, and the memory operation is lost. Although this phenomenon has not yet been clearly explained, one consideration is that the crystal structure becomes discontinuous at the interface between single-crystal silicon and the tunnel insulating film, which is a silicon oxide film. There is an idea that electrons are captured by dangling bonds not related to bonding. These trapped electrons locally enhance the FN electric field,
Furthermore, it explains that a positive feedback phenomenon occurs, in which a bond between silicon and oxygen is broken to create a new dangling bond, and electrons are captured by this dangling bond, eventually leading to dielectric breakdown. .

[0004]

In order to solve the above-mentioned problems, in the present invention, the use of a silicon oxide film as a tunnel insulating film is stopped, and a material is used for an insulating portion between a tunnel drain region and a floating gate. Instead of a hollow structure. By making the part where this FN tunnel current flows into a hollow structure, the number of dangling bonds between the silicon substrate and the space interface cannot be reduced, but after all electrons are trapped by dangling bonds existing on the silicon surface, No new dangling bonds are generated, and the positive feedback phenomenon does not occur. Therefore, dielectric breakdown does not occur in the tunnel region. In addition, even if the electric field is locally increased, the electric field can be effectively dispersed if the structure is hollow. From the above, it is possible to provide a semiconductor non-volatile memory with a remarkably large number of times (almost theoretically infinite) that can be electrically rewritten dramatically.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor nonvolatile memory according to the present invention will be described below with reference to the drawings.

FIG. 1 is a process sectional view in a direction perpendicular to the memory cell channel direction for explaining one embodiment of a method for manufacturing a semiconductor nonvolatile memory according to the present invention.

First, an element isolation region 2 is formed by a LOCOS method on a P-type semiconductor silicon substrate 1 to which boron as a first conductivity type semiconductor impurity is added at about 8 to 30 Ω · cm.
A second part of the active region adjacent to the element isolation region 2
Photo and ion implantation energy of 50 to 110 KeV, 5E13 to 4E
It is formed by an ion implantation process at a concentration of 14 cm-2 (FIG. 1A).

Next, after removing the photoresist used as the implantation mask, a first gate insulating film 4 having a thickness of 35 to 65 nm is formed on the P-type semiconductor silicon substrate 1 by a thermal oxidation method. Then, a window 5 is opened by removing a part of the first gate insulating film 4 on the impurity region 3 of the second conductivity type by a photo-etching process.
3 to 12 n on the conductive impurity region 3 by using a thermal oxidation method.
Then, a tunnel insulating film 6 of m is formed. Further, a first-layer polysilicon film 7 is formed on the first gate insulating film 4 and the tunnel insulating film 6 to a thickness of 150 to 400 nm by a CVD method, and a 25 to 75 Ω / sq. Impurity doping is performed (FIG. 1-B).

A photoresist pattern 8 is formed on the first polysilicon film 7 by exposure, and the first polysilicon film 7 is first processed to form a floating gate 9 by an etching process. At this time, the width of a part of the floating gate in the region where the tunnel current flows is 0.10 to 0.10.
It is important that it is 0.30 um. Subsequently, the tunnel insulating film 6 is formed using the photoresist pattern 8.
Is also removed by etching, and the vicinity of the surface of the P-type semiconductor silicon substrate 1 is also removed by etching to a depth of 150 to 400 nm. Then, the tunnel insulating film 6 sandwiched between the second conductivity type impurity region 3 and the floating gate 9 is laterally etched and removed in a hydrogen fluoride aqueous solution pressurized in a sealed container, The hollow structure 10 is formed. At the time of etching, most of the floating gate 9 is covered with the photoresist, and the hollow structure 10 is formed.
Is exposed to the etchant only. (FIG. 1-C).

After that, an inter-polysilicon insulating film 11 is formed, and a second-layer polysilicon film is laminated and then patterned to form a control gate 12. Here, the inter-polysilicon insulating film 11 closes the left and right ends of the hollow structure 10 which has become a cavity at the time of etching (FIG. 1).
D). Thereafter, although not shown, a normal source / drain region shape is performed to form a metal wiring.

FIG. 2 is a process sectional view in a direction perpendicular to the memory cell channel direction for explaining an embodiment of another method for manufacturing a semiconductor nonvolatile memory according to the present invention.

First, an element isolation region 2 is formed by a LOCOS method on a P-type semiconductor silicon substrate 201 to which boron as a first conductivity type semiconductor impurity is added in an amount of about 8 to 30 Ω · cm. Photo and ion implantation energy of 50 to 110 KeV, 5
It is formed by an ion implantation process with a concentration of E13 to 4E14 cm-2 (FIG. 2-A).

Next, after removing the photoresist used as the implantation mask, the first gate insulating film 20 having a thickness of 35 to 65 nm is formed on the P-type semiconductor silicon substrate 201.
4 is formed by a thermal oxidation method. After that, a portion of the first gate insulating film 204 on the second conductive type impurity region 203 is removed by a photo and etching process to remove the window portion 2.
Then, the second conductive type impurity (arsenic or phosphorus) compound film 206 is formed on the second conductive type impurity region 203.
Is produced with a thickness of 3 to 12 nm. The impurity compound has a temperature of 60 ° C., which is the temperature at which the polysilicon is to be deposited later.
The substance must not react at 0 to 700 ° C. Further, the first gate insulating film 204 and the impurity compound film 2
First polysilicon film 207 is deposited on
It is formed to a thickness of 50 to 400 nm, and is doped with an impurity of 25 to 75 Ω / sq. By a phosphorus predeposition method (FIG. 2-B).

A photoresist pattern 208 is formed on the first polysilicon film 207 by exposure, and a floating gate 209 is formed by processing the first polysilicon film 207 by an etching process. Then, the impurity compound film 206 is subjected to a heat step of pre-deposition temperature of 800 to 950 ° C. of phosphorus or a heat step of heating to a temperature at which an added silicon substrate of 950 to 1100 ° C. flows and melts. The hollow structure 210 is formed by thermal diffusion into the impurity region 203 or the first polysilicon film 207 (FIG. 2C).

Thereafter, an inter-polysilicon insulating film 211 is formed, and a second-layer polysilicon film is laminated and then patterned to form a control gate 212 (FIG. 2).
D). Thereafter, although not shown, a normal source / drain region shape is performed to form a metal wiring.

FIG. 3 is a process sectional view in a direction perpendicular to the memory cell channel direction for explaining an embodiment of another method for manufacturing a semiconductor nonvolatile memory according to the present invention.

First, an element isolation region 302 is formed by a LOCOS method on a P-type semiconductor silicon substrate 301 to which boron of about 8 to 30 Ω · cm is added as a semiconductor impurity of the first conductivity type. An impurity region 303 which becomes a tunnel drain region after arsenic of the second conductivity type in a part of the active region thus formed;
And an impurity region 304, which is divided by the element isolation region 302 but is adjacent and later becomes a control gate, is formed by photo and ion implantation energy of 50 to 110 KeV, 5
It is formed by an ion implantation process with a concentration of E13 to 4E14 cm-2 (FIG. 3-A).

Next, after the photoresist used as the implantation mask is removed, the first gate insulating film 30 having a thickness of 35 to 65 nm is formed on the P-type semiconductor silicon substrate 301.
5 is formed by a thermal oxidation method. Then, a portion of the first gate insulating film 305 on the second conductive type impurity region 303 is removed by a photo and etching process to remove
Then, a tunnel insulating film 307 having a thickness of 3 to 12 nm is formed on the second conductivity type impurity region 303 by thermal oxidation. Further, a first-layer polysilicon film 309 having a thickness of 150 to 400 nm is formed on the first gate insulating film 305 and the tunnel insulating film 307 on the tunnel oxide film 308 on the impurity region 304 by the CVD method. Formed, and 25-75Ω / s by phosphorus pre-deposition method
The impurity doping of q. is performed (FIG. 3-B).

A photoresist pattern 310 is formed on the first polysilicon film 309 by exposure, and the first polysilicon film 309 is processed by an etching process to form a floating gate 311. At this time, it is important that the width of a part of the floating gate in the region where the tunnel current flows is 0.10 to 0.30 μm. Subsequently, the tunnel insulating film 307 is also removed by etching using the photoresist pattern 310, and the vicinity of the surface of the P-type semiconductor silicon substrate 301 is also removed by 15 mm.
Etch and remove to a depth of 0-400 nm. Then, in a hydrogen fluoride aqueous solution pressurized in a closed container,
The tunnel insulating film 307 sandwiched between the second conductivity type impurity region 303 and the floating gate 311 is etched away from the lateral direction to form a hollow structure 312 (FIG. 3C). Thereafter, although not shown, a normal source / drain region shape is performed to form a metal wiring.

[0020]

As described above, according to the present invention, the number of unbonded atoms at the interface between the silicon substrate and the space cannot be reduced by forming the portion through which the tunnel current flows into a hollow structure. When all the electrons are captured by the bonding hands, no new dangling bonds are generated thereafter, and the positive feedback phenomenon does not occur. Therefore, no dielectric breakdown occurs in the tunnel region. In addition, even if the electric field is locally increased, the electric field can be effectively dispersed if the structure is hollow. From the above, the structure of the present invention can provide a semiconductor non-volatile memory with a remarkably large number of electrically rewritable times (almost theoretically infinite).

[Brief description of the drawings]

FIG. 1 is a process sectional view in a direction perpendicular to a memory cell channel direction, for explaining one embodiment of a method for manufacturing a semiconductor nonvolatile memory according to the present invention.

FIG. 2 is a process cross-sectional view in a direction perpendicular to a memory cell channel direction, for explaining one embodiment of another method for manufacturing a semiconductor nonvolatile memory according to the present invention.

FIG. 3 is a process sectional view in a direction perpendicular to the memory cell channel direction, for explaining one embodiment of still another method of manufacturing a semiconductor nonvolatile memory according to the present invention.

FIG. 4 is a cross-sectional view illustrating a structure of a conventional semiconductor nonvolatile memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor silicon substrate 2 ... Element isolation region 3 ... Impurity region 4 ... First gate insulating film 5 ... Window 6 ... Tunnel insulating film 7 ... First polysilicon film 8 ... Photoresist pattern 9 ... Floating gate 10 hollow structure 11 inter-polysilicon insulating film 12 control gate

Claims (8)

[Claims] In a semiconductor non-volatile memory having a single-layer structure or a laminated structure of polycrystalline silicon, a refractory metal or a metal as a floating gate electrode, injection of electrons into the floating gate electrode and A semiconductor non-volatile memory, wherein a region for emitting electrons from a floating gate electrode has a hollow structure. 2. A Fowler-Nordheim (FN) tunnel current is generated by applying a high voltage to electrodes at both ends of the hollow structure according to claim 1, and electrons are injected and emitted. Semiconductor non-volatile memory. 3. The floating gate electrode according to claim 1, wherein a portion of the hollow structure in which the floating gate electrode is partly processed is thinned to form a gate insulating film immediately below the floating gate electrode. And a method of manufacturing the same. 4. The method according to claim 1, wherein after the hollow structure forms an impurity layer on a part of the semiconductor substrate, the floating gate electrode is provided in a region including the impurity layer, and the impurity layer is heat-treated. A non-volatile semiconductor memory and a method of manufacturing the same, wherein the non-volatile semiconductor memory is formed by absorbing in the semiconductor substrate or the floating gate electrode. 5. The nonvolatile semiconductor memory according to claim 1, wherein said floating electrode is capacitively coupled to a control gate electrode provided near a surface of said semiconductor substrate via an insulating film. 6. The semiconductor nonvolatile memory according to claim 1, wherein said floating electrode is capacitively coupled to a control gate electrode provided on said floating gate electrode via an insulating film. 7. An impurity region formed on a part of the surface of the silicon substrate, an element isolation region around the impurity region on the surface of the silicon substrate, a hollow structure on the impurity region, and And a control gate on a surface of the floating gate via an insulating film. 8. The semiconductor nonvolatile memory according to claim 1, wherein said hollow structure generates a Fowler-Nordheim (FN) current to inject and emit electrons.