JP2001338917A - Semiconductor manufacturing equipment, processing method and wafer potential probe - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide semiconductor manufacturing equipment and its processing method by which a wafer potential in processing and the impedance from the wafer to an earth via plasma are obtained by measurement or calculation and the processing based on the impedance can be carried out. SOLUTION: This equipment comprises a wafer potential probe 24, a current/ voltage probe 17 for measuring at least one of the current or the voltage to be applied to a wafer stage, a calculation part for obtaining the impedance from the wafer to the earth via the plasma based on a wafer voltage value, the voltage value applied to the wafer stage or the current value, and a processing part for processing based on the impedance. As a result, the wafer voltage and the plasma impedance can be obtained precisely, and an etching with good reproducibility is achieved by controlling etching parameters on the basis of this information and the deterioration of yield can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus and a processing method for processing a semiconductor wafer using plasma.
And a wafer potential probe.

[0002]

2. Description of the Related Art With the recent increase in the degree of integration of semiconductor devices, circuit patterns are becoming finer, and the required processing dimensional accuracy is becoming increasingly severe. In addition, the wafer size is increasing in diameter for the purpose of improving productivity, and the application of new materials and the change of wiring structure are being studied to improve the performance of the device. With this, development of new process technology has been promoted, and development of process technology has become extremely difficult and costly.

In a semiconductor manufacturing apparatus that processes a wafer using plasma, such as a plasma etcher or a plasma CVD, it is very important to accurately grasp and control the energy of ions incident on the substrate. In turn, this leads to a reduction in the process startup period. Conversely, if the ion energy cannot be accurately grasped, there arise problems such as variations in product performance and a decrease in yield.

One example of a method for monitoring and controlling the energy of ions incident on a substrate during such plasma processing is as follows.
For example, it is disclosed in JP-A-7-135180. In this disclosed example, a method of measuring the potential of a substrate during processing by grounding an electrode on which a substrate to be processed is mounted via a capacitor and providing a potential measuring unit for measuring a potential between the capacitor and the electrode is provided. Is disclosed.

Further, US Pat. No. 5,580,815 and US Pat. No. 6,610,006 disclose a method of manufacturing a probe for measuring a current and a voltage applied to plasma, and a method of obtaining a plasma impedance in a plasma chamber.

[0006]

However, Japanese Patent Application Laid-Open No. Hei 7-135180 discloses a method for measuring the surface potential of a substrate in order to control the energy of ions incident on the substrate. , The voltage between the capacitors connected to this electrode is measured with a voltmeter,
Since the potential of the substrate is not directly measured, a problem may occur. For example, in a case where a substrate is suction-fixed by an electrostatic chuck and subjected to an etching process, there is an example in which a deposited material adheres to the surface of the electrostatic chuck as the number of processed wafers increases. This will be described with reference to FIG.
In the disclosed example, a capacitor C1 having a known capacitance is connected to the electrode on which the substrate is mounted in order to obtain the surface potential Vg of the substrate. Then, the capacitance Cg of the substrate is checked in advance, the potential Vs is measured by the means shown in the disclosed example, and Vg is set to Vg.
It discloses a method of calculating and calculating s + (C1 / Cg) * Vs. When the electrode has an electrostatic chuck function and a dielectric film or the like is provided on the electrode surface, Cg may be corrected in consideration of the capacitance of the dielectric film. If deposits adhere to the surface of the dielectric film compared to immediately after the start of the etching process, the capacitance Cg changes, and as a result, the potential of the substrate cannot be accurately obtained.

In an actual manufacturing apparatus, the terminals connected to the electrodes are not only electrically connected to the substrate via the electrodes, but also to an electric circuit connected to the ground via a capacitor component, or to a high-frequency circuit. There is an inductance component of the power supply line that supplies power. Therefore, even if the potentials at both ends of the capacitor connected to the electrodes are simply measured, the actual potential of the substrate is not accurately measured.

Further, for example, in the case where a reaction product or the like adheres to the inner wall of a vacuum chamber confining plasma in an etching process or the like, even if the potential of the substrate can be measured by the method of the disclosed example, If the state of the plasma itself changes due to the attached matter, the processing result may change even if the voltage of the substrate is controlled.

On the other hand, in the examples disclosed in US Pat. Nos. 5,580,415 and 6,610,006, the impedance network of a plasma chamber is expressed by chamber resistance, electrode inductance, electrode-to-ground capacitance, and stray capacitance. A method for determining impedance is disclosed. However, in this disclosed example, since the surface potential of the wafer being processed in the plasma cannot be obtained, there is a problem that the ion energy incident on the wafer cannot be controlled.

In order to solve these problems, both the potential of the substrate and the plasma impedance are measured or calculated, and in some cases, up to the impedance of the substance adhering to the inner wall of the vacuum chamber or measured or calculated. It is necessary to appropriately control the etching parameters based on these information.

Accordingly, a first object of the present invention is to measure or calculate the potential of a substrate being processed and the impedance from the substrate to the ground via the plasma in a semiconductor manufacturing apparatus using plasma. To provide a semiconductor manufacturing apparatus and a processing method.

A second object of the present invention is to measure or calculate the potential of a substrate being processed and the impedance from the substrate to the ground via the plasma in a semiconductor manufacturing apparatus using plasma, and obtain this information. It is an object of the present invention to provide a semiconductor manufacturing apparatus and a processing method capable of controlling an etching parameter based on the method.

A third object of the present invention is to provide a semiconductor manufacturing apparatus using a plasma in which a proper cleaning time can be easily determined by monitoring the thickness of a film attached to the inner wall of the processing chamber. It is to provide an apparatus and a processing method.

A fourth object of the present invention is to provide a semiconductor manufacturing apparatus using plasma, in which the potential of a substrate being processed, the potential of a susceptor disposed so as to surround the substrate, and the plasma on the substrate being processed are measured. It is possible to measure or calculate the impedance to ground through the ground and the impedance to ground through the plasma on the susceptor, and to independently control the bias voltage applied to the substrate and the susceptor based on this information. It is an object of the present invention to provide a semiconductor manufacturing apparatus and a processing method that can be used.

A fifth object of the present invention is to provide a probe capable of measuring the potential of a substrate being processed and a susceptor arranged so as to surround the substrate.

[0016]

A first object of the present invention is to provide a semiconductor manufacturing apparatus for processing a semiconductor wafer by using a plasma, for example, a wafer potential probe for measuring the voltage of the semiconductor wafer from the back surface of the semiconductor wafer. A current / voltage probe for measuring at least one of a voltage value and a current value applied to the wafer stage from a high frequency power supply, and a voltage value of the semiconductor wafer measured by a wafer potential probe and measured by a current / voltage probe This can be achieved by calculating the impedance from the applied voltage or current value to the ground via the plasma on the semiconductor wafer.

The second object can be achieved, for example, by controlling various processing parameters based on at least one of the obtained impedance and the potential of the wafer.

Further, for example, an impedance is calculated from a voltage and a current measured by a current / voltage probe, and the impedance and a high-frequency power source (more precisely, a current / voltage probe) determined in advance are grounded via a plasma. By calculating the combined impedance of the equivalent circuit model up to and calculating the impedance from the wafer to the ground via the plasma and the potential of the wafer, and controlling various processing parameters based on this impedance and the potential of the wafer. Can be achieved.

Further, for example, if a film thickness probe capable of measuring the film thickness of the film adhered to the inner wall of the vacuum processing chamber is provided, and the impedance of the film thickness measured by the probe is calculated,
Since the impedance (plasma impedance) from the wafer to the surface of the film attached to the inner wall of the processing chamber can be accurately calculated, the etching can be controlled more accurately by controlling various parameters based on this information.

A third object of the present invention is to provide a semiconductor manufacturing apparatus for performing processing on a semiconductor wafer using plasma, for example, by providing a means for measuring the film thickness of the film adhered to the inner wall of the vacuum processing chamber. This can be achieved by monitoring the thickness.

A fourth object of the present invention is to provide, for example, a semiconductor manufacturing apparatus for processing a semiconductor wafer by using plasma, a wafer potential probe for measuring the voltage of the semiconductor wafer from the back side of the semiconductor wafer, and a wafer stage from a high frequency power supply. A current / voltage probe that measures at least one of a voltage and a current value applied to the susceptor, and a susceptor potential probe that measures a voltage of a susceptor arranged so as to surround the semiconductor wafer. From the voltage value of the semiconductor wafer, the voltage or current value measured by the current / voltage probe, and the voltage value of the susceptor measured by the susceptor potential probe, the impedance to the ground through the plasma on the semiconductor wafer and the impedance on the susceptor Calculate impedance to ground via plasma It can be achieved by controlling the RF voltage applied to the Fine and the susceptor independently.

Further, for example, if a film thickness probe capable of measuring the film thickness of the film adhered to the inner wall of the vacuum processing chamber is provided, and the impedance of the film thickness measured by the probe is calculated,
Since the impedance from the wafer to the surface of the film attached to the inner wall of the processing chamber and the impedance from the susceptor to the surface of the film attached to the inner wall of the processing chamber can be calculated, it is more accurate to control various parameters based on this information. Etching can be controlled.

The fifth object is to support, for example, a stylus having electrical conductivity to be brought into contact with the back surface of a semiconductor wafer to be measured with an elastic member having electrical conductivity,
This elastic member can be achieved by exposing the elastic member to the atmosphere side in a state of being electrically insulated from a flange for fixing to the vacuum chamber, and measuring the voltage of this portion.

Further, for example, by making the position of the stylus in the height direction adjustable from the atmosphere side, the measurement can be performed with good reproducibility. Further, if the material of the stylus is made harder than the hardness of the silicon oxide present on the back surface of the wafer, the measurement can be performed with higher reproducibility.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a plasma etching apparatus will be described below.

First, a first embodiment of the present invention will be described with reference to FIGS. In the following description, components having the same functions as those of the first embodiment will be denoted by the same reference numerals as those of the first embodiment, and the description thereof will be omitted.

FIG. 1 shows an example of a plasma etching apparatus according to a first embodiment of the present invention. The processing gas 1 introduced into the processing chamber is inductively coupled and capacitively coupled by a magnetic field and an electric field generated by a coil 3 connected to a high frequency power supply 2 and having high-frequency voltages applied to both ends, and is in a plasma 4 state.
The semiconductor wafer 5 is mounted on a wafer stage 6. The wafer stage 6 has a ceramic dielectric film 7 on its surface, and has an electrostatic chuck function.
The wafer stage 6 is fixed on the electrode 8 with bolts, and is electrically insulated from the vacuum chamber 10 by the insulating plate 9. The electrode 8 electrically connected to the wafer stage 6 is connected to a power supply rod 12 electrically insulated from the flange 11 so that power can be supplied from an external power supply using the power supply rod 12. Has become. In the present embodiment, a bias voltage is applied to the wafer to effectively attract ions in the plasma to the wafer.
Matching box 14 with high frequency power supply 13 of 00 kHz
Is connected to the wafer stage. Reference numerals 15 and 16 denote impedance matching coils and variable capacitance capacitors. The voltage and current value at the exit of the matching box 14 are monitored by a current / voltage probe 17 and input to an external computer 18. Computer 1
Reference numeral 8 denotes a calculation unit for obtaining the impedance from the semiconductor wafer to the ground via the plasma based on the measured voltage value or current value, and processing based on the obtained impedance (eg, display processing, parameter control processing, etc.). )
And a processing unit that performs The power supply rod 12 is also connected to a DC power supply 19 for causing the electrostatic chuck to function.
This DC power supply is a coil 2 for cutting high frequency voltage.
When a DC voltage is applied to the wafer stage while the plasma 4 is ignited, the wafer 7
The DC voltage circuit is formed through the plasma which is in contact with the vacuum chamber and is at the ground potential, and a potential difference is generated between the wafer 7 and the electrode 8 to charge the dielectric film 7 and charge the Coulomb force. Is adsorbed. Reference numeral 21 denotes a cover for protecting the outer periphery of the electrode 8 and the wafer stage 6 from plasma. Reference numerals 22 and 23 denote a turbo molecular pump and a dry pump for exhausting a processing gas and a reaction product. Numeral 24 denotes a wafer potential probe for measuring the potential of the wafer during the plasma processing. The display unit 80 is for displaying and monitoring impedance and the like obtained by a computer, and is, for example, a CRT or the like. Further, the parameter control device 82 controls various parameters of the semiconductor manufacturing apparatus (plasma etching apparatus) according to an instruction from the computer 18.

FIG. 2 shows a detailed configuration diagram of the wafer potential probe 24. In FIG. 2, the wafer potential probe 24 is
It is composed of components other than the components denoted by reference numerals 5-10. The wafer potential probe used in the present invention includes a stylus 36 having electrical conductivity, which contacts the back surface of a semiconductor wafer to be measured, an elastic member 35 having electrical conductivity supporting the stylus, A current introduction terminal 27 having a flange structure while supporting the elastic member, wherein the potential of the stylus can be measured on the atmosphere side, and the height position of the stylus can be adjusted from the atmosphere side. It is configured as follows. The details of the configuration will be described below.

A coaxial through-hole is provided in the vacuum chamber 10, the insulating plate 9, the electrode 8, and the wafer stage 6, and in this through-hole, there is formed a ceramic material for electrically insulating the probe from the electrode and the wafer stage. The insulating pipe 68 is embedded. The wafer potential probe has a flange 25 structure so that it can be attached to a vacuum chamber.
It is vacuum sealed with a ring 70. A through hole is provided at the center of this flange, and a part of this through hole is
6 are provided. Terminals 27 for measuring the voltage of the wafer are attached to the through holes. The terminal 27 has a structure in which a hollow insulating pipe 71 is embedded therein, and a conductive core wire 69 is embedded therein. A part of the outer periphery of the terminal 27 has a male screw 28 structure, and is attached to a female screw 26 provided on a flange. Further, an O-ring 29 is provided on the upper part of the terminal, so that the inner surface 30 on the upper part of the flange 25 can be sealed. A connecting rod 32 having conductivity is provided at the vacuum-side end of the core wire of the terminal. The connecting rod 32 has a socket 33 structure such that one end thereof fits the core wire, and a coil spring 35 is attached to the other end by using a spring stopper 34. A stylus 36 is provided above the coil spring 35 so that it can be driven up and down along the connecting rod. The stylus is attached so that the tip protrudes from the wafer stage surface, and moves downward by weight when the wafer is loaded. The amount of protrusion is determined in consideration of the spring constant of the coil spring. Desirably, when the semiconductor wafer is loaded on the wafer stage, it is sufficient that the semiconductor wafer completely sinks to the wafer stage by its own weight. Further, the stylus is made of a conductive material, and the tip has a radius of curvature and hardness enough to penetrate an oxide film or a nitride film present on the back surface of the semiconductor wafer. In this embodiment, the material of the stylus is tungsten carbide, but other materials such as conductive diamond can also be used. The value of the radius of curvature should be determined by the spring constant of the coil spring and the amount of protrusion of the stylus, that is, the amount of deformation of the spring, and is appropriately determined by the state of the semiconductor wafer to be actually measured. As an example, the curvature radius R required when the spring constant of the coil spring 35 is k, the amount of protrusion is L, and an oxide film having a thickness t is provided on the back surface of the 8-inch wafer is shown. 8 inches weight W of the wafer Distant, Young's modulus and Poisson's ratio, respectively E _n of the stylus, [nu _n Distant, if placed Young's modulus and Poisson's ratio of the oxide film, respectively E _w, and [nu _W, the stylus The radius a of the contact circle between the tip and the oxide film on the back surface of the wafer can be expressed by equation (1). a = {3WR ((1-ν _n ² ) / E _n + (1-ν _W ² ) / E _w ) / 4} ^1/3 (1) Equation (1) At this time, the pressure at the center of the contact portion is the equation (2) Is calculated. p = 3W / 2πa ² (2) If this pressure p is greater than the hardness of the oxide film, the stylus penetrates the oxide film and makes electrical contact with conductive silicon,
The potential of the wafer can be measured. That is, when the Vickers hardness of the oxide film is Hv, it is sufficient that the curvature radius R satisfies the expression (3). Hv <p (3) The protrusion amount of the stylus 36 in a state where no wafer is mounted is adjusted by adjusting the position of the terminal 27 described above. If a scale is attached to the air side of the terminal so that the amount of the tip of the stylus protruding from the wafer stage 7 can be easily determined from the air side, the work becomes easier. Nut 3 on the air side of terminal 27
1, the position of the stylus can be fixed after it is determined, and the vertical position of the terminal can be set arbitrarily. Therefore, a potential substantially equal to the potential of the wafer being processed can be observed on the core wire of the terminal, and the potential of the wafer can be measured by measuring the voltage of this core wire with a voltmeter. Reference numeral 62 denotes an insulating cylinder for electrically insulating the probe from the wafer stage, electrodes, and insulator.

Next, a method for obtaining the impedance from the wafer to the ground via the plasma (plasma impedance) will be described. FIG. 3 shows an equivalent circuit model from a high-frequency power supply (more precisely, a current / voltage probe) to ground via a wafer stage in the first embodiment of the present invention. This equivalent circuit model may be checked in advance using an impedance measuring instrument or the like. Explaining the numbers in the figure, reference numeral 37 denotes the potential of the vacuum chamber 10 and is a ground. 38 is a plasma impedance on the wafer, 39 is a resistance component of the dielectric film 7, 40 is a capacitance component of the dielectric film 7, 41 is a blocking capacitor, and the others are as described above. The wafer potential 42Vw measured by the wafer potential probe 24, the voltage 43Ve of the electrode connected to the outlet of the matching box, and the current 4 flowing into the electrode 4
The measured value of 4Ie is taken into a computer. When the plasma impedance 38 is set to Zp, the voltage applied to Zp at a certain time is the output voltage of the wafer potential probe 24, that is, the wafer potential Vw, and the current flowing to Zp is the current 44Ie flowing into the electrode. Is V
It can be calculated by w / Ie. The value of Zp can be read out after being processed one by one in the computer. In this embodiment, in order to obtain Zp, the voltage at the exit of the matching box, that is, the potential 42 Vw of the wafer actually being processed, is measured instead of the voltage at the exit of the matching box, ie, the potential 43 Ve of the electrode. The reason is that in this embodiment, the dielectric film 7 is attached to the surface of the wafer stage for the purpose of having an electrostatic chuck function.
This is because a voltage drop occurs in this portion, and the voltage at the exit of the matching box, that is, the voltage Ve of the electrode does not become the voltage of the wafer. That is, if the voltage value Ve measured at the exit of the matching box is used to calculate the value of Ve / Ie to obtain the value of the plasma impedance, the actual plasma impedance will not be obtained.

As an example of the problem when the plasma impedance is calculated by Ve / Ie, it is conceivable that a deposition film adheres to the surface of the dielectric film on the wafer stage as the number of processed wafers increases. When the capacitance of the dielectric film decreases due to the deposition of the deposition film, the impedance increases, so that the voltage at the exit of the matching box increases. Therefore, even though the plasma state has not changed at all, it is determined that the plasma impedance has increased. Based on this information, the electrode voltage Ve is used to keep the etching rate constant.
If the etching rate is lowered, the etching rate will be lowered, which causes poor etching. Conversely, if the input power of the high-frequency power supply for plasma generation is increased in order to lower the plasma impedance, the etching rate becomes too high, which leads to over-etching. As a result, poor etching is caused.

On the other hand, when the plasma impedance Zp is obtained in the configuration of the present embodiment, since the result of directly measuring the voltage of the wafer is used to calculate the plasma impedance, more accurate impedance and the potential of the wafer are obtained. Can be obtained by measurement or calculation,
For example, the ion energy incident on the wafer being processed, that is, the bias voltage of the wafer can be appropriately adjusted,
Etching defects can be prevented.

The wafer potential V according to the first embodiment of the present invention is described above.
FIG. 11 is a flowchart showing the flow of processing from obtaining w and plasma impedance Zp to using the same. The following processes from FIG. 11 to FIG.
It is executed by a program in the computer 18 shown in FIGS. First, in the first embodiment, an equivalent circuit model from the high-frequency power supply (more precisely, the current / voltage probe) to the ground via the wafer stage is determined as shown in FIG. 3 (step 110). Next, the wafer potential Vw, the current Ie of the wafer stage, and the voltage Ve are measured using the wafer potential probe and the current / voltage probe (step 111). Next, the computer 1 that has captured the measurement results
8 to calculate the plasma impedance Zp (step 112). Ultimately, it should be determined by the user's judgment, but when monitoring the wafer potential Vw and the plasma impedance Zp, they are displayed on the display unit 80 (step 113). When controlling the process parameters based on the obtained impedance or the like, the computer 18 controls the process parameter control device 82.
Signal, information, and the like, and the control signal from the control device 82 is subjected to parameter control, for example, a high-frequency power source 1
3 to control various parameters (step 11).
4).

A condition in which the state of the inner wall of the processing chamber does not change due to the plasma processing, or a constant condition is maintained by cleaning (there is no deposition film on the inner wall of the processing chamber).
In this case, the above calculated impedance is defined as the impedance from the semiconductor wafer to the inner wall of the vacuum processing chamber via the plasma, and various processing parameters are controlled based on the calculated impedance, whereby the semiconductor being processed with the plasma is processed. The wafer can be processed.

As described above, according to the present invention, the processing can be performed while accurately measuring the potential of the wafer while monitoring the state of the plasma based on the plasma impedance. Is controlled, the ion energy incident on the wafer can be used accurately, so that etching with good reproducibility can be achieved and a decrease in yield can be prevented.

In this embodiment, the case where the bias voltage is controlled as the parameter controlled using the plasma impedance has been described, but the present invention is not limited to this. Other control parameters include, for example, the frequency or power of a high-frequency power supply for generating plasma, the frequency or voltage or power of a high-frequency power supply applied to the wafer stage, the temperature and temperature distribution of the vacuum chamber wall, the temperature and temperature of the wafer. The distribution, the processing pressure, the type and flow rate of the processing gas, the mixing ratio, the intensity and intensity distribution of the magnetic field applied to the plasma, the etching time, and the like are listed. It is also conceivable to control by combining a plurality of these parameters.

Further, the semiconductor product described by the processing method described in this embodiment has an important advantage as compared with a product manufactured without applying the method of this embodiment. that is,
Since the processing of the wafer is always performed within a certain range of conditions, the processing is performed with very high reproducibility, so that there is no variation in performance among products, that is, a highly reliable product. Therefore, since the yield at the time of manufacturing is good, the cost is low and the product is low in price.

In the present embodiment, the plasma impedance is obtained by calculation based on the potential of the wafer and the voltage and current at the exit of the matching box, and the etching parameters are controlled based on the results. Does not necessarily only control the etching parameters.
For example, plasma impedance may be used to monitor the etching state.In some cases, the potential of the wafer or the voltage or current at the exit of the matching box is monitored, and information on the change is used to determine when to stop the apparatus or to maintain the apparatus. It is also conceivable to decide. For example, when the number of etching processes is repeated while monitoring the wafer potential, and a sudden change in the wafer potential is recognized during a certain process, it can be easily predicted that some abnormality has occurred. In other words, it can be used as a monitor of whether or not the etching process is proceeding normally. In this case, it is possible to immediately determine that an abnormality has occurred in the apparatus, and it is possible to minimize waste of the wafer.

In this embodiment, a rod having a coil spring is used as the elastic member for supporting the stylus. However, this is not always necessary, and a leaf spring may be used. The important points are that the stylus has elasticity in the vertical direction, and that the position of the entire stylus can be arbitrarily adjusted in the vertical direction from the main body side.

Further, in this embodiment, the probe for measuring the potential of the wafer is a probe of a type that directly contacts the back surface of the wafer. However, the present invention is not limited to this. For example, a method in which a capacitance-type non-contact electrometer is embedded in a wafer stage and the potential of the wafer is measured using the non-contact electrometer may be considered. However, also in this case, since the absolute value of the voltage of the wafer may change depending on the mounting position of the electrometer, it is necessary to adopt a configuration in which the mounting position can be adjusted from outside the vacuum chamber as in this embodiment.

In this embodiment, the voltage of the wafer is actually measured in order to determine the impedance from the wafer to the ground via the plasma (plasma impedance).
However, it is also possible to calculate the impedance and the voltage of the wafer from the equivalent circuit model, the voltage 43Ve of the electrode connected to the exit of the matching box, and the current 44Ie flowing into the electrode. This method is effective in a process in which the degree of cleanliness due to abrasion powder (foreign matter) from the back surface of the wafer generated by the contact and sliding of the stylus of the wafer potential probe 24 on the back surface of the wafer is also an issue. . For example, foreign matter adhering to the back surface of the wafer is processed next to the plasma process (for example, wet cleaning).
This is the case where the data is transferred onto the surface of the wafer. This will be described below.

First, the phase difference θ is obtained by a computer arithmetic process which is obtained from the waveform Ve (t) of the electrode voltage 43Ve with time and the waveform Ie (t) of the current 44Ie with time. At this time, the impedance at the exit of the matching box is represented by an imaginary number and is set to a + bj. Here, a = Z / (1+ (tan θ) ² ) ^0.5 , b = Z * tan θ / (1+ (tan θ) ² ) ^0.5 , and Z = Ve / Ie. Similarly, the plasma impedance is represented by an imaginary number and is set to c + dj. The aforementioned plasma impedance Zp
Is the size of c + dj expressed as an imaginary number, in this case
(c ² + d ² ) ^0.5 . At this time, the combined impedance Ztotal from the outlet of the matching box to the ground via the plasma can be expressed by the following equation using the resistance component 39 (R (Ω)) and the capacitance component 40 (Xc (Ω)). Ztotal = (c + R * Xc 2 / (R 2 + Xc 2)) + (d-
R ² * Xc / (R ² + Xc ² )) j Since the total impedance Ztotal is equal to the impedance a + bj at the exit of the matching box, the real and imaginary components can be compared to obtain the values of c and d from the following equations. it can. Z / (1+ (tan θ) ² ) ^0.5 = c + R * Xc ² / (R ² + Xc ² ) Z * tan θ / (1+ (tan θ) ² ) ^0.5 = d−R ² * Xc / (R ²
+ Xc ² ) If the values of c and d are obtained, the plasma impedance Z
p and the wafer potential Vw are calculated by the following equations. Zp = (c ² + d ² ) ^0.5 Vw = Ie * Zp By calculating according to the above procedure, the voltage V of the wafer is obtained.
It is not necessary to measure w with the probe 24. Therefore,
The contact and sliding of the stylus of the wafer potential probe 24 on the back surface of the wafer does not cause wear powder (foreign matter) from the back surface of the wafer, thereby preventing the cleanness from being reduced. However, in the present embodiment, when the deposition film adheres to the wafer stage, the value of the equivalent circuit model itself changes, so that there is a problem that it is not accurate. However, it can be used as a method for monitoring a clean plasma impedance under conditions where the condition can be kept constant, such as processing while cleaning the surface of the wafer stage with plasma.

FIG. 12 is a flow chart showing a flow from obtaining the wafer potential Vw and the plasma impedance Zp by the above method and using the same. First, an equivalent circuit model from the high-frequency power supply (more precisely, the current / voltage probe) to the ground via the wafer stage in this embodiment is determined as shown in FIG. 3 (step 120). next,
The combined impedance from the current / voltage probe to the ground via the plasma is calculated (step 121). Next, using a current / voltage probe, the waveform Vw of the wafer potential
(t), the current waveform Ie (t) of the wafer stage is measured,
A phase difference is obtained (step 122). Next, based on these values, the impedance at the position of the current / voltage probe is calculated (step 123). Next, a comparison is made between the previously calculated combined impedance and the impedance determined in step 123 to determine the plasma impedance Zp,
The wafer potential Vw is calculated (Step 124). Ultimately, it should be determined by the user's judgment, but when monitoring the wafer potential Vw and the plasma impedance Zp, they are displayed on the display unit 80 (step 125) to control the process parameters. In this case, information is sent to the process parameter controller 82 to control the process parameters (step 126).

In the above method, the current Ie flowing into the electrode
Is always measured, but it is also possible to obtain Ie by calculation and calculate the plasma impedance. In this case, the voltage waveform V of the wafer is
The current waveform Ie (t) flowing through the circuit may be calculated based on w (t) and the voltage waveform Ve (t) of the electrode, and the impedance Zm of the dielectric film. At this time, the impedance Z of the dielectric film portion
d and the current waveform Ie (t) can be calculated by the following equation. ^{Zd = RXc 2 / (Xc 2} + R 2) -jXcR 2 / (Xc 2 +
From ^{R 2) Ie (t) =} (Vw (t) -Ve (t)) / Zd result, the plasma impedance Zp is calculated by the following equation. Zp = Vw / Ie Although three methods of calculating the plasma impedance have been described above, which method may be appropriately selected according to the process or the like.

FIG. 14 is a flow chart showing a flow from obtaining the wafer potential Vw and the plasma impedance Zp by the above-described method to using the same. First, an equivalent circuit model is determined as shown in FIG. 3 (step 140). next,
Wafer voltage waveform Vw (t) and wafer stage voltage waveform Ve by wafer potential probe and current / voltage probe
(t) is measured (step 141). Next, the current waveform Ie (t) of the wafer stage is calculated from the equivalent circuit model and the voltage waveform obtained in step 141 (step 14).
2). Next, the plasma impedance Zp is calculated (step 143). Ultimately, it should be determined by the user's judgment. However, when monitoring the wafer potential Vw and the plasma impedance Zp, they are displayed on the display unit 80 (step 145), and when the process parameters are controlled. Sends information to the process parameter controller 82 to control the process parameters (step 14).
6).

Conversely, if the potential of the wafer is calculated by the above-described equivalent circuit model while the potential of the wafer is actually measured by the wafer potential probe, the state of the deposit on the surface of the dielectric film on the wafer stage can be displayed on the display section 80. It becomes possible.
The procedure will be described with reference to FIG. First, a wafer potential Vw is measured by a wafer potential probe (step 130).
Next, the current waveform Ie (t) and the voltage waveform Ve (t) of the wafer stage are measured by the current / voltage probe, and the phase difference θ is obtained (step 131). Next, the wafer voltage Vw 'is calculated from Ie, Ve, and θ using the equivalent circuit model of FIG. 3 (step 132). Next, the wafer voltage Vw previously measured by the wafer potential probe and the wafer voltage V
The difference Vw-Vw 'of w' is obtained (step 133). If there is no problem without the deposition film being attached to the surface of the dielectric film or the surface of the dielectric film being etched and reduced, the potential of the wafer measured by the wafer potential probe is compared with the potential of the wafer. Since the wafer potentials calculated by the equivalent circuit substantially match, Vw-Vw 'takes a value close to zero. Specifically, the range of the value of Vw-Vw 'is determined in advance, and if within a certain range, the wafer potential Vw and the plasma impedance Zp are output. In this case, it is understood that the dielectric film has no problem. If the film thickness increases due to the deposition of the deposition film on the surface of the dielectric film, or the film thickness decreases due to etching, the difference between Vw and Vw 'exceeds a certain range. In this case, the value C of the capacitance 40 of the dielectric film in the equivalent circuit model is changed by ΔC (step 13).
4), the changed value C '(= C
Vw 'is calculated again based on (+ ΔC) to obtain Vw-Vw' (step 132). When the re-determined value Vw 'falls within the predetermined range as described above, a determination is made by obtaining ΔC, Vw, and Zp (step 1).
35). That is, when the value of ΔC in this case is positive, it means that the surface of the dielectric film is etched and the film thickness is reduced, and when the value of ΔC is negative, the deposition film is formed on the surface of the dielectric film. It can be determined that the film thickness has increased due to the adhesion. As described above, it can be used as a dielectric film monitor for a dielectric film. This processing is also applicable to the embodiment shown in FIG. Further, in the present embodiment, only the resistance component and the capacitance component of the dielectric film of the wafer stage are considered as the equivalent circuit model. However, the present invention is not limited to this, and the inductance component between the wafer stage and the high-frequency power source, and the wafer stage and the vacuum A capacity component or the like between the walls of the chamber may be included. In this case, more detailed calculation of the plasma impedance can be performed, and as a result, the effect of improving the accuracy and reproducibility of the monitor of the plasma processing can be expected.

As described above, the first embodiment holds when the condition of the inner wall of the processing chamber is not changed by the plasma processing or when a certain condition is maintained by the cleaning. There may be a problem under the condition that such a condition is formed. However, even in such a case, the problem can be avoided by adopting a configuration developed from this embodiment. This will be described below.

FIG. 4 shows the configuration of the second embodiment of the present invention. FIG. 5 shows an equivalent circuit model from a high-frequency power supply (more precisely, a current / voltage probe) to ground via a wafer stage in the second embodiment. In this embodiment, the process is performed in a process in which the adhesion film 65 adheres to the inner wall of the vacuum chamber. Since the impedance from the wafer to the ground changes due to the deposited film, the method of the first embodiment cannot accurately determine the plasma impedance. Therefore, in this embodiment, in order to obtain the impedance of the deposited film, in addition to the apparatus configuration of the first embodiment, a signal such as a film thickness probe 63 for measuring the potential of the plasma being processed and a signal such as the potential measured by the film thickness probe 63 An arithmetic circuit 64 for calculating the film thickness based on the calculation is provided. Thickness probe 6
3 and the arithmetic circuit 64 constitute a film thickness probe section. In addition,
The arithmetic circuit 64 may be provided in the computer 18. Examples of the film thickness probe include a quartz crystal film thickness meter and an optical film thickness meter using an interference wave. Using a film thickness probe, the thickness of the film adhering to the inner wall of the vacuum chamber can be measured, and the capacitance 67 and impedance of the adhering film can be calculated from the thickness of the film. For example, when an adhesion film having a relative dielectric constant of ε is attached to a region having a thickness T and an area S, the vacuum dielectric constant is set to ε _0.
If you, capacitance Cm becomes εε ₀ S / T. When the frequency of the high frequency power supply 13 is f, the impedance Zm of the film is 1
/ 2πfCm. If the plasma impedance Zp at this time is c + dj, the combined impedance from the wafer to the ground can be c + (d−Zm) j. According to the equivalent circuit model, a combined impedance Ztota of the resistance component 39 (R (Ω)) and the capacitance component 40 (Xc (Ω))
l can be expressed by the following equation. Ztotal = (c + R * Xc 2 / (R 2 + Xc 2)) + (d-
Zm−R ² * Xc / (R ² + Xc ² )) j Since this is the same as the impedance measured by the current / voltage probe, the real component and the imaginary component are compared to obtain the values of c and d from the following formula. be able to. The impedance at the exit of the matching box is a + as in the first embodiment.
When expressed as bj, it can be expressed as follows. a = Z / (1+ (tan θ) ² ) ^0.5 , b = Z * tan θ / (1+ (tan θ) ² ) ^0.5 , Z = Ve / Ie Therefore, by comparing the real number component and the imaginary number component, solving the drop equation c and d are obtained. Z / (1+ (tan θ) ² ) ^0.5 = c + R * Xc ² / (R ² + X
c ² ) Z * tan θ / (1+ (tan θ) ² ) ^0.5 = d−Zm−R ² * Xc
/ (R ² + Xc ² ) The magnitude of the plasma impedance at this time is (c ² + d ² )
It can be calculated with ^0.5 . Therefore, if the function of measuring the thickness of the adhered film is added to the first embodiment, the plasma impedance can be accurately measured even when the adhered substance adheres to the inner wall of the processing chamber and the state of the plasma changes. Can be calculated, and the state of the plasma can be monitored. In addition, since the wafer potential can be measured directly by a wafer potential probe or calculated by an equivalent circuit model and the measurement result of the current / voltage probe, controlling the wafer potential based on such information allows the wafer potential to be measured. The energy of the incident ions can be controlled.

FIG. 15 is a flow chart showing a flow from obtaining the wafer potential Vw and the plasma impedance Zp by the above-described method to using the same. First, based on the output of the film thickness probe 63, the thickness of the deposited film adhered to the inner wall of the processing chamber is measured (step 150). Next, the impedance of the deposition film is calculated (step 151). Next, an equivalent circuit model is determined (step 152). Next, a combined impedance from the current / voltage probe to the ground via the plasma and the deposition film is calculated (step 153). next,
Wafer potential waveform Vw using current / voltage probe
(t), the current waveform Ie (t) of the wafer stage is measured,
A phase difference is obtained (step 154). Next, the impedance at the position of the current / voltage probe is calculated (step 155). Next, the plasma impedance Zp and the wafer potential Vw are calculated by comparing the previously calculated combined impedance with the impedance obtained in step 155 (step 156). Ultimately, it should be determined by the user's judgment. However, when monitoring the wafer potential Vw and the plasma impedance Zp, the display unit 8
0 (step 157), and when controlling the process parameters, information is sent to the process parameter controller 82 to control the process parameters (step 1).
58).

Therefore, in this embodiment, various processing parameters can be controlled based on the plasma impedance as in the first embodiment, and a manufacturing apparatus with good reproducibility can be provided. Further, the product manufactured by this processing method has a feature that the performance is stable at a low price as in the first embodiment.

Further, effects different from those of the first embodiment which can be expected in this embodiment will be described. In a process in which a film adheres to the inner wall of the processing chamber, as the process is repeated, the thickness of the film gradually increases. When this film reaches a certain thickness, it peels off due to film stress, and when this film is put on a wafer, it may cause a product defect, which is a problem. On the other hand, if the thickness of the adhered film is monitored by the method described in the present embodiment, the cleaning time can be easily determined, and there is an effect of preventing a product defect from being caused by foreign matter.

FIG. 6 shows the configuration of a third embodiment of the present invention. In this embodiment, the susceptor 45 is arranged so as to surround the periphery of the wafer stage of the first embodiment. The susceptor 45 has a configuration in which a donut-shaped silicon plate 46 is attached to the surface of a ceramic cover facing the plasma 4. The silicon plate 46 is connected to a power supply rod 48 electrically insulated 47 from other components, and is connected to a power supply section at the exit of the matching box 14 via a variable capacitance capacitor 49 provided outside the vacuum chamber. Have been. A terminal 50 electrically connected to the back surface of the silicon plate is provided, and the terminal 50 is a susceptor potential probe 66 having a socket portion 51 electrically insulated from other components.
And pulled out of the vacuum chamber and taken into the computer 18 as in the first embodiment. Therefore,
If the potential of the core wire of the susceptor potential probe is measured with a voltmeter, the voltage of the silicon plate 46 during processing can be measured. Further, in order to measure the voltage of the silicon plate, in addition to the above configuration, the voltage of the power supply rod 48 connected to the silicon plate may be measured. The reason for disposing the silicon plate on the susceptor surface is to eliminate the non-uniform distribution of fluorine radicals generated in the wafer surface when a fluorine-based gas is used for the etching process of an oxide film or the like. In other words, the fluorine radicals in the plasma react with the silicon in the wafer to progress the etching. However, the consumption occurs in the region where the wafer actually exists and in the region where the silicon does not exist such as the susceptor. Since there is a difference in the amount of fluorine radicals to be performed, the amount of fluorine radicals differs near the center and the periphery of the wafer, resulting in a difference in the etching rate. Therefore, by arranging silicon also on the susceptor, the fluorine radicals are consumed to the same extent as the region where the wafer is present, so that a uniform distribution is obtained. Reference numeral 52 denotes a grounding member for preventing abnormal discharge from occurring when a high-frequency voltage is applied to the power supply rod.

In this embodiment, the bias power supplied from the matching box is changed by changing the capacitance of the capacitor 49 so as to positively control the distribution of fluorine radicals in the central region of the wafer and in the vicinity of the outer periphery. Distribute properly to silicon plate. Hereinafter, a method of obtaining the plasma impedance on the wafer and a method of distributing the bias power in the present embodiment will be described.

FIG. 7 shows an equivalent circuit model diagram of the third embodiment of the present invention. This equivalent circuit model is slightly more complicated than the equivalent circuit model of the first embodiment because the ground member 52 and the silicon plate 46 are added. For example,
53 is a capacitance component of a space existing between the electrode and the earth member, 54 is a capacitance component of a variable capacitance capacitor 49 connected to the silicon plate, and 55 is a capacitance component between the wafer and the silicon plate 46. . The values of the capacitance components 40, 53, and 55 can be obtained by experiments using a capacitance sensor when a high-frequency voltage having the same frequency as the bias voltage applied to the wafer stage is applied in an actual apparatus configuration. In this example, when the capacitance was actually measured, 40 was 3 nF, 53 at 800 kHz.
Was 0.3 nF and 55 was 0.1 nF. When such an equivalent circuit is known in advance, the plasma impedance 56Zw on the wafer and the plasma impedance 57Zs on the silicon plate can be calculated by the following procedure. First, the waveform Ve (t) of the electrode voltage (in this case, equal to the potential of the wafer stage) 43 and the current flowing out of the matching box are measured by the current / voltage probe 17 provided between the exit of the matching box and the electrode. The waveform Ie (t) at 44 is measured. Next, the wafer voltage waveform Vw (t) during processing is measured using the same wafer potential probe 24 as the probe of the first embodiment. Also, terminal 5
By measuring the voltage of 0 with a voltmeter, the waveform Vs (t) of the potential 58 of the silicon plate being processed is obtained. Current 4
Current flowing into the silicon plate side of 4Ie (t) 5
9Is (t) indicates the impedance of the capacitor 54 as Zc
Then, it is obtained by the following equation. Is (t) = (Vs (t) -Ve (t)) / Zc Here, the impedance Zc can be easily calculated from the frequency of the bias voltage and the capacitance of the capacitor 54. The current flowing to the ground via the capacitor 53 can be calculated by Ve (t) / Z, where Z is the impedance of the capacitor 53.

Therefore, of the current 44Ie (t), the current value 60Iw (t) flowing on the wafer side is obtained by the following equation. Iw (t) = Ie (t) -Is (t) -Ve (t) / Z Also, the current 61I flowing between the wafer and the silicon plate
ws (t) is obtained by the following equation, where Zws is the impedance between the wafer and the silicon plate. Iws (t) = (Vw (t) -Vs (t)) / Zws From the above, the plasma impedance 56Zw on the wafer is obtained.
And plasma impedance 57Z on silicon plate
The current values 62Izw (t) and 63Izs (t) flowing into s are obtained by the following equations. Izw (t) = Iw (t) −Iws (t) Izs (t) = Is (t) + Iws (t) Since the voltages Vw (t) and Vs (t) are measured, respectively, Zw and Zs Are respectively obtained by the following equations. Zw = Vw (t) / Izw (t) Zs = Vs (t) / Izs (t) In this configuration, by changing the capacitance of the variable capacitor 54, the bias power applied to the wafer and the silicon plate can be arbitrarily set. Can be changed to Therefore, in the etching of the oxide film, the consumption of fluorine radicals can be controlled, so that the etching distribution in the wafer surface can be controlled. Further, since the potentials of the wafer and the silicon plate being processed and the impedance to the ground via the plasma can be measured at the same time, the etching conditions can be controlled based on this signal.

The plasma impedance Zw and Zs, the wafer potential Vw and the susceptor potential Vs
Is shown in FIG. First, an equivalent circuit model in the present embodiment shown in FIG. 7 is determined (step 160). Next, the voltage waveform Vw (t) of the wafer, the voltage waveform Vs (t) of the susceptor, the current waveform Ie (t) of the wafer stage, and the voltage waveform Ve ( t) is measured (step 16)
1). Next, the current waveform I flowing into the plasma from the wafer
zw (t) and the current waveform I flowing into the plasma from the susceptor
zs (t) is calculated (step 162). Next, the plasma impedances Zw and Zs are calculated (step 16).
3). Ultimately, it should be determined by the user's judgment, but when monitoring the wafer potential Vw, the susceptor potential Vs, and the plasma impedances Zw, Zs, they are displayed on the display unit 80 (step 165). If the process parameters are to be controlled, information is sent to the process parameter controller 82 to control the process parameters (step 166).

An example in which the oxide film is etched by using a fluorine-based gas will be described below. While the etching process was continuously performed while simultaneously monitoring the wafer potential during processing, the silicon plate potential, the plasma impedance on the wafer, and the plasma impedance on the silicon plate, the potential of the silicon plate gradually increased after a certain number of processed wafers. Phenomena. From past experience, it was known that the possibility of deposits adhering to the silicon plate was high, albeit little by little, at the number of processed wafers at which the potential began to rise.In this case, the capacity of the variable capacitor was increased. Then, of the high-frequency bias applied to the electrode, a larger power was applied to the silicon plate to clean the deposited material. As a result, it was possible to quickly return to normal processing conditions. In this example, the conventional method takes a procedure of investigating the cause for the first time after the occurrence of an etching defect and taking a countermeasure, so that it takes time and the cost of wasted wafers affects the manufacturing cost. However, this embodiment has an advantage that the progress of the etching can be grasped while the etching is being performed, so that it is possible to respond quickly. Therefore, it is possible to keep the operation rate of the device high and the manufacturing cost low.

Further, if a sudden change is observed while monitoring the plasma impedance during the etching or the voltage of the wafer or the silicon susceptor, it is highly likely that some problem has occurred. In addition, it is possible to immediately take measures such as stopping the apparatus, so that waste of wafers can be minimized. That is, the effect of improving the operation rate of the device and reducing the manufacturing cost can be expected.

In this embodiment, a variable capacitance type capacitor is used to control the amount of bias power distribution from the matching box outlet to the wafer stage and the silicon plate, but this is not always necessary. For example,
It is also possible to apply a bias voltage using another power supply different from the power supply for applying the bias voltage to the wafer stage. However, if it is necessary to align the bias voltage applied to the wafer stage with the bias voltage applied to the silicon plate from the viewpoint of process control,
It is also possible to provide a phase controller separately to make the phases coincide.

In the above description of the embodiment, the potential of the wafer or the impedance from the wafer to the ground, or the voltage of the susceptor and the impedance from the susceptor to the ground are monitored to detect the occurrence of abnormalities, and to check the wafer stage and the silicon plate on the susceptor. Although the high-frequency power applied to one or both of them has been controlled, it is not necessarily limited to this. For example, correlations between phenomena such as an etching rate and an etching rate distribution in a wafer surface, a thickness of a deposited film deposited in a vacuum chamber, a state of chucking of a wafer by an electrostatic chuck, and occurrence of element damage, and wafer potential and plasma impedance. Is known in advance, it is possible to actively change the etching parameters and determine the cleaning time by sequentially comparing the wafer potential and the plasma impedance during wafer processing. Therefore, the effects of improving the yield and reducing the manufacturing cost can be expected.

In this embodiment, as shown in the first embodiment and the second embodiment, Zs and Zw are set to a voltage of 4 from the back surface.
2 and 58 cannot be obtained by calculation from the equivalent circuit model without measurement. The reason is the real number components of Zw and Zs,
This is because, while there are a total of four imaginary components each of two, only one real component and one imaginary component of the point where Ve43 and Ie44 are measured can be obtained. However, in practice, it can be easily calculated by assuming that, for example, Zw and Zs are distributed by the ratio of the area facing the plasma. In this case, as described in the first and second embodiments, the total combined impedance is calculated and calculated.
It can be calculated by comparing the impedance at the measurement points of e and Ie. With this configuration, it is not necessary to directly measure the voltage of the wafer or the voltage of the silicon plate, so that a cleaner monitoring method can be provided.

FIG. 8 shows the configuration of the fourth embodiment of the present invention. FIG. 9 shows an equivalent circuit model from a high-frequency power supply (more precisely, a current / voltage probe) to ground via a wafer stage in the fourth embodiment. In the present embodiment, a process in which the adhesion film 65 adheres to the inner wall of the vacuum chamber as in the second embodiment is performed. Thus, for the same reason as in the second embodiment, in this embodiment, in order to obtain the impedance of the deposited film, in addition to the apparatus configuration of the third embodiment, the thickness of the film deposited on the inner wall of the vacuum chamber is measured. Probe 6
3. An arithmetic circuit 64 is provided. The thickness can be measured by using the thickness probe, and the capacitance Cm and the impedance Zm can be calculated by the same procedure as described in the second embodiment. Therefore, by adding and calculating the capacitance Cm to the equivalent circuit model of the third embodiment,
The plasma impedance on the wafer and the plasma impedance on the susceptor can be calculated.

Therefore, if the function of measuring the thickness of the deposited film is added, it is possible to accurately calculate the plasma impedance even if the deposited material adheres to the inner wall of the processing chamber and the state of the plasma changes. And the state of the plasma can be monitored. In addition, since the potential of the wafer and the potential of the susceptor can be measured directly by a potential probe or can be calculated by the measurement result of the current / voltage probe and an equivalent circuit model, the energy of ions incident on the wafer must be controlled. Can be.

Although the present invention has been described using an example in which the present invention is applied to a dry etcher, a great effect can be expected also when applied to a plasma CVD apparatus. For example, in a plasma CVD apparatus, since a film is formed on a wafer using plasma, a large amount of deposits adhere to the inner wall of a vacuum chamber. If the deposited material exceeds a certain thickness, there is a problem that the deposited material comes off the inner wall of the chamber and contaminates the wafer. However, according to the method of the present embodiment, the thickness of the film adhered to the inner wall of the processing chamber can be predicted, so that the cleaning time can be determined before a product defect is caused. In this case, since the wafer is not wasted, the manufacturing cost can be reduced. In addition, since the wafer potential and the plasma impedance can be monitored with high accuracy, the ion energy incident on the wafer can be controlled by controlling the applied high-frequency voltage based thereon, so that etching with good reproducibility can be realized. As a result, an improvement in yield can be expected, and as a result, there is an effect of reducing costs.

[0065]

As described above, according to the present invention, the potential of a wafer being processed by plasma and the current flowing in plasma can be measured, so that the wafer potential and plasma impedance can be accurately obtained. By controlling the etching parameters based on this information and controlling the ion energy, etching with good reproducibility can be achieved, and a decrease in yield can be prevented. That is, a semiconductor manufacturing apparatus with low manufacturing cost can be provided.

Further, since the potential of the wafer during processing can be directly monitored, when a rapid change in the wafer potential is observed, it is possible to quickly determine that an etching abnormality has occurred, and to waste the wafer. Can be expected to be minimized, that is, the effect of reducing the manufacturing cost can be expected.

Further, according to the present invention, it is possible to measure the potential of the wafer being processed by the plasma, the potential of the silicon susceptor disposed around the wafer, the current flowing into the plasma from the wafer, and the current flowing into the plasma from the silicon susceptor. , The plasma impedance on the wafer and the plasma impedance on the silicon susceptor can be calculated. Therefore, by controlling the etching conditions based on the information on the wafer potential and the plasma impedance, it is possible to provide a semiconductor manufacturing apparatus capable of performing etching with good reproducibility.

According to the present invention, since the high-frequency voltage applied to the wafer and the high-frequency voltage applied to the silicon plate can be distributed, the distribution of plasma incident on the wafer can be controlled. Therefore, a semiconductor manufacturing apparatus capable of controlling the etching distribution in the wafer plane can be provided.

Further, according to the present invention, it is possible to provide a probe capable of measuring the wafer potential during processing with plasma from the back surface of the wafer.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a plasma etching apparatus according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a configuration example of a wafer potential probe used in the present invention.

FIG. 3 is an equivalent circuit diagram of a main part of the first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration example of a plasma etching apparatus according to a second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of a main part of a second embodiment of the present invention.

FIG. 6 is a diagram showing a configuration example of a plasma etching apparatus according to a third embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of a main part of a third embodiment of the present invention.

FIG. 8 is a diagram showing a configuration example of a plasma etching apparatus according to a fourth embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of a main part of a fourth embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram of a main part of a conventional plasma etching apparatus.

FIG. 11 is a flowchart illustrating impedance calculation processing according to the first embodiment.

FIG. 12 is a flowchart illustrating another calculation process of impedance in the first embodiment.

FIG. 13 is a flowchart illustrating a monitoring process of a state of a deposit on the surface of a dielectric film of a wafer stage in the first embodiment.

FIG. 14 is a flowchart illustrating a process of using the obtained plasma impedance in the first embodiment.

FIG. 15 is a flowchart for explaining impedance calculation processing in the second embodiment.

FIG. 16 is a flowchart for explaining another impedance calculation process in the third embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Processing gas, 2 ... High frequency power supply, 3 ... Coil, 4 ... Plasma, 5 ... Semiconductor wafer, 6 ... Wafer stage, 7 ... Dielectric film, 8 ... Electrode, 9 ... Insulating plate, 10 ... Vacuum chamber, 1
DESCRIPTION OF SYMBOLS 1 ... Flange, 12, 48 ... Power supply rod, 13 ... High frequency power supply, 14 ... Matching box, 15, 20 ... Coil,
16: variable capacity capacitor, 17: current / voltage probe, 18: computer, 19: DC power supply, 21: cover, 22: turbo molecular pump, 23: dry pump, 2
4 ... Wafer potential probe, 25 ... Flange, 26 ... Female screw, 27 ... Terminal, 28 ... Male screw, 29,70 ... O-ring, 30 ... Flange upper inner surface, 31 ... Nut, 32 ...
Connecting rod, 33 socket, 34 spring stop, 35 coil spring, 36 stylus, 37 earth, 38 plasma impedance, 39 resistive component of dielectric film, 40 capacitive component of dielectric film, 41 blocking Capacitor, 42: Wafer potential, 43: Electrode voltage, 44, 59, 60, 6
1, 72, 73: current, 45: susceptor, 46: silicon plate, 47: insulation, 49: variable capacitance capacitor,
Reference numeral 50: terminal, 51: socket, 52: ground member, 53
... Capacitance between electrode and earth member, 54 ... Capacitance variable capacitor, 55 ... Capacitance between wafer and silicon plate, 56 ... Plasma impedance on wafer, 57 ...
Plasma impedance on silicon plate, 58 ...
Silicon plate potential, 62: insulating cylinder, 63: film thickness probe, 64: arithmetic circuit, 65: deposited film, 66: susceptor potential probe, 67: capacitance of deposited film, 68: insulating pipe, 69: core wire, 71 ... insulating pipe, 80 ... display unit,
82: Parameter control device.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Ryoji Nishio 502, Kandate-cho, Tsuchiura-shi, Ibaraki Pref. Inside the Machine Research Laboratory, Hitachi, Ltd. Inside the Machinery Research Laboratory (72) Inventor Junichi Tanaka 502 Kandachicho, Tsuchiura-shi, Ibaraki Prefecture Inside the Machinery Research Laboratory, Hitachi Ltd. (72) Inventor Saburo Kanai 794, Higashi-Toyoi, Kazamatsu City, Yamaguchi Prefecture Kasado Hitachi In-house (72) Inventor Kazuyuki Ikenaga 502, Kandachicho, Tsuchiura-shi, Ibaraki F-term in Machinery Research Laboratories, Hitachi, Ltd.F-term (reference)

Claims (29)

[Claims] 1. A semiconductor manufacturing apparatus for processing a semiconductor wafer, a unit for generating plasma in a vacuum processing chamber, a wafer stage for holding a semiconductor wafer introduced into the vacuum processing chamber, and a high-frequency voltage applied to the wafer stage. A high-frequency power supply for applying voltage, a wafer potential probe for measuring a voltage of the semiconductor wafer on the back surface of the semiconductor wafer, and a current / voltage for measuring at least one of a voltage and a current applied to the wafer stage from the high-frequency power supply A probe, a voltage value of the semiconductor wafer measured by the wafer potential probe, and a voltage value or a current value measured by the current / voltage probe, based on the impedance from the semiconductor wafer to ground via plasma. A calculation unit to be obtained, and based on the obtained impedance. And a processing unit for performing processing. 2. The semiconductor manufacturing apparatus according to claim 1,
The said manufacturing part displays the calculated | required impedance on a display part, The semiconductor manufacturing apparatus characterized by the above-mentioned. 3. The semiconductor manufacturing apparatus according to claim 1, wherein
The semiconductor manufacturing apparatus, wherein the processing unit controls various processing parameters based on the obtained impedance. 4. The semiconductor manufacturing apparatus according to claim 3, wherein
A semiconductor, wherein the processing unit sets the obtained impedance as an impedance from the semiconductor wafer to the inner wall of the vacuum processing chamber via plasma, and controls the various processing parameters based on the obtained impedance. manufacturing device. 5. The semiconductor manufacturing apparatus according to claim 3,
The various processing parameters, the frequency or power of the high-frequency voltage for generating the plasma, or the frequency or power of the high-frequency voltage applied to the wafer stage, or the temperature or temperature distribution of the wall forming the vacuum processing chamber, Or at least one of the temperature or temperature distribution of the semiconductor wafer, the pressure of the vacuum processing chamber, the type or flow rate of the processing gas flowing into the vacuum processing chamber, and the mixing ratio of the processing gas, or the magnetic field applied to the vacuum processing chamber Or at least one type of etching time. 6. A semiconductor manufacturing apparatus for processing a semiconductor wafer, a unit for generating plasma in a vacuum processing chamber, a wafer stage for holding a semiconductor wafer introduced into the vacuum processing chamber, and a high-frequency voltage applied to the wafer stage. A high-frequency power supply for applying a voltage, a current / voltage probe that measures at least one of a voltage and a current applied to the wafer stage from the high-frequency power supply, and a voltage value or a current value measured by the current / voltage probe. The impedance at the position of the current / voltage probe is determined based on the calculated impedance, and the calculated impedance and the combined impedance of a previously prepared equivalent circuit model from the current / voltage probe to the ground via the wafer stage are calculated. From the semiconductor wafer via plasma. A calculation unit for calculating an impedance to a semiconductor manufacturing device, characterized in that it comprises a processing unit that performs processing based on the impedance thus calculated. 7. The semiconductor manufacturing apparatus according to claim 6, wherein
The semiconductor manufacturing apparatus, wherein the processing unit displays the calculated impedance on a display unit. 8. The semiconductor manufacturing apparatus according to claim 6, wherein
The semiconductor manufacturing apparatus, wherein the processing unit controls various processing parameters based on the calculated impedance. 9. The semiconductor manufacturing apparatus according to claim 8, wherein
The processing unit, wherein the calculated impedance is defined as an impedance from the semiconductor wafer to the inner wall of the vacuum processing chamber via plasma, and the various processing parameters are controlled based on the calculated impedance. manufacturing device. 10. The semiconductor manufacturing apparatus according to claim 6, wherein the various processing parameters include a frequency or power of a high-frequency voltage for generating the plasma, a frequency or power of a high-frequency voltage applied to the wafer stage, Or the temperature or temperature distribution of the wall forming the vacuum processing chamber, or the temperature or temperature distribution of the semiconductor wafer, or the pressure of the vacuum processing chamber, the type or flow rate of the processing gas flowing into the vacuum processing chamber, or the mixing of the processing gas A semiconductor manufacturing apparatus, wherein at least one of the ratios, the magnetic field applied to the vacuum processing chamber, or the etching time is at least one or more. 11. A semiconductor manufacturing apparatus for processing a semiconductor wafer, a unit for generating plasma in a vacuum processing chamber, a wafer stage for holding a semiconductor wafer introduced into the vacuum processing chamber, and a high-frequency voltage applied to the wafer stage. A high-frequency power supply for applying voltage, a wafer potential probe for measuring a voltage of the semiconductor wafer on the back surface of the semiconductor wafer, and a current / voltage for measuring at least one of a voltage and a current applied to the wafer stage from the high-frequency power supply A probe, a film thickness probe unit for measuring a thickness of a film adhered to an inner wall of the vacuum processing chamber, and the calculation unit comprises: a voltage value of the semiconductor wafer measured by the wafer potential probe; A plasma from the semiconductor wafer based on the voltage value or the current value measured by the probe. The first impedance to ground through the mask is determined, and the second impedance of the deposited film is determined from the thickness of the film deposited on the inner wall of the processing chamber measured by the film thickness probe unit. A semiconductor manufacturing apparatus, comprising: a calculation unit that calculates the impedance of the plasma using the first and second impedances; and a processing unit that performs a process based on at least one of the obtained first and second impedances. 12. The semiconductor manufacturing apparatus according to claim 11, wherein the processing unit displays at least one of the obtained first and second impedances on a display unit. 13. The semiconductor manufacturing apparatus according to claim 11, wherein said processing unit controls various processing parameters based on at least one of said first and second impedances obtained. apparatus. 14. The semiconductor manufacturing apparatus according to claim 13, wherein the processing unit sets the obtained first impedance as an impedance from the semiconductor wafer to the inner wall of the vacuum processing chamber via plasma. A semiconductor manufacturing apparatus, wherein the various processing parameters are controlled based on one impedance. 15. A semiconductor manufacturing apparatus for processing a semiconductor wafer, a unit for generating plasma in a vacuum processing chamber, a wafer stage for holding a semiconductor wafer introduced into the vacuum processing chamber, and a high-frequency voltage applied to the wafer stage. A high-frequency power supply for applying a voltage, a current / voltage probe for measuring at least one of a voltage and a current applied to the wafer stage from the high-frequency power supply, and measuring a thickness of a film attached to an inner wall of the vacuum processing chamber. A film thickness probe unit, a first impedance at the position of the current / voltage probe is obtained based on the voltage value or the current value measured by the current / voltage probe, and the processing chamber measured by the film thickness probe unit. The second impedance of the deposited film is determined from the thickness of the film deposited on the wall, and the first and second impedances are determined. And the combined impedance of the equivalent circuit model from the previously prepared current / voltage probe to the ground via the wafer stage is calculated, and the inner wall of the vacuum processing chamber through the plasma from the semiconductor wafer is processed. And a processing unit for performing processing based on the calculated impedance. 16. The semiconductor manufacturing apparatus according to claim 15, wherein said processing section displays the calculated impedance on a display section. 17. The semiconductor manufacturing apparatus according to claim 15, wherein said processing unit controls various processing parameters based on the calculated impedance. 18. A semiconductor manufacturing apparatus for processing a semiconductor wafer, a unit for generating plasma in a vacuum processing chamber, a wafer stage for holding a semiconductor wafer to be introduced into the vacuum processing chamber, and an outer periphery of the wafer stage. A susceptor disposed so as to surround; a high-frequency power supply for applying a high-frequency voltage to at least one of the wafer stage and the susceptor; a wafer potential probe for measuring a voltage of the semiconductor wafer on a back surface of the semiconductor wafer; A current / voltage probe for measuring at least one of a voltage and a current applied to the wafer stage from a high-frequency power supply; a susceptor potential probe for measuring the voltage of the susceptor; and a voltage value of the semiconductor wafer measured by the wafer potential probe. And the current / voltage probe A voltage value or current value, based on the voltage value measured from the susceptor potential probe, the first impedance from the semiconductor wafer to ground via the plasma,
A semiconductor manufacturing apparatus comprising: a calculating unit for calculating a second impedance from the susceptor to the ground via plasma; and a processing unit for performing processing based on at least one of the obtained first and second impedances. . 19. The semiconductor manufacturing apparatus according to claim 18, wherein said processing unit displays at least one of the obtained first and second impedances on a display unit. 20. A semiconductor manufacturing apparatus according to claim 18, wherein said processing section controls various processing parameters based on at least one of said first and second impedances obtained. apparatus. 21. The semiconductor manufacturing apparatus according to claim 20, wherein the processing section sets the obtained first impedance as an impedance from the semiconductor wafer to the inner wall of the vacuum processing chamber via plasma. A semiconductor manufacturing apparatus, wherein the various processing parameters are controlled based on one impedance. 22. A semiconductor manufacturing apparatus for processing a semiconductor wafer, a unit for generating plasma in a vacuum processing chamber, a wafer stage for holding a semiconductor wafer introduced into the vacuum processing chamber, and an outer periphery of the wafer stage. A susceptor disposed so as to surround; a high-frequency power supply for applying a high-frequency voltage to at least one of the wafer stage and the susceptor; a wafer potential probe for measuring a voltage of the semiconductor wafer on a back surface of the semiconductor wafer; A current / voltage probe for measuring at least one of a voltage and a current applied to the wafer stage from a high-frequency power supply, a susceptor potential probe for measuring the voltage of the susceptor, and a thickness of a film attached to an inner wall of the vacuum processing chamber. Measured by the film thickness probe part to be measured and the wafer potential probe The voltage value of the semiconductor wafer, the voltage value or the current value measured by the current / voltage probe, and the voltage value measured by the susceptor potential probe, from the semiconductor wafer to the ground via the plasma. A first impedance,
A second impedance from the susceptor to the ground through plasma and a third impedance of the deposited film are determined from the thickness of the film deposited on the inner wall of the processing chamber measured by the film thickness probe unit. And a fourth impedance from the wafer surface to the film attached to the inner wall of the vacuum processing chamber and a fifth impedance from the susceptor surface to the film attached to the inner wall of the vacuum processing chamber using the second and third impedances. And a processing unit that performs a process based on at least one of the obtained fourth and fifth impedances. 23. The semiconductor manufacturing apparatus according to claim 22, wherein said processing section displays at least one of the obtained fourth and fifth impedances on a display section. 24. The semiconductor manufacturing apparatus according to claim 22, wherein said processing unit controls various processing parameters based on at least one of the obtained fourth and fifth impedances. apparatus. 25. The semiconductor manufacturing apparatus according to claim 24, wherein the processing unit sets the obtained fourth and fifth impedances as impedances from the semiconductor wafer to the inner wall of the vacuum processing chamber via plasma. A semiconductor manufacturing apparatus, wherein the various processing parameters are controlled based on the obtained first impedance. 26. A semiconductor manufacturing apparatus for processing a semiconductor wafer, comprising: a unit for generating plasma in a vacuum processing chamber; a wafer stage for holding a semiconductor wafer to be introduced into the vacuum processing chamber; A susceptor arranged to surround, a high-frequency power supply for applying a high-frequency voltage independently to the wafer stage and the susceptor, a wafer potential probe for measuring the voltage of the semiconductor wafer on the back surface of the semiconductor wafer, A current / voltage probe for measuring at least one of a voltage and a current applied to the wafer stage from the high-frequency power supply; a susceptor potential probe for measuring the voltage of the susceptor; and a voltage of the semiconductor wafer measured by the wafer potential probe. Value and measured by the current / voltage probe A semiconductor manufacturing apparatus comprising: a control unit that independently controls a high-frequency voltage applied to the wafer stage and the susceptor based on a pressure value or a current value and a voltage value measured by the susceptor potential probe. . 27. A unit for generating plasma in a vacuum processing chamber, a wafer stage for holding a semiconductor wafer to be introduced into the vacuum processing chamber, and a high frequency power supply for applying a high frequency voltage to the wafer stage. In the semiconductor manufacturing apparatus, a method of processing a semiconductor wafer includes: measuring a voltage of the semiconductor wafer on a back surface of the semiconductor wafer; and measuring at least one of a voltage and a current applied to a wafer stage from the high-frequency power supply. And determining the impedance from the semiconductor wafer to the ground via the plasma based on the voltage value of the semiconductor wafer measured by the wafer potential probe and the voltage value or the current value measured by the current / voltage probe. And a step based on the obtained impedance. Performing a process. 28. A unit for generating plasma in a vacuum processing chamber, a wafer stage for holding a semiconductor wafer introduced into the vacuum processing chamber, and a high-frequency power supply for applying a high-frequency voltage to the wafer stage. In the semiconductor manufacturing apparatus, a method of processing a semiconductor wafer includes: measuring at least one of a voltage and a current applied to the wafer stage from the high-frequency power supply; and a voltage value or a current value measured by the current / voltage probe. The impedance at the position of the current / voltage probe is calculated based on the calculated impedance, and the calculated impedance and the combined impedance of a previously prepared equivalent circuit model from the current / voltage probe to the ground via the wafer stage are calculated. Process through the plasma from the semiconductor wafer Semiconductor processing method characterized by comprising the step of calculating the impedance to over scan, and performing a process based on the impedance thus calculated. 29. A wafer potential probe in a semiconductor manufacturing apparatus for processing a semiconductor wafer using plasma, comprising: an electrically conductive stylus in contact with a back surface of a semiconductor wafer to be measured; and an electric stylus supporting the stylus. An elastic member having conductivity; and a current introduction terminal having a flange structure while supporting the elastic member. The electric potential of the stylus can be measured on the atmosphere side, and a position in a height direction of the stylus. Is a wafer potential probe that can be adjusted from the atmosphere side.