JP2001337637A - Display device driver system and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a noise countermeasure taken to an analog picture signal while the picture signal is fed to a display device. SOLUTION: A frequency range of the digital picture signal DT is lowered by developing into plural phases through the sampling memory circuit 13. Then, the digital picture signal is converted to an analog signal though the digital - analog (D/A) converter 15a..., and an obtained low-frequency with high amplitude analog picture signal is fed to the display device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive system and a display device for a display device having display elements arranged in a matrix, and more particularly to a display video signal developed into a plurality of phases and supplied to the display device. The present invention relates to a display device drive system and a display device.

[0002]

2. Description of the Related Art Images having display elements in a matrix form
Various display devices, which are devices for displaying images, have been developed, and one of them is to drive an LCD (liquid crystal display) panel using a polysilicon TFT (thin film transistor).

[0003] A polysilicon TFT-LCD panel utilizes a higher transistor performance than an amorphous silicon TFT-LCD panel, and incorporates a circuit for driving a scanning signal line and a data signal line of the panel into the panel. . However, the polysilicon T
Although the transistor performance of the FT is high, the performance is inferior when compared with the signal line driver LSI made of single crystal silicon, and there is no problem in the circuit for driving the scanning signal line. When driving signal lines, it is often difficult to drive a panel with the same operation as a driver LSI. Although there is no problem with video frequency bands such as NTSC and PAL, which are conventional television systems, the video frequency band is several tens of MHz according to the video display standard of a computer. It is difficult to individually sample signals at timings necessary for the above. When the video frequency band is high as described above, the video signal is divided into a plurality of phases by an external circuit to reduce the frequency band so that a band corresponding to the transistor performance is obtained, and a plurality of analog video signals are applied to a panel. , And the panel is driven by an operation of simultaneously sampling a plurality of data signal lines in the panel.

[0004] A drive system for producing a plurality of phases of analog video signals generally used in the past has a configuration as shown in FIG. FIG. 1 is a block diagram of a driving system for a conventional display device.
I. First, briefly, the red digital video signal DR, the green digital video signal DG, the blue digital video signal DB, and the clock signal CK are D / A.
The red analog video signal A
R, green analog video signal AG, and blue analog video signal AB are output. It is the analog signal processing circuit 12
2, the signal is input to an amplifier circuit 123 including an inverting amplifier circuit IA and a non-inverting amplifier circuit NA.
The signal is input to an analog switch (ASW) 124 together with C and output as a high-frequency large-amplitude analog video signal.
This is input to a sample-and-hold circuit (SH) 125 together with a sample-and-hold control signal SHC, is expanded into a plurality of phases, and is output as a large-amplitude analog video signal whose frequency is reduced.

[0005] That is, while the dot configuration of the panel is physically determined, the video signal standard to be displayed varies widely, such as NTSC or PAL of a television system, or VGA, SVGA, or XGA of a computer. Generally, the signal is once converted into a digital signal and converted into a signal in a format suitable for the dot configuration of the panel. Other processes such as signal correction and adjustment are performed together when the digital signal is more convenient. The processed digital signal is converted to a high-speed video signal D / A (digital /
(Analog) A converter LSI converts the signal into an analog signal, and when analog signal correction is necessary, the signal is corrected. Then, the video signal is amplified to a voltage required for driving the LCD panel, and an inverted and amplified signal for driving the LCD AC is added, thereby obtaining a high-frequency large-amplitude analog video signal. This is developed into a plurality of phases using a sample and hold circuit to create a video signal suitable for an LCD panel.

[0006]

However, the method of expanding a high-frequency large-amplitude analog video signal, which has been generally used in the past, into a plurality of phases of video signals by using a sample-and-hold circuit has a problem of unnecessary radiation. Therefore, handling high-frequency video signals must be delicate. This is because the noise mixed into the video signal affects the final display and must be suppressed, and at the same time, the high-frequency large-amplitude analog video signal itself becomes a noise source and affects other signals. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to produce an analog video signal to be supplied to the LCD panel by processing a very delicate high-frequency large-amplitude analog video signal in an intermediate processing. It is an object of the present invention to provide a display device drive system and a display device that do not need to be manufactured by using the method described above and have low noise.

[0008]

In order to solve the above-mentioned problems, a display device driving system according to the present invention comprises display elements arranged in a matrix, and scan signal lines and data signals are provided based on input display video signals. A data signal bus line for supplying a data signal to the data signal line with a plurality of the data signal lines as one set for a display device for controlling a line and displaying an image indicated by the display video signal. The same number of data signal lines in one set of data signal lines are prepared, the display video signal is expanded into a plurality of phases, whereby the signal frequency is reduced by the divided number, and Signal level change point timing is aligned for all data signal bus lines, and one data signal line is driven at a time based on the display video signal. An analog video signal holding the signal level for each time assigned in each case for the time assigned to one set of the data signal lines is supplied to the data signal bus line, and the same set of data signal lines are applied at the same timing. In a display device drive system that operates to sequentially drive data signal lines for each set, a developing unit that expands the display video signal input as a digital video signal into a plurality of phases, A digital-analog conversion circuit for converting the digital video signal into an analog video signal.

With the above configuration, in order to supplement the drive performance of the display device, a driving method is employed in which an analog video signal obtained by expanding the display video signal of the display device into a plurality of phases is supplied to the display device. Prepare the display video signal in the form of a digital signal by temporarily converting the display video signal into a digital signal in order to perform format conversion, adjustment, and correction.
Then, in the display device drive system that converts the display video signal from a digital video signal to an analog video signal, the display video signal is developed into a plurality of phases at the stage of the digital video signal.

That is, the display video signal is input as a digital video signal by temporarily converting the display video signal into a digital signal, and then the display video signal is converted into a plurality of phases at the stage of the digital video signal by the expanding means. By developing the digital video signal, the frequency band is lowered as it is. Thereafter, it is converted into an analog signal, and the low-frequency, large-amplitude analog video signal thus obtained is supplied to a display device.

Therefore, a high-frequency large-amplitude analog video signal is not generated, and the large-amplitude analog video signal can be a signal dropped to a low frequency band and given to the LCD panel. Therefore, unnecessary radiation can be suppressed to a low level, and measures against noise can be simplified as compared with the related art. That is, according to this configuration, it is possible to simplify the noise countermeasures performed on the analog video signal.

In general, high-frequency signals having a large amplitude are extremely difficult to design because single-crystal silicon devices are required to operate at the performance limit. However, according to the present invention, since a high-frequency large-amplitude analog video signal is not created, design can be performed relatively easily. Therefore, a polysilicon TF is used for a display device that performs the driving described above.
A T-LCD may be used.

Since no high-frequency large-amplitude analog video signal is created, power consumption can be reduced accordingly.

Further, by realizing a drive system conventionally using a plurality of LSIs with one type of LSI, it is possible to suppress power loss caused by signal transmission between the LSIs and reduce power consumption. Can be.

In addition, since a high-frequency large-amplitude analog video signal is not generated as described above, a circuit for processing high-frequency signals can be operated at a low voltage, so that high-speed operation can be achieved by miniaturization, operation is stabilized, and unnecessary radiation is reduced. Level. That is, in general, recent LSI manufacturing processes have advanced in the direction of fine processing, and higher-speed signal processing has become possible. On the other hand, the breakdown voltage has been reduced due to miniaturization, and the processing of large-amplitude signals cannot benefit from the miniaturization, making it difficult to increase the speed. On the other hand, according to the present invention, since the frequency is reduced in the digital processing stage, even if the video signal becomes faster than the current one, the speed can be increased by miniaturizing the LSI.

In the display device driving system according to the present invention, in addition to the above configuration, the digital-to-analog conversion circuit uses a common reference voltage for all the digital video signals developed in a plurality of phases. And convert it to an analog signal.

With the above configuration, each digital video signal is converted into an analog signal using a plurality of digital-analog conversion circuits using a common reference voltage. With such a configuration of the digital-analog conversion circuit, in addition to the effect of the above-described configuration, it is possible to remarkably prevent the conversion variation of each conversion circuit from occurring, and to obtain a more uniform display.

Further, a display device according to the present invention is a projection type display device, wherein the display device is driven by the driving system.

The display device is a projection type (projector)
, The size of the device needs to be smaller than the screen size.

On the other hand, according to the configuration of the present invention,
A projected image is displayed using the above driving method. Therefore, the processing of the video signal can be simplified as compared with the related art. Therefore, the circuit scale can be made compact,
The device size, which is important for a projection display device, can be reduced.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

The display device driving system according to the present embodiment is used in a polysilicon TFT (thin film transistor) -LCD (liquid crystal display) panel or the like in a display device (image display device) for displaying an image. This is a drive system of a system in which an analog video signal is externally developed (divided) into a plurality of phases and supplied to a display device.

Hereinafter, description will be made using an example of a polysilicon TFT-LCD panel. FIG. 1 is a block diagram of a drive system of a display device according to the present embodiment, in which a circuit within a broken line is configured by a single LSI. As shown in FIG. 1, in this drive system, a data latch circuit 11, a sampling clock generation circuit 12, a sampling memory circuit 13, a hold memory circuit 14,
A conversion circuit (digital-analog conversion circuit) 15a, 1
5b (not shown), 15c (not shown), and 15d are provided. Further, buffer circuits 16a, 16b (not shown), 16c (not shown), and 16d are provided.

The data latch circuit 11 latches the input digital video signal DT with the clock signal CK and outputs it to the sampling memory circuit 13 as a data latch signal Di. The sampling clock generation circuit 12 generates the sampling clock signal SP by dividing the clock signal CK into a plurality of timings based on the control signal (enable signal) ENB, and also transfers the same from the control signal ENB and the clock signal CK. The signal HP is generated and output to the sampling memory circuit 13 and the hold memory circuit 14, respectively. The sampling memory circuit 13 develops the data latch signal Di, which has become data synchronized with the clock signal CK in the data latch circuit 11, into a plurality of phases by sampling at the timing indicated by the sampling clock signal SP. Ds is output. The hold memory circuit 14 captures the sampling memory signals Ds expanded into a plurality of phases by the sampling memory circuit 13 at the same timing indicated by the transfer signal HP, holds the captured data for a certain period of time, and generates a hold memory signal Dh. Output. The data latch circuit 11, the sampling clock generation circuit 12, the sampling memory circuit 13, and the hold memory circuit 14 constitute a developing unit.

The D / A conversion circuits 15a to 15d convert a digital video signal indicated by the hold memory signal Dh into an analog signal using a common reference voltage SV. The reference voltage SV is supplied from a reference voltage generation circuit (not shown), and has a cycle in which the polarity is inverted every horizontal period, for example, at the timing of the rising edge of the pulse of the transfer signal HP as described later. AC voltage. Buffer circuits 16a to 16d
Respectively, amplify the current of the analog video signal obtained by the D / A conversion circuits 15a to 15d, and output the analog output signal AP1 as a current having a value necessary to drive a pixel (LCD) panel such as a liquid crystal panel. , AP2 (not shown), AP3 (not shown), and AP4 are supplied to the LCD panel.

The control signal ENB is a signal for giving the timing of the start and end of the phase expansion of the video signal. The clock signal CK is a clock for latching a data signal and generating internal timing. The digital video signal DT is a generic term, and here are actually D0, D1, D2, and D3, and are input 4-bit digital video signals. The data latch signal Di is a generic term.
0i, D1i, D2i, and D3i, which are output signals of the data latch circuit 11. Sampling clock signal S
P is a generic name, and here, SP1, SP2, S
P3 and SP4, the sampling clock generation circuit 1
2 is a clock signal of the sampling memory circuit 13. SP1, SP2, SP3,
SP4 is for the first phase, the second phase, the third phase, and the fourth phase, respectively. The transfer signal HP is an output signal from the sampling clock generation circuit 12 and is a clock signal of the hold memory circuit 14.

The sampling memory signal Ds is a generic term. In this case, D0s1, D1s1, D2s1,.
D3s1 (above, the first phase), D0s2, D1s2, D2
s2, D3s2 (or more, second phase), D0s3, D1s
3, D2s3, D3s3 (above, the third phase), D0s4,
D1s4, D2s4, and D3s4 (hereafter, the fourth phase) are digital signals obtained by developing the digital video signal DT into a plurality of phases (here, four phases).

The hold memory signal Dh is a generic term,
Here, actually, D0h1, D1h1, D2h1, D3
h1 (above, the first phase), D0h2, D1h2, D2h
2, D3h2 (above, the second phase), D0h3, D1h3,
D2h3, D3h3 (above, the third phase), D0h4, D1
h4, D2h4, and D3h4 (the above is the fourth phase), and the timing is adjusted so that the timings of the sampling memory signals Ds of all the phases match.

FIG. 2 shows an example of the configuration of the sampling clock generation circuit 12. In the example shown in FIG. 1, the sampling clock generation circuit 12 includes D-type flip-flops FF1 to FF8, a NOR gate NOR1, a NAND gate
Gates NAND1 and NAND2, inverter INV
1 and INV2, the control signal ENB and the clock signal CK are input, the internal signals SS1 to SS5 are created, and the transfer signal HP and the sampling clock signals SP1 to SP4 are output. Internal signals SS1 to SS5, transfer signal H
P and sampling clock signals SP1 to SP4
Has a waveform as shown in FIG.

FIG. 4 shows an example of the configuration of a data signal line driving section. As shown in FIG.
1, data signal bus line 22, data signal line 2
3, a switch 24, and an output signal line 25 are formed.

The number of data signal bus lines 22 is four in this embodiment. For example, in the case of the XGA format, the number is 12 lines. The analog output signals AP1, AP2, AP3 output from the buffer circuits 16a to 16d (see FIG. 1) are connected to the data signal bus line 22.
AP4 is inputted respectively.

The number of data signal lines 23 is equal to the number of pixels driven in one horizontal period (for example, 1024 in the XGA format), and is equal to the number of data signal bus lines 22 (four in the present embodiment). And one set. In the figure, three sets (A, B,
Although only C) is illustrated, the data signal line 2 is actually
The number of pairs (for example, 1024/4 = 4) obtained by dividing the number of 2 (for example, 1024) by the number (here, 4) in one set
256 sets) exist.

The switch 24 is connected to each data signal line 23
Are formed one by one. The switch 24 turns on / off conduction between each data signal bus line 22 and the corresponding data signal line 23 based on a sampling pulse from the shift register 21.

The output signal line 25 is for sequentially transmitting the sampling pulse from the shift register 21 to the switch 24 in accordance with the clock signal SCK. A pulse is sent. Each output signal line 25 branches into the same number as the number of data signal lines 23 in this set (four in this case), and the switch 24 is formed at each branch destination. Therefore, when one output signal line 25 supplies a sampling pulse, all the switches 24 connected thereto (here, 4
), And all of the data signal lines 23 (shown as 1 to 4 in the drawing) of a certain set (for example, set A) corresponding to the switch 24 are electrically connected to the data signal bus line 22. It has become.

The shift register 21 receives the clock signal SC
According to the timing indicated by K or the like, first, from the output signal line 25, the data signal line 23 of the set A
The sampling pulse is supplied only to the switch 24 connected to (1 to 4 in the figure). As a result, of the data signal lines 23, only the data signal lines 23 belonging to one set A are turned on. By turning on the set A and turning off all other sets in this manner, the four data signal bus lines 22 are connected to the data signal lines 23 of the set A.
Only the analog video signals AP1 to AP4 are sent to the analog video signal.

At the next timing, a sampling pulse is supplied to only the set B, the set B is turned on, and the other sets are turned off, so that the data signal lines 23 of the set B are connected from the four data signal bus lines 22. Analog video signal AP1
To AP4. Hereinafter, the same operation is performed.

As a comparison, FIG. 5 shows a case where a plurality of data signal lines are driven one by one without being divided. The analog video signal is sequentially sent from the data signal bus line 32 to the data signal line 33 by sequentially turning on the switch 34 at each timing based on the clock signal SCK or the like by the shift register 31. In other words, from a different point of view, it can be said that the number of data signal lines in one set of data signal lines (therefore, the number of data signal bus lines) is one.

In this embodiment, for convenience of explanation, four data signal lines are set as one set as described with reference to FIG. 4, but more specifically, for example, in the XGA format, the data signal lines The number is 1024, the number of scanning signal lines is 768, and the dot clock frequency is 65 MHz. At this time, as shown in FIG. 6, 12 data signal bus lines (a to l) are prepared, and the 12 data signal lines are simultaneously operated as one set. In this case, 1024/12 = 8
5.33, there are 86 such sets. In FIG. 6, the upper part represents one horizontal period (1H), the horizontal axis represents time, and the vertical axis represents a voltage level, that is, a brightness level. A video signal is usually given a temporal change in brightness as a signal. In FIG. 6, the middle row is an enlarged view of one set of data signal bus lines in the upper row, and the lower row is each data signal bus line (a, b, c, k, l for convenience of explanation). Only the voltage value is illustrated).

In order to sample 1024 lines individually, the sampling time per line is extremely short, and it is difficult with the current capability of the polysilicon TFT.
Therefore, by sampling 12 lines at a time and sampling at the same timing, it is possible to take 12 times as long as in the case of one line at a time, so that sufficient sampling can be performed even if a polysilicon TFT is used. become. That is, the video signal supplied to the data signal bus line is
In the case of the XGA format, the number is 12. If driving is performed using one analog video signal as shown in FIG.
The time allocated per 1024 data signal lines is about 15.4 ns (= 1/65 MHz). On the other hand, when driven by 12 data signal bus lines, 1024 lines are divided into 86 groups, and the time available for one group is about 185 ns (= 15.4 × 12).

However, in order to perform such driving, it is necessary to prepare a video signal suitable for this driving method.
The video signals supplied to the two data signal bus lines need to be devised as in the present embodiment. That is, it is necessary to apply a video signal devised to maintain the display resolution in the original state of the XGA format to the data signal bus line. That is, originally, the video signal information to be transferred to each data signal line has a time of 15.4 ns in the original video signal, but it is necessary to create a new video signal holding this information for 185 ns. That's what it means. Then, the data signal bus line 1
Each of the two video signals is obtained by converting the original video signal to 15.4.
At a timing shifted by ns, information for a time of 15.4 ns is held for 185 ns. Here, in order to drive these 12 at the same timing,
The video signals of the 12 data signal bus lines have the same change timing.

Next, a detailed procedure for generating the data signal bus line signal from the input digital video signal will be described with reference to FIGS. 7 to 7 based on the drive system having the configuration shown in FIG. This will be described with reference to FIG. Note that, for convenience of explanation, here, the description will be made assuming that the video signal is expanded into a four-phase large-amplitude analog video signal. Therefore, the number of data signal bus lines is four (the number of data signal lines in one set is also four), and the number of sampling clock signals is four (SP1 to SP4). However, the number of phases is not limited to this.

As described above, here, it is assumed that the digital video signal DT is 4 bits (16 gradations). However, the number of bits is not limited to this.

FIG. 7 explains the operation of the data latch circuit 11 and the sampling clock generation circuit 12. The control signal ENB is a pulse signal having one horizontal period as one cycle. When the control signal ENB is low, it is turned on to generate the sampling clock signals (SP1, SP2,...) In the sampling clock generation circuit 12 (see FIG. 1). The sampling clock signal is enabled and turned off when the signal is high, indicating that the generation of the sampling clock signal is prohibited.
1,...) (Three in FIG. 7), that is, the number of data signal lines.

7 to 9, for convenience of description, it is assumed that three sets of data signal lines exist, and therefore, each sampling clock signal (for example, SP1) and the transfer signal HP are generated three times in one horizontal period. However,
Actually, for example, in the case of the XGA format,
As described above, since there are 86 data signal lines, each sampling clock signal and transfer signal HP
It occurs 86 times in one horizontal period.

The 4-bit digital video signal DT is shown in FIG.
, D0 (first bit), D1 (second bit), D2 (third bit), D3 (fourth bit)
It is. These are latched by the data latch circuit 11 in order to synchronize with the clock signal CK, and data latch signals D0i, D1i, D2i, and D3i having the rising edge of the clock signal CK as a change point are generated. The sampling clock generation circuit 12 uses the control signal ENB and the clock signal CK to extract the sampling clock signal SP necessary for developing the digital video signal DT into four phases.
1, SP2, SP3, SP4 and a transfer signal HP indicating the timing of data transfer to the hold memory circuit 14 are created.

That is, the control signal ENB is latched at the rising edge of the clock signal CK, and when the latched signal (control signal ENB) becomes L (low) level, creation of the sampling clock signal is started and H (high) ) End when the level is reached. Sampling clock signal SP
1 to SP4 are pulses each having a width corresponding to one cycle of the clock signal CK.
This is a signal having a timing shifted in phase by the period. The transfer signal HP is a clock signal supplied to the hold memory circuit 14, and is a signal between the sampling clock signal SP4, that is, the last sampling clock signal of a certain set of four, and SP1, that is, the first sampling clock signal of the next set. It is created to generate a pulse at the timing. Here, the phase of the transfer signal HP is delayed from SP4 by the high-level time of the clock signal CK, that is, the time corresponding to half of the pulse of each sampling clock signal.

FIG. 8 illustrates the operation of the sampling memory circuit 13. Inside the sampling memory circuit 13, there are four latch circuits (not shown) for latching 4-bit data, that is, the same number as the number of data signal bus lines, and these four latch circuits have the above data as common data. Latch signals D0i, D1i,
D2i and D3i are supplied, and the sampling clock signals SP1, SP2, SP4 and SP4 are supplied as clock signals for the respective latch circuits. Then, as output signals (sampling memory signals Ds) of these latch circuits, D0s1, D1s1, D2s1, and D3s1 (first
Phase), D0s2, D1s2, D2 captured by SP2
s2, D3 s2 (second phase), D0 captured by SP3
s3, D1s3, D2s3, D3s3 (third phase), SP
4, D0s4, D1s4, D2s4, D3
It is expanded into four sets of 4-bit data signals of s4 (fourth phase).

FIG. 9 illustrates the operation of the hold memory circuit 14. The hold memory circuit 14 captures the four sets of 4-bit data signals developed by the sampling memory circuit 13 as the latch timing of the rising edge of the transfer signal HP, and as the hold memory signal Dh, D0h1, D1h1, D2h1,.
D3h1 (first phase), D0h2, D1h2, D2h2,
D3h2 (second phase), D0h3, D1h3, D2h3,
D3h3 (third phase), D0h4, D1h4, D2h4,
As in D3h4 (fourth phase), a four-phase 4-bit data signal is output in all groups (phases) with the same data change timing.

FIGS. 10 and 11 show the D / A conversion circuit 1.
The operation of 5a to 15d will be described. That is, FIG. 10 shows that the transfer signals H generated by a plurality of reference voltages SV (see FIG. 1), that is, by the number of sets of data signal lines.
This indicates that the polarity is inverted at the timing of the rising edge of one of the P pulses (the rightmost one in the figure). FIG. 11 shows the hold memory signal Dh and the reference voltage S
The analog output signals AP1 to AP4 generated by the D / A conversion circuits 15a to 15d based on V
This shows that the polarity is inverted at the same time as the polarity inversion timing of the reference voltage SV, and the polarity is always the same as the reference voltage SV. The transfer signal HP is the same in FIG. 10 and FIG. 11, and is shown in FIG. 11 (a), FIG. 11 (b), FIG.
(C) and FIG. 11 (d) show the analog output signal A, respectively.
P1, AP2, AP3 and AP4 are shown. In FIGS. 10 and 11, a represents a potential serving as a reference of the reference voltage SV. Further, examples of the levels of the original digital signals (here, 0 to 15 because they are 4 bits) corresponding to the respective analog voltage values shown in FIGS. 10 and 11 are shown in parentheses. In FIG. 10, as the reference voltage SV, the reference voltage for the digital level 15 is shown by a solid line, the reference voltage for the digital level 0 is shown by a dashed line, and the other reference voltages (digital levels 1 to 1) are shown.
Illustration of 14) is omitted.

In the D / A conversion circuits 15a to 15d,
The D / A conversion circuits 15a to 15a-1 use the above-mentioned reference voltage SV which is a common digital-analog conversion reference voltage.
The 4-bit data signal (hold memory signal Dh) sent to each circuit of 5d is converted into an analog signal. Here, as the reference voltage signal, the voltage value is
By adopting what is changed according to AC drive,
A large-amplitude analog video signal can be obtained,
By using a common digital-analog conversion reference voltage, the deviation between the plurality of outputs (AP1 to AP4) can be kept extremely small.

Next, in order to obtain a current required for driving the LCD panel, the analog video signals obtained by the D / A conversion circuits 15a to 15d are respectively amplified by buffer circuits 16a to 16d. I do. The buffer circuits 16a to 16d are respectively connected to data signal bus lines of the LCD panel. Thus, the analog video signal amplified by the buffer circuits 16a to 16d is supplied to the LCD panel. That is, as described above, these analog output signals AP1 to AP4 are input to the data signal bus lines 22 shown in FIG. The data signals are output and supplied to the pixels of the LCD panel for each set.

As described above, a large-amplitude analog video signal reduced to a low frequency can be obtained from a conventional high-frequency digital video signal without creating a high-frequency large-amplitude analog video signal by intermediate processing.

Although the operation has been described here in terms of four-phase conversion of a 4-bit signal, the number of bits and the number of phases can be set arbitrarily in a form suitable for video display.

Further, the driving system of FIG. 1 is a block diagram of a circuit for performing signal processing for one color.
Red, green, and blue 3
When processing is performed on color, three circuit blocks in FIG. 1 may be used.

Next, a case where the present driving system is applied to a projection type display device (projector) will be described. FIG. 12 shows a configuration of such a projection type display device 61. The display device 61 includes a high-luminance metal halide lamp 62, total reflection mirrors M1 to M
3. UV filter 63, dichroic mirror DM
1 to DM4 and condenser lenses C1 to C3.
LCR, LCB, and LCG are liquid crystal display elements for red, blue, and green, respectively, and are respectively connected to the circuit blocks of FIG. 1 for the colors. Each of the liquid crystal display elements receives a data signal from a data signal line (not shown) and is controlled in transmittance, so that an image is projected on a screen 65 by a projection lens 64.

As described above, when the display device is of the projection type, the size of the device needs to be smaller than the screen size. On the other hand, according to the configuration of the present embodiment, by performing the projection image display using the above-described driving method, the processing of the video signal, in particular, the noise countermeasures can be simplified as compared with the related art. The size can be made compact, and the device size of the display device can be made compact while suppressing noise.

The driving system for a display device according to the present invention includes a plurality of data signal lines in a display device having display elements arranged in a matrix and displaying an image by controlling scanning signal lines and data signal lines. As one set, the same number of data signal bus lines for supplying data signals to be provided to the data signal lines are prepared as the number of the data signal lines, and a signal to be provided to the plurality of data signal bus lines is a video signal to be displayed. Is divided into a plurality of parts, and the signal frequency is lowered and the timing of the change point is aligned. The signal relationship between the data signal bus lines is the time allocated when the original video signal is driven one line at a time. The data signal lines of the same set are prepared at the same timing while maintaining the signal level of each set. This is related to a display device driving method in which the driving frequency of the data signal line is lowered by sequentially driving.A video signal given to the data signal bus line is an analog video with a large amplitude that can sufficiently control the liquid crystal transmittance. In a drive system in which a video signal is converted to a digital signal at least once in order to process the video signal, the signal is shifted to a plurality of phases at the time of the digital video signal as a phase shift of the signal, and a common reference voltage is applied. A configuration may be employed in which a plurality of digital-to-analog conversion circuits to be used are used to obtain an analog video signal whose phase is shifted.

In addition, the display device driving system according to the present invention, in the above configuration, comprises a polysilicon TFT-
It may be configured to use an LCD panel.

The display device according to the present invention may be configured to be of a projection type using the above-described driving method.

[0060]

As described above, the display device driving system according to the present invention comprises a developing means for developing the display video signal input as a digital video signal into a plurality of phases, and a developing means for developing the display video signal into a plurality of phases. A digital-analog conversion circuit for converting a digital video signal into an analog video signal is provided.

As a result, a signal for driving a display device can be generated without generating a high-frequency, large-amplitude analog video signal which is generated in a signal processing process by a conventional driving system and which is susceptible to noise and also a source of noise. As a result, it is possible to create a necessary analog video signal, and therefore, it is possible to simplify the measures against noise.

Further, since a high-frequency large-amplitude analog video signal is not created, power consumption can be reduced accordingly.

Further, since the system configuration can be realized with a single LSI, there is an effect that power loss due to signal transmission can be suppressed and power consumption can be further reduced.

Further, in the display device driving system according to the present invention, in addition to the above configuration, the digital-analog conversion circuit converts all the digital video signals developed in a plurality of phases to a common reference voltage. It is configured to be used to convert to an analog signal.

Thus, by adopting a configuration in which a common voltage is used as the conversion reference voltage of the plurality of digital-analog conversion circuits, in addition to the effect of the above-described configuration, the conversion variation of each conversion circuit occurs. Can be significantly prevented,
There is an effect that a more uniform display can be obtained.

The display device of the present invention is of a projection type, and is configured to be driven by the drive system.

As a result, a projected image is displayed using the above-mentioned driving method, and the processing of the video signal can be simplified as compared with the conventional method, so that the circuit scale can be made compact.
Therefore, it is important for projection display devices,
This has the effect of making the device size compact.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a display device drive system according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a sampling clock generation circuit.

FIG. 3 is a timing chart showing waveforms of an internal signal and an output signal of a sampling clock generation circuit.

FIG. 4 is a block diagram illustrating a configuration example of a data signal line driving unit.

FIG. 5 is a block diagram illustrating another configuration example of a data signal line driving unit.

FIG. 6 is an explanatory diagram showing a state of driving a data signal bus line and a signal waveform.

FIG. 7 is a timing chart showing the operation of the drive system according to the present invention and showing how a data latch signal is created.

FIG. 8 is a timing chart showing the operation of the drive system according to the present invention and showing how a sampling memory signal is created.

FIG. 9 is a timing chart showing the operation of the drive system according to the present invention and showing how a hold memory signal is created.

FIG. 10 is a timing chart showing an operation of the drive system according to the present invention and showing a signal waveform of a reference voltage for generating an analog output signal.

FIGS. 11A to 11D show the operation of the drive system according to the present invention and are timing charts showing signal waveforms of analog output signals.

FIG. 12 is an explanatory diagram illustrating a configuration example of a projection display device.

FIG. 13 is a block diagram showing a configuration example of a conventional display device driving system.

[Explanation of symbols]

Reference Signs List 11 data latch circuit (expansion means) 12 sampling clock creation circuit (expansion means) 13 sampling memory circuit (expansion means) 14 hold memory circuit (expansion means) 15a, 15d D / A conversion circuit (digital-analog conversion circuit) 16a 16d buffer circuit 21 shift register 22 data signal bus line 23 data signal line 24 switch 25 output signal line 31 shift register 32 data signal bus line 33 data signal line 34 switch 35 output signal line 61 display device 62 metal halide lamp 63 ultraviolet filter 64 projection Lens 65 Screen AP1, AP2, AP3, AP4 Analog output signal C1, C2, C3 Condenser lens CK Clock signal Dh Hold memory signal DM1, DM2, DM , DM4 dichroic mirror Ds sampling memory signal DT digital video signal ENB control signals FF1, FF2, FF3, FF4, FF5, FF6, F
F7, FF8 D-type flip-flop HP transfer signal INV1, INV2 Inverter LCB, LCG, LCR Liquid crystal display element M1, M2, M3 Total reflection mirror NAND1, NAND2 NAND gate NOR1 NOR gate SP Sampling clock signal SCK Clock signal SS1, SS2, SS3 , SS4, SS5 Internal signal SV Reference voltage

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) H04N 5/66 102 H04N 5/66 102B (72) Inventor ▲ Taka ▼ Fuji Yutaka Nagaikecho, Abeno-ku, Osaka-shi, Osaka No. 22-22 Sharp Corporation F-term (reference) 2H093 NA16 NA32 NA43 NC13 NC16 NC21 NC22 NC23 NC26 NC28 NC34 ND39 ND40 ND49 NG02 5C006 AA01 AA16 AA22 AF83 BB16 BC12 BC20 BF03 BF04 BF06 BF11 BF26 BF27 BF27 FA47 FA56 5C058 AA09 BA04 BA26 BA33 BB05 BB06 BB10 BB11 5C080 AA10 BB05 CC03 DD12 DD23 DD26 EE29 EE30 FF11 JJ02 JJ04 JJ06

Claims (3)

[Claims] 1. A display device comprising a display element arranged in a matrix and controlling a scanning signal line and a data signal line based on an input display video signal to display an image indicated by the display video signal. A plurality of data signal lines are set as one set, and the same number of data signal bus lines for supplying data signals to be provided to the data signal lines are prepared as the number of data signal lines in the set of data signal lines.
Expanding the display video signal into a plurality of phases, thereby lowering the signal frequency by the amount divided into a plurality, and aligning the change point timing of the signal level of each divided signal for all data signal bus lines, Providing an analog video signal, which holds the signal level for each time assigned when each data signal line is driven based on the display video signal for the time assigned to one set of the data signal lines, to the data signal bus line; In a display device drive system in which the same set of data signal lines are operated at the same timing and the data signal lines are sequentially driven for each set, the display video signal input as a digital video signal is developed into a plurality of phases. Expanding means for converting the digital video signal expanded into a plurality of phases into an analog video signal The drive system of the display device characterized by comprising an analog converter - digital converting. 2. The digital-to-analog conversion circuit according to claim 1, wherein all of the digital video signals developed into a plurality of phases are converted into analog signals by using a common reference voltage. Display device drive system. 3. A display device of a projection type, wherein the display device is driven by the drive system for a display device according to claim 1.