JP2001337142A - Semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing device for facilitating multichannel by reducing the number of output pins of a relay-control LSI in pin electronics. SOLUTION: A switch of a test signal for each channel in pin electronics is carried out, according to make/break control of the relay of a plurality of relays in this semiconductor testing apparatus. The semiconductor testing apparatus is provided with a relay control signal producing circuit giving data for controlling the relays in the respective channels, a switching circuit selectively switching the control data of the respective channels in the relay control signal producing circuit, a flip-flop writing and storing the channel control data selected by the switching circuit by a writing enable signal for performing the relay make/break control, and a writing control signal circuit producing the writing enable signal for the flip-flop.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor test apparatus for switching a test signal of each channel in pin electronics by making / break control of a plurality of relays.

[0002]

2. Description of the Related Art The configuration and operation of an example of the prior art will be described with reference to FIGS. First, the outline of the configuration of the semiconductor test apparatus will be described. As shown in FIG. 2, the configuration of the semiconductor test apparatus is a workstation 1
, A main frame 2, a test head 3, a performance board 80, and an IC socket 90.

[0003] The workstation 1 is an input / output means that serves as an interface between a semiconductor test apparatus and a person. The main frame 2 contains a power supply unit of the semiconductor test apparatus, a computer, a test signal generation unit, a logical comparator, and the like. The test head 3 incorporates a plurality of substrates of the pin electronics 10 corresponding to the number of test channels.
The performance board 80 is a pin electronics 1
The IC socket 90 connected to the electronic circuit No. 0 is mounted. The IC socket 90 is a socket for mounting a device under test.

Next, the outline of the operation of the semiconductor test apparatus will be described with reference to the block diagram of FIG. The pattern generator 5 generates logical data in synchronization with the basic clock signal output from the timing generator 4. In the waveform shaper 6, the logical data from the pattern generator,
A test pattern is generated with the clock signal from the timing generator 4. In the pin electronics 10, the test pattern is amplified to a desired voltage level by a driver and output to an input pin of the DUT 91. The output signal from the output pin of the DUT 91 is compared with a voltage by a comparator of the pin electronics 10 and output as a logic signal. In the logical comparator 7, at the timing of the strobe signal from the timing generator 4, the logical output signal of the DUT 91 and the expected value from the pattern generator 5 are logically compared to make a pass / fail judgment.

Next, the pin electronics 10 and the DU
The operation of the signal relationship with T91 will be described with reference to FIG. As shown in FIG. 4, in the pin electronics 10, a driver D11 that amplifies a test pattern from a waveform shaper (FC) to a desired voltage level and outputs the amplified voltage to a DUT 91, and a comparator C11 that compares an output signal from the DUT 91 with a voltage. Means make (O) by relay S12
N) / break (OFF). In addition, a universal DC test unit (U
DC) and the pin of the DUT 91 are made / breaked by the relay S11. Further, the terminating resistor R1 for terminating the signal from the output pin of the DUT 91 is connected to the relay S13.
Make / break.

Similarly, make / break of relays S21, S22, S23 is performed for each pin of DUT 91.
Here, the relay is, for example, a reed relay, and 30 to
Make / break control is performed by a drive current of 40 mA. Although the number of relays used for each channel in the pin electronics 10 corresponding to each pin of the DUT 91 is three, the number actually used is three to eight depending on the type of pin electronics.

Next, a control circuit of a relay of a conventional semiconductor test apparatus will be described with reference to FIG. As shown in FIG. 5, the relay control circuit includes a relay control unit 70, a relay control LSI 20, relay drivers Rd11, Rd
12, Rd21, Rd22, ..., Rdn1, Rdn
And 2. And relays S11, S12,
Make / break control is performed on S21, S22,..., Sn1 and Sn2. However, in the pin electronics 10 of FIG. 5, the number of relays to be controlled is two for each channel in order to simplify the drawing. Also,
The circuit element of the signal controlled by the relay is a driver D1
Only one is shown and the others are omitted.

The relay control section 70 supplies a control signal for controlling the relay in accordance with a program for testing the DUT 91 to the relay control LSI 20 in the form of a bus.

The relay control LSI 20 outputs a control signal corresponding to a relay for performing make / break control for each channel.

[0010] Relay drivers Rd11, Rd12, Rd
, Rdn1,..., Rdn1, Rdn2 are relays S11, S12, S21, S22,.
The make / break is performed by driving the respective electromagnetic coils of n1 and Sn2. Relays S11, S12, S21, S2
2,..., Sn1, Sn2 are of the electromagnetic type, so that an induced electromotive force is generated when a current flows through the electromagnetic coil, and the electromotive force damages the relay control LSI 20, so that the relay drivers Rd11, Rd12, Rd21, Rd22,
.., Rdn1 and Rdn2 are always required.

Here, the number of relays required for make / break control for each channel of the pin electronics 10 is six.
Assuming that the number of electronic circuits of the pin electronics 10 is 80, the number of control signals is 6 × 80 = 480. Accordingly, the output signal of the relay control LSI 20 increases due to the increase in the number of channels of the semiconductor test device. Therefore, the relay control LSI 20 also increases in response to the increase of the number of channels of the semiconductor test device and the number of control relays per channel. Must be pinned.

As a result, the package size of the relay control LSI 20 becomes large, the substrate of the pin electronics 10 becomes large, and the test head becomes large.

For example, when the relay control LSI 20 has a large number of pins, a BGA package can be used for downsizing. However, the pin electronics to be mounted must be a multi-layer board, and the cost increases drastically, which is not a practical method.

[0014]

As described above, in the conventional semiconductor test apparatus of the pin electronics relay control system, when the number of channels is increased, the relay control LS is required.
The number of output pins of I increases, the size of the package also increases, the test head increases, and there is a practical problem such as the cost increases sharply in the case of a BGA package. The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor test apparatus in which the number of output pins of a relay control LSI of pin electronics is reduced to facilitate multichannel operation.

[0015]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention provides a semiconductor test apparatus for switching a test signal of each channel in pin electronics by making / break control of a plurality of relays. A relay control signal generation circuit for providing data for controlling the relay of each channel, a switching circuit for switching and selecting control data of each channel of the relay control signal generation circuit, and writing control data for the channel selected by the switching circuit A semiconductor test comprising: a flip-flop for writing / holding by an enable signal to perform make / break control of the relay; and a write control signal generating circuit for generating a write enable signal for the flip-flop. The device is the gist.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. The main configuration and operation of the semiconductor test apparatus shown in FIG. 2 and FIG. 3 are the same as those in the related art and have been described in the related art, so that the description is omitted.

The pin electronics 1 shown in FIG.
The operation of the signal relation between 0 and the DUT 91 is also the same as the conventional operation, and the description is omitted.

The relay control circuit in the semiconductor test apparatus of the present invention will be described with reference to FIG. As shown in FIG. 1, the relay control circuit includes a relay control unit 70, a relay control LSI 30, and flip-flops FF11, FF12, FF21, FF2 instead of a relay driver.
, FFn1 and FFn2. Then, the relays S11, S12, S21, S22,.
-Make / break control of Sn1, Sn2.
However, in the pin electronics 10 of FIG. 1, the number of relays to be controlled is shown as two for each channel in order to simplify the drawing. Further, only the driver D11 is shown as a circuit element of a signal controlled by the relay.

The relay control unit 70 supplies a control signal for controlling a relay to the relay control LSI 30 in accordance with a program for testing the DUT 91.

The relay control LSI 30 includes a relay control signal generation circuit 41, 42,.
And a write control signal generation circuit 60.
The relay control signal generation circuit 41 outputs data D1A and D1B for controlling the relays S11 and S12 of the first channel to the switching circuit 50. The relay control signal generation circuit 42 outputs data D2A and D2B for controlling the relays S21 and S22 of the second channel to the switching circuit 50.
Similarly, the relay control signal generation circuit 4n includes data DnA and Dn for controlling the relays Sn1 and Sn2 of the n-th channel.
nB is output to the switching circuit 50.

The switching circuit 50 selects which channel of control data is to be output by a control signal from the relay control unit 70.

The write control signal generation circuit 60 generates a clock signal for writing data for controlling the relay into the flip-flop.

The flip-flops FF11, FF12, F
F21, FF22,... FFn1, FFn2 are relays S11, S12, S21, S22,.
1. The respective electromagnetic coils of Sn2 are driven to make (ON) / break (OFF), respectively.

For example, the first channel relay S11,
In the case of controlling S12, control data D1A and D1B are selected by the switching circuit 50, and the write enable signal WE1 is generated by the write control signal generation circuit 60.
Data is written into the flip-flops FF11 and FF12, and the relays S11 and S12 are made / breaked by the outputs Q1A and Q1B being high / low.

The relays S21 and S of the second channel
In the case of controlling the control signal 22, the control data D 2 A and D 2 B are selected by the switching circuit 50, the write enable signal WE 1 is generated by the write control signal generation circuit 60, the control data is written into the flip-flops FF 21 and FF 22, and the output Q 2 A , Q2B high / low makes and breaks relays S21 and S22. At this time, the relays S11 and S12 of the first channel are connected to the control data D1A and D1 of the flip-flops FF11 and FF12.
1B, the control data D1A, D1B
Is not rewritten.

Similarly, the relay Sn1 of the n-th channel,
Make / break control can also be performed on Sn2.

Therefore, since data of n channels can be shared by the switching circuit 50, the number of output pins of the relay control LSI 30 can be reduced. For example, if the number of relays required for make / break control for each channel of the pin electronics 10 is six,
If the electronic circuit of 0 is 80 channels, the switching circuit 50
Has six control data outputs, and the number of write enable signals of the write control signal generation circuit 60 is 80 channels.

On the other hand, the relay control unit 70 and the relay control LS
The signal between I30 is supplied in the same bus format as before. For example, when controlling 8 channels with the bus signal data as 8 bits, the 0th to 4th bits specify which relay is controlled, and the 5th to 7th bits specify which channel is controlled. The eighth bit is the relay control signal generation circuits 41 to 4n and the write control signal generation circuit 60
And make a choice. When further increasing the number of channels, it is necessary to add the number of control signals in order to increase the number of bits of the bus signal. However, since the conventional bus format is used, the number of control signals is the same as the conventional one. . That is, the number of signal lines between the relay control unit 70 and the relay control LSI 30 is the same as that of the related art and the present invention if the number of controlled channels is the same.

By the way, when testing the DUT 91 of the device under test, many channels are used, but the relay setting of each channel is often the same control. For example, as shown in FIG.
When testing the gates A1, A2, the AND gates A1,
Relays S12 and S2 for providing a signal to pin 4 of the input of A2
1, S31 and S41 perform the same make / break control. However, the relays S31 and S41 are not shown in FIG.

That is, if the make / break control of the relays of channels 1 to m is the same, channel 1
To the relay control LSI 30 from the relay control unit 70, the write control signal generation circuit 60 simultaneously outputs the write enable signals WE1 to WEm at the same timing, Relay control data DA and DB are simultaneously written into flip-flops FF1 to FFm, and relays S11 to Sm1 of channels 1 to m can be set at the same time. Therefore, in the semiconductor test apparatus of the present invention, the time for controlling the relay can be reduced, so that the test time for the device can be reduced.

Therefore, when the semiconductor test device is to be multi-channeled, the relay control LSI 30 can reduce the number of output signals. It is not necessary to increase the number of pins of the LSI 30.

When increasing the number of pins of the relay control LSI 30, it is not necessary to increase the package size.
This can be realized even if the substrate of the pin electronics 10 is small, and the test head does not become large.

[0034]

The present invention is embodied in the form described above and has the following effects. That is,
Since the switching control data of the relay is shared by the switching circuit, control of many channels can be realized by a relay control LSI having a small number of pins, and the size of the test head can be reduced. Also, if you set the same relay for each channel,
By controlling the write enable signal, there is an effect that the speed of the relay control can be increased.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a semiconductor test apparatus of the present invention.

FIG. 2 is an external view of a semiconductor test apparatus.

FIG. 3 is a main block diagram of the semiconductor test apparatus.

FIG. 4 is a main part circuit diagram of the semiconductor test apparatus.

FIG. 5 is a main part circuit diagram of a conventional semiconductor test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Workstation 2 Main frame 3 Test head 4 Timing generator 5 Pattern generator 6 Waveform shaper 7 Logic comparator 10 Pin electronics 20, 30 Relay control LSI 41, 42, ... 4n Relay control signal generation circuit 50 Switching circuit Reference Signs List 60 write control signal generation circuit 70 relay control section 80 performance board 90 IC socket 91 DUT

Claims (1)

[Claims] 1. A semiconductor test apparatus for switching a test signal of each channel in pin electronics by make / break control of a plurality of relays, a relay control signal generating circuit for providing data for controlling a relay of each channel, and the relay A switching circuit for switching and selecting control data of each channel of the control signal generating circuit; and a flip-flop for writing / holding the control data of the channel selected by the switching circuit with a write enable signal to perform make / break control of the relay. And a write control signal generation circuit for generating a write enable signal for the flip-flop.