JP2001337134A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, having a simple structure allowing an effective acceleration test. SOLUTION: This integrated circuit device is provided with burn-in signal terminals and signal terminals for general operation, such that the burn-in signal terminals are separated electrically from the signal terminals for the general operation. Since parasitic capacitance or the like to be added to the signal terminals will not be added to the signal terminals, the operation speed will not be reduced. Accordingly, a burn-in signal can be supplied using a simple connection jig, to effectively execute the acceleration test.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effective for use in an acceleration test technology of a multi-pin semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Investigations after the present invention has been carried out have revealed that Japanese Unexamined Patent Publication No. 9-8220 (hereinafter referred to as prior art 1) is considered to be related to the present invention described later. . In the publication of Prior Art 1, BG
A terminal for taking out a signal line between chips which cannot be seen from the outside is provided on the surface of the A type package. Extracting the signal lines between the chips to the outside in this way is for directly inputting or extracting signals to individual chips, and is not used at the time of burn-in as in the present invention.

[0003]

SUMMARY OF THE INVENTION BGA / LGA (Lan
In a semiconductor integrated circuit device having a (dGrid Arry) structure, a large number of signal electrodes are provided on the back surface at high density. In order to effectively find out initial defects of the semiconductor element at the time of the accelerated test (burn-in or aging), it is necessary to bring the internal circuit into operation in addition to the heat treatment. In order to make the internal circuit operate as described above, it is necessary to supply an input signal from the signal electrode. In this case, each of the signal electrodes such as the LGA is formed small and densely, and a burn-in connection jig for electrically connecting to the signal electrodes and supplying the input signal is expensive. There is a problem in that

An object of the present invention is to provide a semiconductor integrated circuit device which can realize an effective acceleration test with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. A signal terminal for burn-in and a signal terminal for normal operation are provided so as to be electrically separated.

[0006]

FIG. 1 is a block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 7A shows the surface portion, and FIG. 7B shows the cross-sectional portion. The inside of the surface portion of FIG.

The semiconductor integrated circuit device is not particularly limited, but (b) is electrically connected to two semiconductor chips consisting of an A chip and a B chip on bumps formed on the surface of the base as shown in the cross section. Is done. That is, the A chip and the B chip are overlapped so that their surfaces face the surface of the base, and are connected to the bumps. A plurality of capacitors for stabilizing a power supply and the like are provided in a peripheral portion of the semiconductor chip.

On the upper side of the base, the A chip and B
A cap is provided to cover a mounting surface on which the chip and the capacitor are mounted. This cap is made of epoxy (ep
(oxy) is bonded to the base. Electrodes electrically connected to the back surfaces of the A chip and the B chip are provided on the back surface of the cap, and a predetermined bias voltage is supplied to the substrates of the A and B chips.

As shown on the surface of FIG. 2A, the cap has a length substantially the same as that of the bait in the longitudinal direction of the semiconductor integrated circuit device (lateral direction in FIG. 1). In the short side (vertical direction in the figure) of the semiconductor integrated circuit device, it is formed shorter than the base. As a result, the base is provided with portions that are not covered by the cap at the top and bottom of the figure, and the burn-in pads are arranged there. That is, the burn-in pad can be electrically contacted on the surface of the semiconductor integrated circuit device.

FIG. 2 is a back view of one embodiment of the semiconductor integrated circuit device according to the present invention. On this back surface, a general signal LAND (terminal) is provided in a grid shape. These terminals include a power supply terminal for supplying a DC voltage such as a power supply voltage or a circuit ground potential, in addition to a signal terminal for circuit operation.

In the semiconductor integrated circuit device according to the present invention, as shown in FIGS. 1 and 2, a signal terminal and a burn-in signal terminal are provided respectively. Of these terminals, signal terminals for performing circuit operations are not directly electrically connected inside the semiconductor integrated circuit device. That is, during normal operation, a signal that changes to a high level / low level in accordance with the circuit operation is not transmitted to the burn-in terminal. This enables high-speed operation without connecting the large parasitic capacitance of the burn-in terminal to the parasitic capacitance of the signal input terminal.

However, since a power supply voltage for operation is supplied to the chip even at the time of burn-in, DC voltage terminals such as an operating voltage and a ground potential of a circuit are mutually connected via the power supply terminal of the chip. What is connected.
Therefore, the meaning that the signal terminal and the burn-in terminal are not electrically connected means that the signal terminals that change to a high level / low level in connection with the circuit operation are not connected to each other.

The burn-in terminal is a J
The number of interfaces corresponding to the TAG is smaller than the number of signal terminals provided on the rear surface.
Then, in order to facilitate the contact with the probe or the like, the size is formed larger than the signal terminal, and furthermore, it is provided in a line. In this way, a simple and inexpensive burn-in connection jig using a pogo pin or a probe needle having a spring property can be used, and burn-in can be performed on a plurality of semiconductor integrated circuit devices in parallel. Can be.

FIG. 3 is a layout view of one embodiment of a burn-in terminal of the semiconductor integrated circuit device according to the present invention. In this embodiment, 21 burn-in electrodes are provided along one side of the front side of the semiconductor integrated circuit device and another side parallel to the one side. That is, in one semiconductor integrated circuit device, a total of 42 burn-in electrodes are provided.

Of the 42 electrodes, the terminals connected to the JTAG interface provided on the A chip are HATCK and HA of the 10th to 6th pins.
TRST, HATDI, HATMS and HATDO. The terminals connected to the JTAG interface section provided on the B chip are the H pins of the 20th to 16th pins.
BTCK, HBTRST, HBTDI, HBTMS and HBTDO. The remaining terminals are burn-in DC power supply terminals.

FIG. 4 is a block diagram showing one embodiment of a semiconductor chip mounted on a semiconductor integrated circuit device according to the present invention. The A chip and the B chip are the same semiconductor chip on which circuit blocks as shown in FIG. In this embodiment, a DRAM (dynamic RA
M), an SRAM (static RAM), user logic (User Logic) for controlling the SRAM, a test circuit BIST, and the interface circuit JTAG.
Consists of The interface circuit JATG serially inputs and outputs the mode setting signal TMS, the test input data TDI, and the test output data TDO in synchronization with the clock terminal TCK.

A DRAM is, for example, 64K words × 288.
DRAM core having a large storage capacity such as 1 bit (about 18.4 Mbits), four registers having a storage capacity of 72 bits each for writing to the DRAM core, and storage of 72 bits each for reading. And four registers having a capacity. The SRAM has a role as a buffer register at the time of its input / output operation, and has four write ports each having 128 words × 72 bits.
And four read ports each having 128 words × 72 bits. The user logic includes an input / output interface unit that inputs and outputs data in units of 72 bits, a multiplexer that transmits data of 72 bits each between the SRAM and the DRAM, and the like.

The test circuit BIST serially supplies a test pattern to a latch circuit which is formed in a chain in the user logic unit to form a register, and supplies a user logic unit and a DRAM or SRAM.
Are transmitted in parallel.
Thus, the internal circuits of the DRAM, the SRAM, and the user logic are operated by the signal supplied from the test circuit BIST. As a result, DRAM and SRA
Since the input signal at the time of burn-in is supplied in a different system from the normal operation signal of M and the signal path for the normal operation and the signal path for the burn-in are not directly connected, the signal transmission speed during the normal operation is affected. The burn-in operation can be performed without any need.

FIG. 5 is a waveform diagram of the DRAM for explaining the operation at the time of burn-in. RAS-N is set to low level via the latch circuit, and a RAM activation signal is formed. This signal and the address terminals ADR, R
An internal operation is instructed by a command consisting of AS / and CAS /, and a word line selecting operation is performed. A signal of a bit line connected to the selected memory cell is amplified by an amplifying operation of a sense amplifier, and the memory cell is amplified. Is rewritten. Although not particularly limited, in the burn-in, an internal circuit is operated by such a row-related selection operation. A read signal of the selected memory cell is output from the output terminal. When performing a write operation, write data may be input to the latch DAT, and a write command may be input.

Also in the SRAM, an address is set in ADR, read and write operations are instructed by RE and WE, and data set in DAT is written in a selected memory cell in a write operation, and is selected in a read operation. Information stored in the memory cell is output to DAT. In the user logic unit, the input signal may be supplied to a latch that supplies the input signal to the latch. In this way, the burn-in can be performed by the test circuit BIST with the user logic, the DRAM, and the SRAM operating.

The functions and effects obtained from the above embodiment are as follows. (1) By providing the burn-in signal terminal and the signal terminal for normal operation separately, a parasitic capacitance or the like added to the signal terminal is not added to the signal terminal, so that the operation speed is reduced. Thus, the burn-in signal can be supplied by a simple connecting jig, and an effect of enabling an effective acceleration test can be obtained.

(2) In addition to the above, by providing the signal terminal for the normal operation on the back side and the signal terminal for the burn-in on the front side, it is possible to efficiently provide terminals corresponding to the respective functions. The effect that it can be obtained is obtained.

(3) In addition to the above, by making the contact area of the burn-in signal terminal larger than the contact area of the normal operation signal terminal, a simple and inexpensive burn-in connection jig is used for the burn-in connection jig. The effect of being able to supply signals and power is obtained.

(4) In addition to the above, by providing the burn-in signal terminals in a line at the periphery of the package surface, a simple and inexpensive method using a spring-like perov needle or pogo pin is provided. An effect that a signal and power for burn-in can be supplied by a simple burn-in connection jig is obtained.

(5) In addition to the above, the burn-in signal terminal is made to correspond to an interface corresponding to JTAG, and a test circuit for generating a test signal necessary for the operation of the internal circuit through the interface is provided, so that the burn-in is reduced. The advantage is that the internal operation for effectively performing the burn-in by utilizing the test operation can be realized while using the terminal for use.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, FIG.
In the above, the burn-in terminals may be provided along the four sides of the package surface. Semiconductor chips built into semiconductor integrated circuit devices are:
There is no need to provide a plurality of chips as described above, and a single chip may be mounted. The burn-in terminal may be adapted to supply an input signal according to its internal circuit, in addition to the terminal corresponding to the JTAG. The present invention can be widely used for semiconductor integrated circuit devices.

[0027]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. By providing the signal terminal for burn-in and the signal terminal for normal operation separately, no parasitic capacitance or the like added to the signal terminal is added to the signal terminal. The burn-in signal can be supplied by a simple connecting jig, and an effective acceleration test can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a back view showing one embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a layout diagram showing one embodiment of a burn-in terminal of the semiconductor integrated circuit device according to the present invention.

FIG. 4 is a block diagram showing one embodiment of a semiconductor chip mounted on the semiconductor integrated circuit device according to the present invention.

FIG. 5 is a waveform diagram of a DRAM for explaining an operation at the time of burn-in.

[Explanation of symbols]

DRAM: dynamic RAM, SRAM: static RAM, BIST: test circuit, JTAG: interface circuit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toru Kobayashi F-term (reference) 2G003 AA07 AC01 AH05 AH09 2G032 AA07 AB02 AD06 AD07 AK19 AK19, 6-16 Shinmachi, Ome-shi, Tokyo, within the Device Development Center, Hitachi, Ltd. 5L106 AA01 AA02 DD35 GG06

Claims (5)

[Claims] 1. A semiconductor integrated circuit device comprising: a burn-in signal terminal and a normal operation signal terminal, which are electrically separated from each other. 2. The semiconductor integrated circuit device according to claim 1, wherein the signal terminal for normal operation is provided on a back side, and the burn-in signal terminal is provided on a front side. 3. The semiconductor integrated circuit device according to claim 1, wherein a contact area of the burn-in signal terminal is larger than a contact area of the normal operation signal terminal. 4. The semiconductor integrated circuit device according to claim 2, wherein the burn-in signal terminals are provided in a line at a peripheral portion of the surface. 5. The burn-in signal terminal according to claim 1, wherein the signal terminal for burn-in corresponds to an interface corresponding to JTAG, and an operation of an internal circuit in response to an input signal input through the interface. A semiconductor integrated circuit device, further comprising a test circuit for generating a test signal required for the semiconductor integrated circuit.