JP2001326355A - Method for manufacturing semiconductor device, method for manufacturing active matrix substrate and electrooptical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device of a stable LDD structure in which the number of steps is simplified, and a misalignment of a gate electrode and the LDD structure is eliminated, and there is no fear of an age-based deterioration of characteristics; a method for manufacturing an active matrix substrate; and an electrooptical device. SOLUTION: The present invention comprises the steps of: forming a gate oxide film 4, a gating conductive film 202 and a resist film 203 on a polysilicon film 3; patterning the gating conductive film 202 by use of a mask 203a of this resist to form a masking conductive film 202a having the substantially same pattern as that of the mask 203a; introducing a high concentration impurity into a polysilicon film 3 by use of the mask 203a and the masking conductive film 202a; selectively removing both side parts of the masking conductive film 202a to form a smaller gate electrode than the pattern of the mask 203a; and removing the mask 203a to introduce a low concentration impurity into a polysilicon film 3 with the gate electrode as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a thin film transistor (TFT), a method for manufacturing an active matrix substrate, and an electro-optical device, and more particularly, to an LDD (Lightly Doped Dr.).
ain) A technique for forming a TFT having a structure.

[0002]

2. Description of the Related Art Conventionally, among various semiconductor devices, an active matrix substrate with a built-in drive circuit of an electro-optical device such as a liquid crystal display device, which is an active matrix display device, or an active matrix for a current drive control type display device. In a substrate or the like, a TFT is used as a pixel switching element or a switching element included in a driving circuit. Further, in order to improve the withstand voltage of the TFT or reduce the off-leak current in the active matrix substrate, a technique of forming the TFT with an LDD structure or an offset gate structure is often used.
Particularly, in a liquid crystal display device, a TFT which is an active element is used.
Since it is necessary to prevent the characteristics from deteriorating with time, an LDD structure in which the electric field concentration is prevented by making the gradient of the impurity concentration in the drain region gentle is used.

Next, a method of manufacturing an N-type TFT which is an example of the LDD structure will be described with reference to FIG. First, on the substrate 1011 shown in FIG.
As shown in FIG. 1, an underlying protective film (not shown), a silicon film 1
After 012 (semiconductor film) is sequentially formed, the silicon film 1012 is patterned into an island-shaped silicon film 1012 as shown in FIG. Next, as shown in FIG. 7D, the island-shaped silicon film 1012 and the substrate 1011 are formed.
After a gate insulating film 1013 is formed on the surface of the gate electrode 1013, a conductive film is formed on the surface of the gate insulating film 1013 facing the silicon film 1012, and is patterned to form a gate electrode 1013.
It is assumed to be 14. Next, as shown in FIG. 7E, low-concentration N-type impurities such as phosphorus (P) ions are introduced into the silicon film 1012 using the gate electrode 1014 as a mask.
As a result, the silicon film 1012 has the gate electrode 101
4 is a self-aligned low-concentration N-type region 1151.
Is formed. On the other hand, a portion of the silicon film 1012 where impurities are not introduced becomes a channel formation region 1017.

[0004] Next, as shown in FIG. 7 (f), after forming a resist mask 1055 that slightly widens the gate electrode 1014, as shown in FIG. A concentration of N-type impurity is introduced into the silicon film 1012. As a result, a part of the low-concentration N-type region 1151 except for a predetermined inner region is a high-concentration N-type region 1151.
It becomes 2. Next, as shown in FIG. 7H, after removing the resist mask 1055, an interlayer insulating film 1018 is formed on the surface side of the gate electrode 1014.
18, a contact hole 1019 reaching the high-concentration N-type region 1152 is formed, and the source electrode 1051 and the drain electrode 1 electrically connected to the high-concentration N-type region 1152 through the contact hole 1019 of the interlayer insulating film 1018.
052 is formed.

[0005] The TFT 1010 having the above-described structure has a structure in which the source electrode 105 of the source / drain region 1015 is formed.
1 and the drain electrode 1052 are electrically connected to each other to form a high-concentration N-type region 1152, and the gate electrode 1014
Has an LDD structure in which a portion opposed to the end of the gate insulating film 1013 via the gate insulating film 1013 is the low concentration region 1151. In order to manufacture an N-type TFT having an offset gate structure, the step of introducing a low-concentration N-type impurity shown in FIG. At this time, the TFT 1010 has an offset gate structure in which the portion corresponding to the low-concentration N-type region 1151 has the same impurity concentration as the channel forming region 1017. In order to manufacture a P-type TFT having an LDD structure or an offset gate structure, an impurity to be introduced is changed from an N-type impurity such as phosphorus (P) ion to a P-type impurity such as boron (B) ion. Can be manufactured in the same manner as the above-described N-type TFT.

[0006]

By the way, the aforementioned L
In the case of the TFT having the DD structure, in order to reduce the high electric field applied to the drain end and increase the reliability, the low-concentration region 1 having a high resistance is used.
The width of 151 needs to be stabilized. Further, in order to reduce the manufacturing cost, it is necessary to simplify the process as much as possible. In particular, the formation of the low concentration region 1151 and the high concentration region 1
If the formation of the gate electrode 152 and the patterning of the gate electrode 1014 can be simplified, it is possible to greatly reduce the manufacturing cost. However, a conventional LDD structure TFT1
In the manufacturing method of No. 010, since the distance between the end of the resist mask 1055 and the end of the gate electrode 1014 defines the LDD length or the offset length, the formation position of the resist mask 1055 is slightly different from the gate electrode 1014 in the surface direction. In this case, there is a problem that the deviation directly causes variation in the LDD length or the offset length.

Therefore, various studies have been made on how to manufacture a TFT without varying the LDD length and offset length. However, in general, P-type TFTs are often formed together with the N-type TFTs 1010 on the same substrate, and forming these TFTs of different conductivity types requires a considerably large number of steps. Therefore, even if the purpose is to suppress variations in LDD length and offset length, it is not preferable to further complicate the manufacturing process. Further, in addition to a TFT, a capacitor may be formed over the same substrate. In general, this capacitor element uses a semiconductor region formed simultaneously with the source / drain region of the TFT as one electrode,
It is obtained by a method in which the other electrode is formed simultaneously with the gate electrode of the TFT. However, this method has a restriction that an impurity must be introduced into a semiconductor film located below the gate electrode before the gate electrode is formed. It has been extremely difficult to suppress variations in LDD length and offset length without complicating the structure.

Therefore, in a method of manufacturing a semiconductor device in which TFTs of different conductivity types are formed on the same substrate, or in a method of manufacturing a semiconductor device in which a capacitance element is formed on the same substrate together with these TFTs, At present, it is not possible to sufficiently suppress variations in LDD length and offset length. In order to break this situation,
In the above-described conventional method of manufacturing an N-type TFT having an LDD structure, the following method has been studied. First, FIG.
A conductive film is formed on the surface of the gate insulating film 1013 shown in FIG.
A resist mask is formed over the surface of the conductive film, and the conductive film is patterned using the resist mask to form a gate electrode 1014 having a width smaller than the width of the resist mask. Next, the resist mask and the gate electrode 101
4 is used as a mask to introduce high-concentration N-type impurities such as phosphorus (P) ions into the silicon film 1012. Next, the resist mask is removed, and the remaining gate electrode 1014 is removed.
Low concentration of N such as phosphorus (P) ion
A type impurity is introduced into the silicon film 1012.

Although this method has a feature that an N-type TFT having no variation in LDD length can be obtained because there is no possibility that the resist mask is displaced with respect to the gate electrode 1014, the characteristic of the TFT is obtained. Deteriorates and the relaxation of the high electric field becomes insufficient, and as a result,
A new problem arises in that the junction between the low-concentration N-type region 1151 and the high-concentration N-type region 1152 is broken and a leakage current occurs. This problem is particularly serious when the impurity concentration at the time of introduction is as high as about 3 × 10 ¹⁵ cm ⁻² or more. The reason is that when a high concentration impurity is introduced into the silicon film 1012, the impurity concentration becomes 3 × 10
^At a high concentration of about ¹⁵ cm ^-2 or more, the edge of the resist mask becomes thin and the thickness becomes thin. Therefore, this high concentration impurity penetrates through the edge of the resist mask to form a low-concentration N-type region. This is because the low concentration N-type region 1151 is made into a high concentration N-type region.

If the low-concentration N-type region 1151 becomes a high-concentration N-type region, a good LDD structure cannot be obtained because the originally required low-concentration N-type region is lacking. The characteristics of the TFT thus obtained also become insufficient. The polysilicon (p-Si) forming the low-concentration N-type region 1151 and the high-concentration N-type region 1152 is
If ions are excessively implanted, it becomes amorphous (amorphized), so that the amount of ions implanted into the high-concentration N-type region 1152 is limited. Therefore, the low concentration N-type region 11
If the region 51 is formed as a high-concentration N-type region, the gradient of the impurity concentration in the drain region becomes steep, and it becomes difficult to prevent electric field concentration.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to simplify the number of steps in forming a TFT having an LDD structure on a substrate by reducing the number of masks used in a manufacturing process. And the TFT L
Variations in the DD length can be suppressed, the displacement between the gate electrode and the LDD structure can be eliminated, and defects due to remaining patterns can be reduced in the wiring region and the like, and as a result, there is no possibility that the characteristics will deteriorate over time. Stable LDD
It is an object to provide a method for manufacturing a semiconductor device having a structure, a method for manufacturing an active matrix substrate, and an electro-optical device using the active matrix substrate.

[0012]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a thin film transistor on a substrate; forming a gate insulating film and a gate electrode on a surface of the semiconductor film forming the thin film transistor; A multilayer film forming step of sequentially forming a conductive film and an organic thin film for a mask, and patterning the conductive film for forming a gate electrode using the organic thin film for a mask as a mask, the same size as the pattern of the organic thin film for a mask. A mask conductive film forming step of forming a mask conductive film; a high-concentration impurity introducing step of introducing a high-concentration impurity into the semiconductor film using the mask organic thin film and the mask conductive film as a mask;
A gate electrode forming step of selectively removing both side portions of the mask conductive film and forming a gate electrode of the thin film transistor smaller than the pattern of the mask organic thin film; and removing the mask organic thin film and masking the gate electrode. And introducing a low-concentration impurity into the semiconductor film.

This method of manufacturing a semiconductor device is a method for manufacturing a TFT having an LDD structure. In a multilayer film forming step, a gate insulating film, a conductive film for forming a gate electrode and an organic thin film for a mask are formed on the surface of a semiconductor film. The gate electrode forming conductive film is patterned using the mask organic thin film as a mask in a mask conductive film forming step to form a mask conductive film having the same size as the mask organic thin film pattern. I do. When patterning the conductive film for forming a gate electrode, anisotropic dry etching, for example, reactive ion etching (RIE) is used, and the width of the pattern of the organic thin film for mask is set to the gate length and the width of both sides of the LDD structure. If the width is made to match the width of the low-concentration region, the pattern of the obtained mask conductive film becomes the same as the mask organic thin film in both the width direction and the length direction. Therefore, in the high-concentration impurity introduction step, when a high-concentration impurity is introduced into the semiconductor film using the mask organic thin film and the mask conductive film as a mask, the semiconductor film is self-aligned with respect to the mask conductive film. Impurities are introduced
A source region and a drain region are formed in the semiconductor film.

Here, a region of the semiconductor film into which a high concentration impurity is not introduced is a region of the same size as the organic thin film for mask, that is, the conductive film for mask. The width is the sum of the gate length and the width of the low concentration region on both sides of the LDD structure. Therefore, in the semiconductor film, the region covered with the mask conductive film is composed of the channel formation region and the high electric field relaxation region formed on both sides of the channel formation region and doped with a low concentration impurity. Area. Since the dimensions in the width direction and the length direction of this region are always equal to the dimensions in the width direction and the length direction of the organic thin film for a mask used for patterning the conductive film for the mask, the displacement of the mask causes the displacement. LDD
The length does not vary.

Next, in a gate electrode forming step, both sides of the mask conductive film are selectively removed, a gate electrode of the thin film transistor smaller than the pattern of the mask organic thin film is formed, and further, the mask organic thin film is removed. And
Since the low-concentration impurity introduction step of introducing a low-concentration impurity into the semiconductor film using the gate electrode as a mask is performed, the semiconductor film can be formed without newly forming a mask by using the thin-film transistor gate electrode as a mask. In the film, a low-concentration region serving as a high-field relaxation layer and a high-concentration region serving as source and drain regions can be formed clearly with a small number of steps. In addition, it is possible to prevent a defect from occurring in the wiring region due to the remaining pattern.

In the conventional manufacturing method, when the mask organic thin film is used twice for patterning and impurity introduction, the peripheral portion of the film is deteriorated and sagged. In the manufacturing method of the present invention, the organic thin film for a mask is used as a mask in the high-concentration impurity introduction step. Using a mask conductive film of the same size as the pattern of
By using a gate electrode obtained by selectively removing both sides of the mask conductive film as a mask for the low-concentration impurity introduction step, patterning of the gate electrode, high-concentration impurity introduction, and low-concentration impurity introduction can be performed with one mask. Each step can be performed, and the steps can be simplified. Accordingly, there is no possibility that a characteristic defect or the like due to a position shift or the like occurring at the time of mask alignment occurs, and a low-concentration region can be formed in a self-aligned manner.

Further, there is no possibility that impurities introduced into the high concentration region are introduced into the low concentration region, and the impurity concentration in the low concentration region does not increase. Therefore, the distinction between the high-concentration region and the low-concentration region becomes clear, and a stable LDD structure can be obtained in which deterioration over time caused by an increase in the impurity concentration in the low-concentration region can be avoided. In addition, since a mask conductive film and a gate electrode that are more resistant than the mask organic thin film are used as a mask for the impurity introduction step, both the gate length and the width of the low-concentration region on both sides of the LDD structure are made uniform, The LDD structure has a shape controlled with high precision. As a result, it is possible to arbitrarily set the energy and dose of the impurity at the time of introduction in accordance with a desired product.

In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the selective removal of both sides of the conductive film for a mask is performed by a wet etching method. In the wet etching method, it is possible to adjust the lateral etching amount on both sides of the mask conductive film by adjusting the etching time. Thereby, the width of the gate electrode obtained by etching both sides of the mask conductive film can be adjusted with high precision, and a gate electrode with a uniform gate length can be obtained.

In the method of manufacturing a semiconductor device according to the present invention, in the high-concentration impurity introducing step, an impurity is introduced into the semiconductor film at a dose of 1 × 10 ¹⁵ cm ⁻² or more. , The semiconductor film is
It may be introduced at a dose of less than × 10 ¹⁵ cm ⁻² . In the method for manufacturing a semiconductor device according to the present invention, the thin film transistor is an N-type or P-type thin film transistor.

A method for manufacturing an active matrix substrate according to the present invention uses the method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the thin film transistor for pixel switching and the thin film transistor for a driving circuit, comprising the thin film transistor, The thin film transistor and a thin film transistor for a driving circuit including a thin film transistor of a different conductivity type are formed over the same substrate.

In this case, a pixel switching thin film transistor and a drive circuit thin film transistor formed of an N type thin film transistor and a drive circuit thin film transistor formed of a P type thin film transistor are formed on the same substrate. Further, a pixel switching thin film transistor and a drive circuit thin film transistor including a P-type thin film transistor and a drive circuit thin film transistor including an N-type thin film transistor may be formed over the same substrate.

An electro-optical device according to the present invention is characterized in that an electro-optical material is sandwiched between an active matrix substrate manufactured by the method of manufacturing an active matrix substrate according to claim 5 and a counter substrate. The electro-optical material may be a liquid crystal, and the electro-optical device may be a liquid crystal display.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention,
An embodiment of a method for manufacturing an active matrix substrate and an electro-optical device will be described with reference to the drawings. FIG.
1 is a sectional view showing a semiconductor device obtained by a method for manufacturing a semiconductor device according to an embodiment of the present invention. 2 and 3 are process diagrams showing a method for manufacturing the semiconductor device. The semiconductor device shown here is an N-type pixel switching TFT having an LDD structure used in an electro-optical device described later.
FT for N-type drive circuit having LDD structure
T and T for P-type drive circuit having self-aligned structure
Together with the FT, a drive circuit built-in type active matrix substrate is configured.

In FIG. 1, a base oxide film (base insulating film) made of silicon oxide (SiO ₂ ) or the like is formed on a glass substrate 1.
2. An island-shaped polysilicon film (semiconductor film) 3 constituting an N-type pixel TFT is sequentially formed, and a gate oxide film (gate insulating film) made of SiO ₂ is formed on the surface of the polysilicon film 3.
Chromium (Cr), aluminum (Al), and the like are formed on the surface of the gate oxide film 4 facing the polysilicon film 3.
A gate electrode 5 made of a metal such as tantalum (Ta) is formed. The glass substrate 1 may be a substrate having an insulating property and an excellent flatness, and may be replaced with, for example, a quartz substrate. The underlying oxide film 2 is made of silicon oxide (Si
O ₂ ), silicon oxide / silicon nitride (SiO ₂ / Si ₃ N ₄ )
Can be replaced with an insulating film composed of a two-layer film or the like.
The polysilicon film 3 has source / drain regions 11 and 12
And a channel forming region 13 for forming a channel between the source / drain regions 11 and 12.

In the source / drain regions 11 and 12, the portions to which the source / drain electrodes 6 and 7 described later are electrically connected are the high-concentration N-type regions 111 and 121, and a gate oxide film is formed at the end of the gate electrode 5. The portions opposed to each other via 4 are the low-concentration N-type regions 112 and 122. Then, the high-concentration N-type regions 111 and 121 and the low-concentration N-type regions 112 and 122
And the channel forming region 13 constitute an N-type pixel TFT 10 having an LDD structure. In the source / drain regions 11 and 12, the high-concentration N-type region 11
The impurity concentration of 1 and 121 is about 1 × 10 ²⁰ cm ⁻³ , and the impurity concentration of low-concentration N-type regions 112 and 122 is about 1 × 10 ¹⁸ c.
m ^-3 . Therefore, in the TFT 10, since the electric field intensity at the drain end is reduced by the low-concentration N-type regions 112 and 122, the off-leak current is significantly reduced. Further, since the TFT 10 has an LDD structure, compared with a TFT having a self-aligned structure,
The withstand voltage between the source and the drain can be increased, and the channel length can be shortened.

The channel forming region 13 is a portion of the polysilicon film 3 where no impurity is introduced. For example, when the channel is doped with low-concentration boron (B) ions, the impurity concentration is about 1 × 10 ¹⁶ cm
^-3 to 1 × 10 ¹⁷ cm ⁻³ , etc. For example, by performing such channel doping on an active matrix substrate with a built-in drive circuit, the threshold voltages of the N-type drive circuit TFT and the P-type drive circuit TFT can be set to predetermined values. In general, the hole mobility μ _h is smaller than the electron mobility μ _e , so that the ON current of the P-type driving circuit TFT is significantly smaller than the ON current of the N-type driving circuit TFT. Although there is a tendency, the difference in the magnitude of this on-current is caused by adjusting the threshold voltage by channel doping.
Almost can be solved. As a result, in the active matrix substrate with a built-in drive circuit, the on-current between the N-type drive circuit TFT and the P-type drive circuit TFT constituting the complementary transistor circuit is well balanced.

A lower interlayer insulating film 21 is formed on the surface of the gate electrode 5.
Contact holes 22 and 23 reaching the high-concentration N-type regions 111 and 121 are formed, and the high-concentration N-type region 1 is formed through the contact holes 22 and 23 of the lower interlayer insulating film 21.
Source / drain electrodes 6 and 7 electrically connected to 11 and 121 are formed. Source / drain electrodes 6, 7
An upper interlayer insulating film 24 is formed on the surface side of the lower interlayer insulating film 21, and the source interlayer
A contact hole 25 reaching the drain electrode 7 is formed, and a pixel electrode 8 electrically connected to the source / drain electrode 7 via the contact hole 25 in the upper interlayer insulating film 24 is formed.

Next, a method of manufacturing a semiconductor device according to the present embodiment will be described using an N-type pixel switching TFT having an LDD structure as an example. First, as shown in FIG. 2A, a base oxide film 2 is formed on the surface of a glass substrate 1 using a chemical vapor reaction method (CVD method) or the like (base insulating film forming step). Here, the base oxide film 2 is made of SiO ₂ 1
In the case of a layer, a film is formed by depositing SiO ₂ using a plasma CVD method (microwave plasma CVD method, optical CVD method, or the like) or a normal CVD method. When the underlying oxide film 2 is composed of two layers of SiO ₂ / Si ₃ N ₄ ,
i ₃ N ₄ is deposited and plasma CVD or normal CV
A film is formed by depositing SiO ₂ using the D method or the like and depositing Si ₃ N ₄ using the plasma CVD method or the like.

Next, an amorphous silicon film (amorphous silicon film) is formed on the underlying oxide film 2 by using a plasma CVD method or the like.
con), the crystal grains of the amorphous silicon film are grown by a laser annealing method or a rapid heating method to form a polysilicon film (polysilicon) 201,
The polysilicon film 201 is patterned by using a photolithography method, and the polysilicon film is left in a region where the N-type pixel TFT 10 is formed, thereby forming an island-shaped polysilicon film 3. Note that the polysilicon film 201 may be formed directly on the underlying oxide film 2 using a low pressure CVD method or the like.

Next, the TEOS-CVD method and the plasma C
A gate oxide film 4 made of SiO ₂ having a thickness of about 30 nm to about 200 nm is formed on the surface of the polysilicon film 3 by using a VD method, a thermal oxidation method, or the like. When the gate oxide film 4 is formed using the thermal oxidation method, the polysilicon film 3 can be formed by simultaneously crystallization of the amorphous silicon film. When channel doping is performed on the channel forming region of the polysilicon film 3, for example, boron (B) ions are implanted at this timing at a dose of about 5 × 10 ¹¹ cm ^{−2 to} 5 × 10 ¹² cm ⁻² . As a result, the silicon film 3 has an impurity concentration of about 1 × 10 ¹⁰ cm ⁻³ to 1 ×.
A low-concentration P-type silicon film of 10 ¹⁷ cm ⁻³ is obtained.

Next, as shown in FIG. 2B, a thickness of about 200 nm to about 600 nm is formed on the surface of the gate oxide film 4.
A gate electrode forming conductive film 202 made of a metal film of Ta, Cr, Al or the like is formed, and a resist film (organic thin film for mask) 203 is formed on the surface of the gate electrode forming conductive film 202.
Is formed (a multilayer film forming step). Next, as shown in FIG. 2 (c), the resist film 2 is formed using a normal fine processing technique.
03 is patterned to form a resist mask 203a. The width of the resist mask 203a has a width L ₁ of the low concentration N-type region 122 of one side of the LDD structure, a gate length L ₂ of the channel formation region 13, a low concentration of the other side of the LDD structure N The width L is the sum of the width L ₃ of the mold region 112.

Next, as shown in FIG. 2D, the conductive film 202 for forming a gate electrode is patterned by anisotropic dry etching, for example, reactive ion etching (RIE) using the resist mask 203a. ,
A conductive film for mask 202a having the same size as the resist pattern of the resist mask 203a is formed (mask conductive film forming step). Next, phosphorus (P) ions (N) are added to the polysilicon film 3 by ion doping using the resist mask 203a and the mask conductive film 202a as a mask.
Is ion-implanted at 30 to 80 keV with a dose (high concentration) of 1 to 5 × 10 ¹⁵ cm ⁻² (high concentration impurity introduction step). As a result, high-concentration N-type regions 111 and 121 having an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ are formed in the polysilicon film 3 in a self-aligned manner with respect to the mask conductive film 202a.

The region of the polysilicon film 3 which is covered with the mask conductive film 202a is not ion-implanted, and thus becomes a non-doped region 204. The non-doped region 204, the resist pattern of the resist mask 203a, i.e. from a conductive film 202a same size and mask, the width of the non-doped region 204 has a width L ₁ of the low concentration N-type region 122, a channel formation The width L is the sum of the gate length L ₂ of the region 13 and the width L ₃ of the low-concentration N-type region 112. Therefore, this non-doped region 204
Are the channel forming region 13 and the channel forming region 1
3 is a region in which the low-concentration N-type regions 112 and 122 formed on both sides of the substrate 3 are combined. The dimensions of the non-doped region 204 in the width direction and the length direction are determined by the mask conductive film 202a.
Are always equal to the dimensions in the width direction and the length direction of the resist mask 203a used for patterning.

When the gate electrode forming conductive film 202 is etched using the resist mask 203a,
As shown in (a), the end of the resist mask 203a is sagged with a width of about 1 μm to have a trapezoidal cross section or a squashed cross section. Conventionally, high-concentration ions are implanted into the polysilicon film 3 using only the resist mask 203a whose end is sagged. Therefore, phosphorus (P) ions are injected into the polysilicon film 3 below the end of the resist mask 203a. The low concentration N-type regions 112 and 122 may be implanted into the regions that should become low concentration N-type regions 112 and 122, and the low concentration N-type regions 112 and 122 may become high concentration N-type regions. In the embodiment, the resist mask 20
Since high-concentration ion implantation is performed on the polysilicon film 3 using the mask 3a and the mask conductive film 202a as a mask, there is no possibility that phosphorus (P) ions are implanted into the low-concentration N-type regions 112 and 122. As a result, In addition, there is no possibility that the low-concentration N-type regions 112 and 122 become high-concentration N-type regions.

Next, as shown in FIG. 3A, the mask conductive film 202a is formed by wet etching using a resist mask 203a so that the mask conductive film 202a has a desired gate length L ₂ , that is, a width required as a gate electrode. Both sides of the mask conductive film 202a are over-etched to form the gate electrode 5 (gate electrode forming step). At this time, since the mask conductive film 202a is isotropically overetching is done laterally, width or the gate length L ₂ of the obtained gate electrode 5 is narrower than the width L of the resist pattern of the resist mask 203a Becomes Therefore, it is possible to form the gate electrode 5 of the TFT having a narrow gate length L ₂ from the width L. After forming the gate electrode 5, the resist mask 203a is removed.

Next, as shown in FIG. 3B, using the gate electrode 5 as a self-alignment mask, 30 (P) ions (N-type) are added to the non-doped region 204 of the polysilicon film 3.
Ion implantation is performed at a dose of 1 to 5 × 10 ¹³ cm ⁻² (low concentration) at 80 keV (low concentration impurity introduction step). As a result, the impurity concentration is approximately 1 × 1
The low-concentration N-type regions 112 and 122 of 0 ¹⁸ cm ^-3 are formed in a self-aligned manner with respect to the gate electrode 5. At this time, ions are also implanted into the high-concentration N-type regions 111 and 121 at the above dose (low concentration), but the impurity concentration of the high-concentration N-type regions 111 and 121 is low. Since the impurity concentration of the high-concentration N-type regions 111 and 121 is hardly affected, since the impurity concentration of the high-concentration N-type regions 111 and 121 is higher by two digits or more than that of the impurity concentrations of 112 and 122. Further, since ion implantation is not performed in a region of the non-doped region 204 overlapping with the gate electrode 5, the low-concentration N-type region 11
A channel forming region 13 is formed in the non-doped region between the regions 2 and 122.

Next, as shown in FIG.
A lower interlayer insulating film 21 is formed on the surface side of the substrate, and contact holes 22 and 23 reaching the high-concentration N-type regions 111 and 121 are formed in the lower interlayer insulating film 21. Next, the contact holes 22 and 23 are filled with a conductive material,
The drain electrodes 6 and 7 are formed. Next, an upper interlayer insulating film 24 is formed on the surface of the lower interlayer insulating film 21, a contact hole 25 reaching the drain electrode 7 is formed in the upper interlayer insulating film 24, and a contact hole 25 is formed on the surface of the upper interlayer insulating film 24. The pixel electrode 8 electrically connected to the source / drain electrode 7 via the contact hole 25 is formed.

As described above, in the method of manufacturing a semiconductor device according to the present embodiment, phosphorus (P) ions are ion-implanted into the polysilicon film 3 using the resist mask 203a and the mask conductive film 202a as a mask, and then the mask Since both sides of the conductive film 202a are over-etched to form the gate electrode 5, the resist mask 203a is removed, and phosphorus (P) ions are ion-implanted into the polysilicon film 3 using the gate electrode 5 as a mask. Membrane 3
In this case, the high-concentration N-type regions 111 and 121 are formed in a self-aligned manner with respect to the mask conductive film 202a, and the low-concentration N-type regions 112 and 122 have a lower impurity concentration than the high-concentration N-type regions 111 and 121. Are formed in a self-aligned manner with respect to gate electrode 5.

[0039] Here, the width L ₃ of the width L ₁ and the low concentration N-type region 112 of the low-concentration N-type region 122 is masked conductive film 2
Is always constant equal to half the difference between the width L ₂ of the width L and the gate electrode 5 of 02a. Therefore, L in the manufacturing process
The variation in the DD length becomes extremely small, and the variation in the LDD length caused by the positional displacement of the mask, which has been conventionally regarded as a problem, can be suppressed. As described above, the photolithography conventionally required when forming the low-concentration N-type regions 112 and 122 becomes unnecessary, and there is no possibility that a characteristic defect or the like due to a positional shift or the like that occurs at the time of mask alignment occurs. A low-concentration region can be formed in an efficient manner.

Further, phosphorus (P) ions are implanted into the polysilicon film 3 using the resist mask 203a and the mask conductive film 202a as masks, and phosphorus (P) ions are implanted into the polysilicon film 3 using the gate electrode 5 as a mask. Is implanted, there is no possibility that impurities introduced into the high-concentration N-type regions 111 and 121 will be introduced into the low-concentration N-type regions 112 and 122, and the low-concentration N-type regions 112 and 122 will not be introduced.
Does not increase the impurity concentration. Therefore, the low-concentration N-type regions 112 and 122 are
11 and 121 can be clearly divided, a stable LDD structure can be obtained, and the reliability can be improved. As a result, the low-concentration N-type regions 112 and 1
22 can be prevented from deteriorating with time due to the increased impurity concentration.

As a mask for the impurity introduction step,
Conductive film 202a for a mask that is more resistant than a resist
And so using the gate electrode 5, the gate length L _2, the width L ₁ of the low concentration N-type region 122, the width L ₃ of the low-concentration N-type region 112
Can be made uniform, and the LDD structure can have a shape controlled with high precision. As a result, the energy and dose of the impurity at the time of introduction can be arbitrarily set in accordance with a desired product.

In the low concentration impurity introducing step,
In order to implant phosphorus (P) ions into the silicon film 3 using the gate electrode 5 as a mask, low-dose phosphorus (P) ions are implanted not only into the non-doped region 204 but also into the high-concentration N-type regions 111 and 121. However, since the high-concentration N-type regions 111 and 121 have a high concentration, even if a low-concentration phosphorus (P) ion is introduced, the high-concentration N-type region 11
The impurity concentrations of 1, 121 are hardly affected. Therefore, in the low-concentration impurity introduction step, an operation such as separately forming a mask for introducing the low-concentration impurity is not required, so that the step for forming the mask can be omitted, and the manufacturing cost can be reduced. Can be. Further, by etching the gate electrode twice, it is possible to prevent a defect from occurring in the wiring region due to the remaining pattern.

FIG. 4 is a block diagram schematically showing the configuration of the electro-optical device. In this electro-optical device, the N-type pixel TFT 10 and the driving circuit TFT and the P-type driving circuit T
An active matrix substrate on which an FT is formed is used. As shown in FIG. 4, a data line 90 and a scanning line 91 are formed on an active matrix substrate 301 for an electro-optical device so as to be orthogonal to each other. The gate of the pixel TFT 10 connected to the pixel electrode in each pixel is connected to the scanning line 91, and the source of the pixel TFT 10 is connected to the data line 90.

Each pixel has a liquid crystal cell 94 to which an image signal is input via the pixel TFT 10. For the data line 90, a data line driving circuit 60 including a shift register 84, a level shifter 85, a video line 87, and an analog switch 86 is formed on an active matrix substrate 301. Also, the scanning line 91
, The shift register 88 and the level shifter 8
9 is formed on an active matrix substrate 301.

The scanning line driving circuit 70 and the data line driving circuit 60 are composed of an N-type driving circuit TFT and a P-type driving circuit TFT. In each pixel, a storage capacitor 40 (capacitive element) may be formed between the pixel and the capacitor line 98.
4 has the function of improving the charge retention characteristics. Note that the storage capacitor 40 may be formed between the scanning line 91 and the preceding stage. The active matrix substrate 301 thus configured forms an electro-optical device as shown in FIGS.

FIG. 5 is a plan view of the electro-optical device, and FIG.
FIG. 6 is a sectional view taken along line HH ′ of FIG. 5. In these figures, the electro-optical device 401 is a counter substrate in which the above-described active matrix substrate 301 and a transparent insulating substrate 500 such as a quartz substrate or a high heat-resistant glass substrate are provided with a counter electrode 71 and a matrix light-shielding film 501. 302,
A liquid crystal (electro-optical material) 303 sealed and sandwiched between these substrates 301 and 302 is roughly constituted.

The active matrix substrate 301 and the counter substrate 302 are bonded to each other with a predetermined gap by a sealing layer 80 using a sealing material containing a gap material, and a liquid crystal 303 is sealed between the substrates 301 and 302. I have. As the seal layer 80, a polymer material such as an epoxy resin or various ultraviolet curable resins can be used. As the gap material, an inorganic or organic fiber or sphere having a diameter of about 2 μm to about 10 μm can be used.

The counter substrate 302 is smaller than the active matrix substrate 301,
The peripheral portion 1 is bonded so as to protrude outward from the outer peripheral edge of the counter substrate 302. Therefore, the scanning line driving circuit 60 and the data line driving circuit 70 of the active matrix substrate 301 are located outside the counter substrate 302. Further, since the input / output terminals 81 of the active matrix substrate 301 are also located outside the counter substrate 302, the flexible printed wiring board 402 can be connected to the input / output terminals 81 by wiring.

Here, the seal layer 80 is partially interrupted, and the interrupted portion constitutes the liquid crystal injection port 83. For this reason, after the active matrix substrate 301 and the counter substrate 302 are bonded to each other, if the area inside the seal layer 80 is depressurized, the liquid crystal 303 can be injected from the liquid crystal injection port 83 into the area inside the seal layer 80 under reduced pressure. Can be. In order to seal the liquid crystal 303, the liquid crystal 303 may be sealed in the inner region of the seal layer 80, and then the liquid crystal injection port 83 may be closed with the sealing agent 82. The counter substrate 302 includes
A light-shielding film 88 for cutting off the display area is formed inside the seal layer 80.

[0050]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a conductive film for a mask having the same size as the pattern of the organic thin film for a mask is used as a mask in the high-concentration impurity introducing step. Since a gate electrode obtained by selectively removing both sides of the mask conductive film is used as a mask for the low-concentration impurity introduction step, patterning of the gate electrode, introduction of high-concentration impurities, introduction of low-concentration impurities can be performed with one mask. Can be performed, and the steps can be simplified.

Further, a stable LDD structure capable of clearly distinguishing between a high concentration region and a low concentration region and avoiding deterioration with time due to an increase in impurity concentration in the low concentration region is provided. Can be. Accordingly, there is no possibility that a characteristic defect or the like due to a position shift or the like occurring at the time of mask alignment occurs, and a low-concentration region can be formed in a self-aligned manner.

As a mask for the impurity introduction step,
Since the mask conductive film and the gate electrode, which are more resistant than the mask organic thin film, are used, the gate length and the width of the low concentration region on both sides of the LDD structure can be made uniform. Thereby, the LDD structure of the obtained semiconductor device can be made a stable structure, and the reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device obtained by a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and is a process diagram showing each step performed after the step shown in FIG. 2;

FIG. 4 is a block diagram illustrating a configuration of an active matrix substrate for an electro-optical device to which the present invention has been applied.

FIG. 5 is a plan view of an electro-optical device showing an example of using an active matrix substrate.

6 is a cross-sectional view of the electro-optical device shown in FIG. 5, taken along line HH ′.

FIG. 7 is a process chart showing a conventional method for manufacturing a TFT having an LDD structure.

[Explanation of symbols]

 Reference Signs List 1 glass substrate 2 base oxide film 3 polysilicon film (semiconductor film) 4 gate oxide film (gate insulating film) 5 gate electrode 6, 7 source / drain electrode 8 pixel electrode 10 TFT for pixel 11, 12 source / drain region 13 channel Forming region 21 Lower interlayer insulating film 22, 23 Contact hole 24 Upper interlayer insulating film 25 Contact hole 111, 121 High-concentration N-type region 112, 122 Low-concentration N-type region 201 Polysilicon film 202 Conductive film for gate electrode formation 202a Conductive film for mask 203 Resist film (organic thin film for mask) 203a Resist mask 204 Non-doped region 301 Active matrix substrate 302 Counter substrate 303 Liquid crystal (electro-optical material) 401 Electro-optical device

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toru Takeguchi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 2H092 JA25 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB57 KA04 KA07 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA35 MA37 MA41 NA27 NA28 PA06 5C058 AA08 AB06 BA35 5F110 AA14 AA16 BB02 BB04 CC02 DD02 DD03 DD13 DD14 DD17 EE03 EE04 FF02 FF23 FF29 FF30 GG02 GG13 H12 GG32 HGG

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device in which a thin film transistor is formed on a substrate, wherein a multi-layer film in which a gate insulating film, a conductive film for forming a gate electrode, and an organic thin film for a mask are sequentially formed on a surface of a semiconductor film forming the thin film transistor. Forming a conductive film for a mask, using the organic thin film for a mask as a mask, and patterning the conductive film for forming a gate electrode to form a conductive film for a mask having the same size as the pattern of the organic thin film for a mask. A high-concentration impurity introducing step of introducing a high-concentration impurity into the semiconductor film using the organic thin film for mask and the conductive film for mask as a mask; and selectively removing both side portions of the conductive film for mask. A gate electrode forming step of forming a gate electrode of the thin film transistor smaller than the pattern of the organic thin film, Method of manufacturing a semiconductor device film is removed, and having a low concentration impurity introduction step of introducing a low concentration of impurities in the semiconductor film by the gate electrode as a mask. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the selective removal of both sides of the mask conductive film is performed by a wet etching method. 3. The high-concentration impurity introducing step includes introducing an impurity into the semiconductor film at a dose of 1 × 10 ¹⁵ cm ⁻² or more. In the low-concentration impurity introducing step, the impurity is introduced into the semiconductor film by 1 × 10 ¹⁵ cm ^−2. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is introduced at a dose of less than 10 ¹⁵ cm ^-2 . 4. The method according to claim 1, wherein the thin film transistor is an N-type thin film transistor or a P-type thin film transistor. 5. A thin film transistor for pixel switching and a thin film transistor for a driving circuit, comprising the thin film transistor, and a conductive film different from the thin film transistor, on the same substrate, using the method of manufacturing a semiconductor device according to claim 1. A method for manufacturing an active matrix substrate, comprising forming a thin film transistor for a drive circuit comprising a thin film transistor of a type. 6. An electro-optical device comprising an electro-optical material sandwiched between an active matrix substrate manufactured by using the active matrix substrate manufacturing method according to claim 5 and a counter substrate.