JP2001320031A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve charge holding capability of a cell while the space factor of the cell is reduced, in a trench type DRAM cell. SOLUTION: A node electrode 22 of a trench capacitor is buried and formed in a surface part of, e.g. a P-type silicon substrate 11. Just above the node electrode 22, a transfer gate transistor constituted of a vertical type MOSFET is formed. As a result, the charge holding capability of a cell can be improved sufficiently without increasing the space factor of the cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a trench type DRAM (Dynamic Random Accesses).
s read write memory) cell.

[0002]

2. Description of the Related Art The degree of integration of semiconductor memory devices has been improved year by year, and the progress has been remarkable. In particular, among them,
DRAMs are required to have a high degree of integration. An important factor in increasing the degree of integration of a DRAM is improving the short channel characteristics of the transfer gate transistor in the DRAM cell.

One factor that determines the charge retention capability of a DRAM cell is the cutoff current of a transfer gate transistor. Transfer gate transistors are required to have a cutoff current that is at least two orders of magnitude lower than transistors used in peripheral circuits.

However, as the integration of DRAMs has increased, the transfer gate transistor has a gate length of less than 0.2 μm, and the latest one has a gate length of less than 0.1 μm.
It is about to reach μm. Therefore, the short channel effect of the transfer gate transistor is suppressed,
It has become very difficult to achieve a sufficiently low cutoff current.

[0005]

As described above, in the prior art, while achieving high integration, it is necessary to achieve a sufficiently low cutoff current by suppressing the short channel effect of the transfer gate transistor. There was a problem that it was becoming very difficult.

Therefore, the present invention provides a semiconductor memory capable of greatly reducing the cell occupation area, and further, capable of sufficiently reducing the cut-off current of the transfer gate transistor and increasing the charge retention capability of the cell. It is an object to provide an apparatus and a method for manufacturing the same.

[0007]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a semiconductor substrate, a trench capacitor formed on a main surface of the semiconductor substrate, and a trench capacitor. A vertical transistor provided on the capacitor, wherein the charge carriers move in a direction perpendicular to the surface of the semiconductor substrate.

In the method of manufacturing a semiconductor memory device according to the present invention, a step of forming a trench in a main surface of a semiconductor substrate and a step of forming a capacitor insulating film of a trench capacitor on a wall surface of the trench are performed. A step of burying a node electrode of the trench capacitor inside the trench via the capacitor insulating film, and a step of forming a plate electrode of the trench capacitor on a part of the semiconductor substrate along the capacitor insulating film. Forming a gate electrode of a vertical transistor on a main surface of the semiconductor substrate via an insulating film, and forming a through hole penetrating the gate electrode and the insulating film and reaching the node electrode; Forming a gate insulating film of a vertical transistor on a side wall surface of the through hole; and forming the gate insulating film through the gate insulating film. Embedding a semiconductor layer serving as a channel of the vertical transistor therein, a first diffusion layer of the vertical transistor below the semiconductor layer, and a second diffusion layer of the vertical transistor above the semiconductor layer. Forming diffusion layers, respectively.

Further, in the method of manufacturing a semiconductor memory device according to the present invention, a step of forming a gate electrode of a vertical transistor on a main surface of a semiconductor substrate via an insulating film, the step of forming the gate electrode and the insulating film Forming a through-hole reaching the surface of the semiconductor substrate by penetrating the semiconductor substrate; opening a trench connected to the through-hole in a main surface portion of the semiconductor substrate; and forming a trench capacitor on a wall surface of the trench. Forming a capacitor insulating film of the same type, and a gate insulating film of a vertical transistor on the wall portion of the through hole by the same film; and forming a node electrode of the trench capacitor inside the trench via the capacitor insulating film. Embedding a semiconductor layer in the through-hole via the gate insulating film; and forming a first diffusion layer below the semiconductor layer. And, a second diffusion layer in the upper portion of the semiconductor layer, characterized by comprising a step for forming, respectively.

According to the semiconductor memory device and the method of manufacturing the same of the present invention, the vertical transistor and the trench capacitor can be arranged very close to each other. This makes it possible to sufficiently increase the charge holding capacity of the cell without increasing the area occupied by the cell.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 14 schematically show a method of manufacturing a trench type DRAM cell according to a first embodiment of the present invention.

First, as shown in FIG. 1, the surface of a semiconductor substrate, for example, a P-type silicon substrate (plane orientation (100)) 11 having a specific resistance of 4 to 6 .OMEGA. After the oxide film 12 is formed, a silicon nitride film 13 having a thickness of about 1500 Å and a silicon oxide film 14 having a thickness of about 3000 Å are deposited thereon by the CVD method.

Next, as shown in FIG.
Photoresist film 1 in which a square hole of about m length is formed
5 using the silicon oxide film 1 as an etching mask.
4. The silicon nitride film 13 and the thermal oxide film 12 are respectively removed by RIE.

Next, after the photoresist film 15 is removed, as shown in FIG. 3, the silicon oxide film 14, the silicon nitride film 13, and the thermal oxide film 12 are used as a mask for forming a trench. A trench 16 having a depth of about 5 μm is formed on the surface of the silicon substrate 11 by RIE.

Next, as shown in FIG. 4, a silicon oxide film (AsSG film) 17 containing a high concentration of arsenic (As)
Deposited in a thickness of about 00 angstroms,
A silicon oxide film 18 containing no impurities is formed thereon by 500
Deposit in a thickness of about Angstrom. And 9
Annealing is performed at a temperature of about 00 ° C. to form a plate electrode 19 of an N-type trench capacitor on the side wall of the trench 16.
To form

Next, as shown in FIG. 5, the AsSG film 17 and the silicon oxide film 18 are removed with hydrofluoric acid. Thereafter, a silicon nitride film 20 having a thickness of about 70 angstroms is deposited by the LPCVD method.
By thermally oxidizing at a temperature of 00 ° C. to form an oxide film 21 having a thickness of about 30 Å on the silicon nitride film 20, NO which becomes a capacitor insulating film of a trench is formed.
Form a film.

Next, as shown in FIG. 6, a polysilicon film heavily doped with arsenic is deposited to a thickness of about 3000 Å to fill the trench 16. Further, the entire surface is etched by RIE so that the height of the upper surface of the polysilicon film is lower than the height of the surface of the silicon substrate 11 by about 500 angstroms. An electrode 22 is formed.

Next, as shown in FIG. 7, a silicon oxide film 23 is deposited to a thickness of about 3000 angstroms. Then, the silicon nitride film 13 is formed by a CMP method.
Is used as a stopper film to planarize the silicon oxide film 23 so as to bury the upper part of the node electrode 22. Thereafter, the silicon nitride film 13 is removed with high-temperature phosphoric acid.

Next, as shown in FIG. 8, etching is performed with hydrofluoric acid so that the height of the upper surface of the silicon oxide film 23 is the same as the height of the surface of the silicon substrate 11, thereby completing a trench capacitor. Let it.

Next, as shown in FIG. 9, a silicon oxide film 24 having a thickness of about 1000 angstroms is deposited on the P-type silicon substrate 11, and a low concentration P (phosphorus) doped at a high concentration is deposited thereon. 300 polysilicon film of resistance
It is deposited with a thickness of about 0 Å. afterwards,
Using the photoresist film (not shown) as a mask material, the polysilicon film is processed into a desired shape by RIE to form a gate electrode 25 of a vertical MOSFET serving as a transfer gate transistor.

Further, after removing the photoresist film,
On the gate electrode 25, a silicon oxide film is deposited to a thickness of about 6000 angstroms. Then, the surface is polished and flattened by the CMP method so that the silicon oxide film 26 is left on the gate electrode 25 with a thickness of about 2000 Å.

Next, as shown in FIG. 10, on the silicon oxide film 26, a photoresist film 27 in which a square hole having a side of about 0.3 μm in length is formed. The holes are formed in the photoresist film 27 so as to correspond to the inside of the trench capacitor (the node electrode 22 of the trench capacitor) as a position on a plane viewed from the surface of the silicon substrate 11.

Thereafter, using the photoresist film 27 as a mask, the silicon oxide film 26, the gate electrode 2
5. A node electrode (polysilicon film) 2 of a trench capacitor penetrating through the silicon oxide film 24 and the silicon oxide film 23 and buried in the trench 16
An opening 28 is formed by RIE so as to reach No. 2. In this case, RIE is controlled so that etching is performed on each film under optimum conditions while changing gas, temperature, and the like.

Next, after removing the photoresist film 27, as shown in FIG. 11, an oxide film (gate insulating film) 29 having a thickness of about 100 angstroms is deposited.
Densify in an oxygen atmosphere at about 00 ° C.

Thereafter, amorphous silicon containing boron (B) at a low concentration is deposited to a thickness of about 500 angstroms by LPCVD. Then, the entire surface of the amorphous silicon is etched by the RIE method, and processing is performed so that the amorphous silicon film 30 remains on the side wall of the opening 28.

Next, as shown in FIG. 12, after the oxide film 29 on the node electrode 22 of the trench capacitor is removed by dilute hydrofluoric acid, an amorphous silicon film 31 containing boron at a low concentration is formed to a thickness of about 2,000 angstroms. Then, the inside of the opening 28 is buried.

Thereafter, annealing is performed at a temperature of about 600 ° C., and the amorphous silicon films 30 and 31 are recrystallized to form a polysilicon film (semiconductor layer) having large grains and relatively few crystal defects.

Next, as shown in FIG. 13, the entire surface of the recrystallized polysilicon film 32 is polished by the CMP method, and the inside of the opening 28 is completely polished by the polysilicon film 32 in which a channel is formed later. Embed in

Further, after arsenic is ion-implanted, the arsenic is annealed at a temperature of about 850 ° C. to activate the arsenic.
And are formed. The lower diffusion layer 34 is formed by diffusing arsenic contained in the node electrode 22 of the trench capacitor.

Each of the upper and lower diffusion layers 33 and 34 of the vertical MOSFET is partially formed by the gate electrode 25.
And overlap, that is, vertical MOSFE
The arsenic diffusion distance is controlled by adjusting the activation annealing condition so that the T source / drain does not have an offset structure.

Next, as shown in FIG. 14, after a contact hole to the gate electrode 25 of the vertical MOSFET is formed in the silicon oxide film 26, the barrier metal film 3 of TiN is formed.
5. An Al film 36 is deposited by a sputtering method, and a bit line of a DRAM cell array is formed on the upper diffusion layer 33, and a wiring to the gate electrode 25 serving as a word line is formed.

Thereafter, an oxide film 37 and a silicon nitride film 38 are deposited to a thickness of about 3000 angstroms, respectively, by a plasma CVD method to form an uppermost protective film, thereby completing a trench type DRAM cell.

According to such a trench type DRAM cell, immediately above the node electrode of the trench capacitor,
Since the transfer gate transistor constituted by the vertical transistor is provided, the transfer gate transistor and the trench capacitor can be arranged very close to each other. This allows
The occupied area of the cell can be significantly reduced as compared with the conventional trench type cell in which the transfer gate transistor and the trench capacitor are arranged side by side on the silicon substrate.

Further, by electrically separating the node electrode and the transfer gate transistor of the trench capacitor from the silicon substrate by the insulating film, the electric charge held in the capacitor is transferred to the bit line via the transfer gate transistor. Since there is only a leak path that flows, the cutoff current of the transfer gate transistor directly serves as the charge retention capability of the cell.

That is, the cut-off current of the vertical transistor is proportional to the cross-sectional area of the polysilicon film 32 where the channel is formed, and is inversely proportional to the thickness of the gate electrode 25 in the vertical direction, that is, the gate length. Therefore, in order to suppress the cut-off current, the cross-sectional area of the columnar polysilicon film 32 embedded in the opening 28 is reduced as far as the processing technology allows.
In addition, the gate length, that is, the thickness of the gate electrode 25 may be increased. In this case, the reduction in the cross-sectional area of the polysilicon film 32 and the increase in the film thickness of the gate electrode 25 do not work in the direction of increasing the occupied area of the cell, and therefore, without increasing the occupied area of the cell. The charge holding ability can be increased.

(Second Embodiment) FIGS. 15 to 24 schematically show a method of manufacturing a trench type DRAM cell according to a second embodiment of the present invention.

First, as shown in FIG.
On a P + type silicon substrate (plane orientation (100)) 51 having a specific resistance of 0.005 Ω · cm to 0.01 Ω · cm,
An epitaxial substrate (semiconductor substrate) is prepared by epitaxially growing a P-type silicon layer (plate electrode of a trench capacitor) 52 having a specific resistance of 4 to 6 Ω · cm with a thickness of about 1 μm.

Next, as shown in FIG. 16, a silicon oxide film 53 having a thickness of about 1000 Å is deposited on the P-type silicon layer 52, and a low-resistance polysilicon doped with a high concentration of phosphorus is formed thereon. A silicon film is deposited to a thickness of about 3000 angstroms. Thereafter, the polysilicon film is processed into a desired shape by RIE using a photoresist film (not shown) as a mask material.
Vertical MOS as transfer gate transistor
The gate electrode 54 of the FET is formed.

Further, after removing the photoresist film,
On the gate electrode 54, a silicon oxide film is deposited to a thickness of about 5000 angstroms. Then, the surface is polished and flattened by the CMP method so that the silicon oxide film 55 is left with a thickness of about 1500 Å on the gate electrode 54.

Next, as shown in FIG. 17, a silicon nitride film 56 is deposited to a thickness of about 1000 angstroms, and a silicon oxide film 57 is further deposited to a thickness of about 3000 angstroms. One side is 0.
A photoresist film 58 having a square hole having a length of about 4 μm is formed.

Next, as shown in FIG. 18, using the photoresist film 58 as a mask, the silicon oxide film 5 is formed.
7, the silicon nitride film 56, the silicon oxide film 5
5. An opening window (through hole) is formed by RIE so as to penetrate all of the gate electrode 54 and the silicon oxide film 53 and reach the P-type silicon layer 52. In this case, RIE is controlled so that etching is performed on each film under optimum conditions while changing gas, temperature, and the like.

Next, after removing the photoresist film 58, as shown in FIG. 19, the silicon oxide film 57 is used as a mask material to penetrate the P-type silicon layer 52 and reach the silicon substrate 51. A trench 59 having a depth of about 5 μm is formed.

Next, as shown in FIG. 20, a silicon nitride film (Si ₃ N ₄ film) 6 having a thickness of about 70 Å is formed.
Is deposited on the silicon nitride film 60 by thermal oxidation at a temperature of about 900 ° C. to form an oxide film 61 having a thickness of about 30 angstroms. A film and a gate insulating film of a vertical MOSFET are formed.

Next, a polysilicon film heavily doped with arsenic is deposited to a thickness of about 3000 Å to fill the trench 59. Further, the polysilicon film is etched by isotropic dry etching having high selectivity to the silicon oxide film. In this case, the height of the upper surface of the polysilicon film is
Processing is performed so as to be lower than the height of the bottom surface of the gate electrode 54 of the vertical MOSFET by about 1000 angstroms, thereby forming the node electrode 62 of the trench capacitor.

Next, amorphous silicon containing boron at a low concentration is deposited on the node electrode 62 to a thickness of about 3000 angstroms. Then 600
The amorphous silicon is recrystallized by annealing at a temperature of about ℃ to form a polysilicon film (semiconductor layer) having large grains and relatively few crystal defects.

Next, the entire surface of the recrystallized polysilicon film is etched by RIE, and the height of the upper surface of the polysilicon film 63 where a channel is to be formed later is set to the vertical MOSF.
The ET is processed so as to be about 2,000 Å above the height of the upper surface of the gate electrode 54 (see FIG. 21).

The semiconductor layer can be formed by a selective epitaxial growth method. For example, by selective epitaxial growth, silicon containing boron at a low concentration is deposited only on the upper surface of the node electrode 62 of the trench capacitor to a height of about 2,000 Å above the height of the upper surface of the gate electrode 54 of the vertical MOSFET. It can be similarly formed by growing.

Next, after removing the silicon oxide film 57 used as the mask material with hydrofluoric acid, as shown in FIG. 22, the silicon nitride film 56 is removed with high-temperature phosphoric acid.

Next, as shown in FIG. 23, the upper surface of the polysilicon film 63 left by polishing by the CMP method is left flat. Then, after arsenic is ion-implanted, 85
Activated by annealing at a temperature of about 0 ° C.
An upper diffusion layer 64 and a lower diffusion layer 65 of the OSFET are formed.

As in the case of the manufacturing method according to the first embodiment, the lower diffusion layer 65 is formed by diffusing arsenic contained in the node electrode 62 of the trench capacitor.

Each of the upper and lower diffusion layers 64 and 65 of the vertical MOSFET is partially formed by the gate electrode 54.
And overlap, that is, vertical MOSFE
The arsenic diffusion distance is controlled by adjusting the activation annealing condition so that the T source / drain does not have an offset structure.

Next, as shown in FIG. 24, as in the case of the manufacturing method according to the first embodiment, after the wiring is formed by the TiN barrier metal film 69 and the Al film 66, the plasma CVD method is performed. An oxide film 67 and a silicon nitride film 68 are each deposited to a thickness of about 3000 Å to form a top protective film, thereby completing a trench type DRAM cell.

Even with such a trench type DRAM cell, the trench type DRAM cell according to the above-described first embodiment can be used.
An effect similar to that of the RAM cell can be expected. That is, it is possible to sufficiently increase the charge holding capacity of the cell without increasing the area occupied by the cell.

In particular, in the case of the manufacturing method according to the second embodiment of the present invention, since the trench capacitor and the aperture window in which the channel of the transfer gate transistor is formed can be continuously opened, the steps Can be simplified, and the problem of misalignment occurring when the photolithography process is performed in a plurality of times can be solved, so that further miniaturization is possible.

When the capacitor insulating film and the gate insulating film of the transfer gate transistor can be formed of the same film as in the manufacturing method according to the second embodiment, the steps can be simplified. This leads to a reduction in manufacturing costs.

Of course, various modifications can be made without departing from the spirit of the present invention.

[0058]

As described in detail above, according to the present invention, the occupied area of the cell can be greatly reduced, and the cut-off current of the transfer gate transistor is sufficiently reduced to maintain the charge of the cell. It is possible to provide a semiconductor memory device and a method of manufacturing the same, which can increase the capacity.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a trench DRAM cell according to a first embodiment of the present invention;

FIG. 2 is also a process sectional view illustrating the method for manufacturing the trench DRAM cell;

FIG. 3 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell.

FIG. 4 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell.

FIG. 5 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell.

FIG. 6 is a process sectional view shown for explaining the method of manufacturing the trench DRAM cell;

FIG. 7 is also a process sectional view shown for explaining the method of manufacturing the trench DRAM cell;

FIG. 8 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell.

FIG. 9 is a process sectional view shown for explaining the method of manufacturing the trench DRAM cell;

FIG. 10 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 11 is a process sectional view shown for explaining the method of manufacturing the trench DRAM cell;

FIG. 12 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 13 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 14 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 15 is a process cross-sectional view shown for explaining the method for manufacturing the trench DRAM cell according to the second embodiment of the present invention.

FIG. 16 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 17 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 18 is also a process sectional view shown for explaining the method of manufacturing the trench DRAM cell;

FIG. 19 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 20 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 21 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 22 is a process sectional view shown for explaining the method of manufacturing the trench DRAM cell;

FIG. 23 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

FIG. 24 is a process sectional view similarly illustrating the method for manufacturing the trench DRAM cell;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... P-type silicon substrate 12 ... Thermal oxide film 13 ... Silicon nitride film 14 ... Silicon oxide film 15 ... Photoresist film 16 ... Trench 17 ... Silicon oxide film (AsSG film) 18 ... Silicon oxide film 19 ... Plate electrode 20 ... Silicon Nitride film 21 oxide film 22 node electrode 23 silicon oxide film 24 silicon oxide film 25 gate electrode 26 silicon oxide film 27 photoresist film 28 opening portion 29 oxide film (gate insulating film) 30, DESCRIPTION OF SYMBOLS 31 ... Amorphous silicon film 32 ... Polysilicon film 33 ... Upper diffusion layer 34 ... Lower diffusion layer 35 ... Barrier metal film 36 ... Al film 37 ... Oxide film 38 ... Silicon nitride film 51 ... P + type silicon substrate 52 ... P type Silicon layer 53 ... Silicon oxide film 54 ... Gate electrode 55 ... Silicon oxide film 56 ... Silicon nitride film 7 ... silicon oxide film 58 ... photoresist film 59 ... trench 60 ... silicon nitride film _(Si 3 _{N 4} film) 61 ... oxide film 62 ... node electrode 63 ... polysilicon film 64 ... top of the diffusion layer 65 ... lower diffusion layer 66 ... Al film 67 ... Oxide film 68 ... Silicon nitride film 69 ... Barrier metal film

Claims (22)

[Claims] A semiconductor substrate; a trench capacitor formed in a main surface portion of the semiconductor substrate; and a vertical portion provided on the trench capacitor and in which charge carriers move in a direction perpendicular to a surface of the semiconductor substrate. A semiconductor memory device comprising: a type transistor. 2. The trench capacitor has a capacitor insulating film formed on a wall surface of a trench opened in a main surface portion of the semiconductor substrate, and is embedded in the trench via the capacitor insulating film. 2. The semiconductor device according to claim 1, further comprising a node electrode provided, and a plate electrode provided on at least a part of the semiconductor substrate via the capacitor insulating film between the node electrode. 3. Semiconductor storage device. 3. The semiconductor memory device according to claim 2, wherein said plate electrode is provided along a wall surface of said trench. 4. The semiconductor memory device according to claim 2, wherein said plate electrode is provided on a silicon substrate constituting a part of said semiconductor substrate. 5. The semiconductor memory device according to claim 4, wherein said trench penetrates said plate electrode and is provided at a depth reaching said silicon substrate. 6. The vertical transistor is provided on a main surface of the semiconductor substrate with an insulating film interposed therebetween, and a gate electrode penetrating the gate electrode and the insulating film and reaching the node electrode. A semiconductor layer buried in the through hole with a gate insulating film provided on the side wall surface thereof, a first diffusion layer provided below the semiconductor layer, and a semiconductor layer embedded above the semiconductor layer. 2. The semiconductor memory device according to claim 1, further comprising a second diffusion layer provided. 7. The semiconductor memory device according to claim 6, wherein said first diffusion layer of said vertical transistor is electrically connected to said node electrode. 8. The semiconductor device according to claim 1, wherein the first diffusion layer of the vertical transistor does not protrude from an upper surface of the node electrode.
The semiconductor memory device according to claim 7, wherein the semiconductor memory device is provided to have a smaller cross-sectional area than the node electrode. 9. The semiconductor device according to claim 1, wherein the first diffusion layer of the vertical transistor does not protrude from an upper surface of the node electrode.
The semiconductor memory device according to claim 7, wherein the semiconductor memory device is provided to have the same cross-sectional area as the node electrode. 10. The semiconductor memory device according to claim 2, wherein said through hole of said vertical transistor and said trench of said trench capacitor are integrally formed. 11. The semiconductor memory device according to claim 2, wherein said gate insulating film of said vertical transistor and said capacitor insulating film of said trench capacitor are formed of the same film. 12. The semiconductor according to claim 6, wherein a channel of the vertical transistor is formed between the first diffusion layer and the second diffusion layer of the semiconductor layer. Storage device. 13. The semiconductor memory device according to claim 12, wherein at least a side surface of said semiconductor layer where said channel is formed is covered by said gate electrode. 14. A step of forming a trench in a main surface portion of a semiconductor substrate, a step of forming a capacitor insulating film of a trench capacitor on a wall surface of the trench, and a step of forming a trench in the trench via the capacitor insulating film. A step of burying a node electrode of the trench capacitor therein; a step of forming a plate electrode of the trench capacitor in a part of the semiconductor substrate along the capacitor insulating film; and a step of forming an insulating film on a main surface of the semiconductor substrate. Forming a gate electrode of the vertical transistor; forming a through hole that penetrates the gate electrode and the insulating film to reach the node electrode; A step of forming a gate insulating film; and a semiconductor serving as a channel of a vertical transistor in the through hole via the gate insulating film. And a step of forming a first diffusion layer of a vertical transistor below the semiconductor layer and a second diffusion layer of a vertical transistor above the semiconductor layer, respectively. A method for manufacturing a semiconductor memory device, comprising: 15. The semiconductor device according to claim 14, wherein the through hole has a smaller sectional area than the node electrode so as not to protrude from an upper surface of the node electrode.
6. The method for manufacturing a semiconductor memory device according to claim 1. 16. A step of forming a gate electrode of a vertical transistor on a main surface of a semiconductor substrate via an insulating film, and a through hole reaching the surface of the semiconductor substrate through the gate electrode and the insulating film. Forming a trench connected to the through hole in the main surface of the semiconductor substrate; forming a capacitor insulating film of a trench capacitor on a wall of the trench; and forming a wall of the through hole. Forming a gate insulating film of a vertical transistor with the same film, embedding a node electrode of a trench capacitor inside the trench through the capacitor insulating film, and forming the gate insulating film through the gate insulating film. Embedding a semiconductor layer in the through-hole; forming a first diffusion layer below the semiconductor layer and a second diffusion layer above the semiconductor layer; Forming a semiconductor memory device. 17. The method according to claim 16, wherein a plate electrode of a trench capacitor is previously formed on a part of the semiconductor substrate. 18. The method according to claim 16, wherein the opening of the trench is performed continuously to the through hole. 19. The method according to claim 14, wherein the first diffusion layer has a top surface provided at a height overlapping with the gate electrode. 20. The method according to claim 14, wherein the lower surface of the second diffusion layer is provided at a height overlapping the gate electrode. 21. The method according to claim 14, wherein the semiconductor layer is formed by recrystallizing an amorphous silicon film. 22. The method according to claim 16, wherein the semiconductor layer is formed by selectively growing an epitaxial film in the through hole.