JP2001319929A - Method for increasing process window of chemical/ mechanical polishing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the process window of chemical/mechanical polishing(CMP) and to simplify a photolithography process. SOLUTION: In a CMP process, a substrate is installed, a dielectric layer is formed on the substrate and a cap layer is formed on the dielectric layer. A part of the cap layer and a part of the dielectric layer are moved so that an opening is formed for exposing a part of the substrate. A metallic layer is formed on the cap layer for filling the opening and a part of metal outside the opening is removed until the cap layer is exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the process of chemical mechanical polishing (CMP), and more particularly to a method of increasing the process window of a CMP, which also simplifies the photolithography process.

[0002]

BACKGROUND OF THE INVENTION At many stages during the manufacture of integrated circuit devices, it is often necessary to remove one or more layers from the surface of the device. In addition, wafers often must be planarized before subsequent processing operations can be performed. Currently, chemical mechanical polishing (CMP) is one of the techniques that provides a wide range of flatness. Chemical and mechanical products that emerged after decades of research and development are microprocessors and memories.

[0003] Chemical mechanical polishing begins by mounting a silicon wafer on a fixed holder and pressing the entire surface of the wafer onto a polishing table having a layer of polishing pad material thereon. The polishing table rotates in a predetermined direction. During polishing, the amount of pressure acting on the wafer is controlled and the slurry is continuously supplied to the polishing pad surface through a pipe. The slurry is composed of colloidal silicon, dispersed aluminum and potassium hydroxide (KO).
H) or ammonium hydroxide (NH ₄ OH). By using these highly abrasive components in the slurry, the silicon wafer surface is actively polished.

[0004] For example, device structures such as field effect transistors and bipolar transistors are formed on a provided substrate. The substrate is covered by an insulating layer. The insulating layer has a contact hole or via formed therein. Metal materials such as tungsten are filled into contact holes or vias to form wiring lines. Tungsten is formed by chemical vapor deposition (CVD). A portion of the tungsten is removed outside the contact hole or via, so that the tungsten remaining in the contact hole or via is used to form a plug. The step of removing tungsten can be done in several ways. One method is reactive ion etching (RIE). However, RIE causes over-etching and removes tungsten from contact holes or vias. As a result, a recess is formed on the tungsten plug. The recess opens between tungsten and a wiring line formed in the next step. RIE also forms particles, which deposit on the substrate and contaminate it. Another method of removing tungsten is chemical mechanical polishing (CMP).

[0005] One known CMP process consists of two steps. The first step is performed using a slurry with a low pH oxidant to remove unwanted tungsten and form a dielectric layer. When making the first step, the dielectric layer can be used as a polishing stop layer. The second step is performed with a slurry having a high pH value to planarize the dielectric layer.

In the above CMP process, the first stage damages the dielectric layer. The wound captures the contaminants and causes a short circuit in the conductor structure. Therefore, it is necessary to mitigate the wound in the second stage. A portion of the dielectric layer is removed in a second step. The thickness of the removed dielectric layer is at least equal to the depth of the flaw.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide CMP.
And a method for increasing the process window.

[0008]

SUMMARY OF THE INVENTION The method of the present invention employs a one-step CMP process for polishing tungsten without forming flaws on the dielectric surface.

The method of the present invention comprises forming a plane of a dielectric layer on a provided substrate having a semiconductor such as a transistor formed thereon. The cap layer is formed on the dielectric layer. The stiffness of the cap layer is more stiff than the stiffness of the dielectric layer. Photolithography and etching processes are performed to form openings in the dielectric and cap layers to expose portions of the substrate. The tungsten layer is formed on the cap layer and in the opening. A one-step CMP process is performed to remove a portion of the tungsten layer out of the opening until the cap layer is exposed.

During the CMP process, the cap layer is used as a polish stop layer. Because the cap layer is stiffer than the dielectric layer, the cap layer is less likely to be damaged. Since the dielectric layer is protected by the cap layer and there is no scruff on the cap layer, the second step of mitigating the scuff in the prior art is removable.

Furthermore, the material of the cap layer has a low reflectivity, so that the cap layer can be used as an anti-reflective layer during a subsequent step to define a layer of material on the tungsten layer. The step of forming the anti-reflection layer on the dielectric layer and the tungsten plug may be omitted. Therefore, the process of forming the metal interconnect structure is simplified.

[0012]

Other objects, features and advantages of the present invention will become apparent from the following detailed description of non-limiting embodiments. The description is made below with reference to the drawings.

FIGS. 1 through 5 are cross-sectional views illustrating the process steps of one preferred embodiment of a method for increasing the process window of a CMP.

Referring to FIG. 1, a substrate 100 is provided. A semiconductor structure such as a bipolar or field effect transistor (FET) is formed on a substrate 100. In a preferred embodiment, the transistors are formed on substrate 100. Each transistor comprises a gate 102 on a substrate 100 and a spacer 104 beside it. The source / drain regions of the transistor are not shown.

A dielectric layer 106 such as BPSG is formed on the substrate 100 by spin coating. A dielectric layer 106 is formed between the transistors and has a flat top surface. The thickness of the dielectric layer 106 is sufficient to fill the space between the transistors.

Referring to FIG. 2, a dielectric layer 108 is formed over the dielectric layer 106 and the transistor. Dielectric layer 1
A preferred material of 08 comprises TEOS oxide. After forming the dielectric layer 108, a cap layer 110 is formed on the dielectric layer 108. The thickness of the cap layer 110 is about 5
It is between 00 and 1000 angstroms. Preferred materials of the cap layer 110 is made of silicon nitride or silicon oxynitride _(SiO x _{N y).}

Referring to FIG. 3, a photolithography and etching process is performed on a portion of the cap layer 110,
This is performed to remove a part of the dielectric layer 108 and a part of the dielectric layer 106. Openings 112 between the transistors are thus formed to expose a portion of substrate 100. The remaining cap layer is shown as 110a.

Referring to FIG. 4, insulation protection (confo
rmal) An adhesive layer (or barrier layer) 114 is formed on the structure shown in FIG. A metal layer 116, such as tungsten, may be used to completely fill the openings 112
Formed on top. Adhesive layer 114 is used to enhance the adhesion between metal layer 116 and dielectric layers 106 and 108. Adhesive layer 114 is also used to prevent the material of metal layer 116 from diffusing into substrate 100 into dielectric layers 106 and 108.

Referring to FIG. 5, a CMP process is performed to remove a portion of the metal layer 116 outside the opening 112 and a portion of the adhesive layer 114 until the cap layer 110a is exposed. Metal plug 116a and remaining adhesive layer 1
14a is thus formed in the opening 112.

Because the cap layer is stiffer than the dielectric layer, the cap layer can be used as a polish stop layer when removing the metal and adhesive layers. The process window of the CMP is thus increased. The dielectric layer under the cap layer is also the CM
Protected from being damaged during the P process.

Furthermore, the cap layer is on the BPSG layer. There is no need to form a TEOS oxide layer on the BPSG layer. After forming the BPSG layer having a flat top surface, the cap layer can be formed directly on the BPSG layer. However, in this situation, the BPSG layer must be formed over the transistor on the substrate.

The material of the cap layer has a low reflectivity.
After forming the metal plug, a metal layer is formed and defined on the cap layer to form a wiring line. During the definition of the metal layer, the cap layer is used as an anti-reflection layer, so that no additional anti-reflection layer needs to be formed on the cap layer before forming the metal layer. Thus, the process steps are simplified.

While the invention has been described in detail by way of examples and preferred embodiments, the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the claims must be interpreted in the broadest sense to cover all such modifications and similar arrangements and procedures.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating process steps of one preferred embodiment of a method for increasing a process window of a CMP.

FIG. 2 is a cross-sectional view illustrating process steps of one preferred embodiment of a method for increasing a process window of a CMP.

FIG. 3 is a cross-sectional view illustrating process steps of one preferred embodiment of a method for increasing a process window of a CMP.

FIG. 4 is a cross-sectional view illustrating the process steps of one preferred embodiment of a method for increasing the process window of a CMP.

FIG. 5 is a cross-sectional view illustrating the process steps of one preferred embodiment of a method for increasing the process window of a CMP.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Substrate 102 Gate 104 Spacer 108,106 Dielectric layer 110,110a Cap layer 112 Opening 114,114a Adhesive layer 116,116a Metal layer

Continuation of the front page (71) Applicant 599116362 Mosel Viteric Inc., Taiwan, Sinchu, Science-Based Industrial Park, Rishin Road, No. 19 (71) Applicant 599002401 Siemens AG Germany, D-80333, München, Wittelsbacher Platz 2 (72) Inventor Yun-Nien Tong Taiwan, Taipei, Chun-Shan-en-N Road, Section 2, Lanes 11, 11, 3F-1F Term ( Reference) 5F033 HH07 JJ19 KK01 NN06 NN07 QQ04 QQ09 QQ37 QQ48 QQ49 RR02 RR06 RR08 RR15 SS04 SS21 TT02 XX01 5F045 AB32 AB33 AB34 AB35 AB36 AB40 CA01 CB04 CB05 GH10 HA12

Claims (14)

[Claims] Providing a substrate; forming a dielectric layer on the substrate;
Forming a cap layer on the dielectric layer; removing a portion of the cap layer and a portion of the dielectric layer to form an opening to expose a portion of the substrate; forming a metal layer on the cap layer to fill the opening. Forming; increasing the CMP process window comprising the steps of performing a CMP process to remove a portion of the metal layer outside the opening until the cap layer is exposed. 2. The method of claim 1, wherein the cap layer comprises silicon nitride. 3. The method of claim 1, wherein the cap layer comprises silicon oxynitride (SiO _x N _y ). 4. The thickness of the cap layer is about 500 to 100.
2. The method of claim 1, wherein the thickness is 0 Angstroms. 5. The method according to claim 1, wherein the dielectric layer comprises BPSG. 6. The method according to claim 1, wherein the metal layer is made of tungsten.
The described method. 7. Provided is a substrate having a plurality of transistors;
Forming a first dielectric layer on the substrate and between the transistors;
Forming a second dielectric layer on the first dielectric layer and on the transistor; forming a cap layer harder than the dielectric layer on the second dielectric layer; opening to expose a portion of the substrate Partially removing the cap layer, the second dielectric layer, and the first dielectric layer to form a metal layer on the cap layer and in the opening; and performing a CMP process until the cap layer is exposed. A method for increasing the process window of CMP consisting of each step. 8. The method according to claim 7, wherein the first dielectric layer comprises BPSG. 9. The method of claim 7, wherein the second dielectric layer comprises TEOS oxide. 10. The method of claim 7, wherein the cap layer comprises silicon nitride. 11. The method according to claim 7, wherein the cap layer is made of silicon oxynitride (SiO _x N _y ). 12. The thickness of the cap layer is about 500 to 10
8. The method of claim 7, wherein the thickness is 00 Angstroms. 13. The method of claim 7, wherein the metal layer comprises tungsten. 14. The method of claim 7, wherein the step of forming a metal layer on the cap layer comprises the step of forming a conformal adhesive layer on the cap layer and in the opening.