JP2001319489A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that the operation speed is difficult to increase for a conventional semiconductor memory while suppressing the area increase of a core part. SOLUTION: A row decoder(RDC) 12 is arranged in each sub-array 11 in a core part 10. Wirings (M2) 13 are arranged along each word line WL on each sub-array 11. The wirings 13 are connected to the word lines WL. A bit line selector(BLS) 14 for selecting a bit line is provided between adjacent sub- arrays 11. A column decoder(CDC) 15 is provided near the bit line selector 14. The bit lines of each sub-array 11 are connected to a main bit line MBL and the main bit line MBL is connected to a sense amplifier arranged in a peripheral circuit region 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device mounted, for example, with a logic circuit, and more particularly to a semiconductor memory device using a three-layer metal wiring technique.

[0002]

2. Description of the Related Art FIG. 8 schematically shows a configuration of a 4 Mb macro in a conventional nonvolatile semiconductor memory device. This nonvolatile semiconductor memory device has, for example, 32 subarrays (SBA) 1. Each sub-array 1 has a storage capacity of, for example, 16 KB (16 × 8 = 128 Kb), and includes a bit line BL formed of a first-layer metal wiring (M1).
And the word line WL, and the bit line BL and the word line W
A memory cell (not shown) formed of, for example, a flash EEPROM selected by L is arranged. Bit line B
A sense amplifier (S / A) and a column sub-decoder (CSD) are provided between two sub-arrays 1 adjacent in the L direction.
C) are provided, and two column decoder regions 2 in which the sub-arrays 1 are arranged are provided.
Bit line 1 is selected.

Further, a double word line decoding method is adopted for selecting a word line WL. That is, a row sub-decoder (RSDC) 3 is provided between two sub-arrays 1 adjacent in the word line WL direction, and the row sub-decoder 3 is shared by the two sub-arrays 1. The row sub-decoder 3 selects a word line of the sub-array 1. Furthermore, 4 adjacent to the word line WL direction
Row main decoder (RM)
DC) 4 is arranged. This row main decoder 4
Is connected to a row main decode line 5 composed of a second layer metal wiring (M2). This row main decoder 4
The required row sub-decoder 3 is selected by the row main decode line 5.

A peripheral circuit area 6 is provided adjacent to the plurality of sub-arrays 1. This peripheral circuit area 6
Is provided with a column main decoder (not shown). The column main decoders are connected to column main decode lines 7 made of, for example, a third-layer metal wiring (M3). These column main decode lines 7 are connected to the respective column decoder regions 2. A required column sub-decoder is selected by the column main decoder and the column main decode line 7.

FIG. 9 shows a circuit example of the above-mentioned double word line decoding system, and the same parts as those in FIG. 8 are denoted by the same reference numerals. As shown in FIG. 9, one row main decoder 4
Are connected to a plurality of row sub-decoders 3.
These row sub-decoders 3 are constituted by CMOS transfer gates 3a formed of, for example, complementary MOS transistors. The input terminal of each transfer gate 3a is connected to the block decoder 8, and the output terminal is connected to each word line WL.

In the above configuration, a signal is output from the row main decoder 4 according to the address signal, and a plurality of row sub-decoders 3 are selected. At the same time, a signal is output from one of the block decoders 8, and one required word line WL is selected.

[0007]

Incidentally, the nonvolatile semiconductor memory device is required to operate at high speed. Therefore, when data is written to or read from a memory cell, it is important to change the bit line potential and the word line potential at high speed. In particular,
The word line is generally constituted by a polycide wiring. Since the polycide wiring has a higher resistance value than the metal wiring, by shortening the length of the word line, the wiring resistance is reduced and high-speed operation becomes possible. Therefore, as shown in FIG. 8, the memory cell array is divided into many sub-arrays 1 and the bit lines BL and word lines WL in the sub-array 1 are divided.
The length has been shortened.

However, as shown in FIG. 8, a column decoder region 2 is provided in each subarray 1, a row subdecoder 3 is provided for two subarrays 1, and a row main decoder is provided for four subarrays 1. 4 are provided. Therefore, when the number of sub-arrays 1 increases, the number of the column decoder regions 2, the row sub-decoders 3, and the row main decoders 4 increases, and the area of the core unit 9 increases.

Here, the area of the row main decoder 4 is A
The area of the main and row sub-decoders 3 is Asub, the area of the memory cell array when not divided is A0, and the area of the dead space generated when divided into a plurality of sub-arrays is A.
d Assuming that the area of the core for one array is Acore, the area Acore of the core when the memory cell array is not divided is as follows.

[0010] Also, when the memory cell array is divided into two, the area of the core part Acore is expressed by the following equation.

Acore = Amain + 2 × Asub + A0 / 2 × 2 + Ad × 1 = Amain + 2Asub + A0 + Ad In general, the relationship between the required core area and the division number N of the memory cell array is as follows.

Acore = Amain + N × Asub + A0 + Ad × (N−1) Thus, it can be seen that as the number of divisions N increases, the area of the core increases.

The CMOS transfer gate 3a constituting the row sub-decoder 3 has a large on-resistance. Therefore, the voltage waveform of the word line becomes dull, which hinders a high-speed read operation.

FIG. 10 shows a row main decoder 4.
Is schematically shown. This row main decoder 4
In accordance with an address signal of a power supply voltage level supplied from an address buffer 6a provided in the peripheral circuit region 6, voltages corresponding to various operation modes of the nonvolatile semiconductor memory device are supplied to the word lines. Therefore, the level shifter 4 is provided between the AND circuits 4a and 4b constituting the decode circuit.
c and 4d are provided. The level shifter 4c converts a power supply voltage level signal supplied from the AND circuit 4a into a high voltage used for reading and writing operations, and the level shifter 4d converts it into a negative voltage for erasing. As described above, since the row main decoder 4 includes the level shifters 4c and 4d in addition to the decode circuit, the address buffer 6a
It takes time from when a signal is supplied from to until the output level is determined.

In addition, in the row main decoder 4, the AND circuit 4a is constituted by low voltage transistors because the input signal is at the power supply voltage level, and the level shifters 4c, 4d and the AND circuit 4b are supplied with a high voltage. , High-voltage transistors. When a plurality of transistors having different breakdown voltages are formed as described above, it is necessary to increase an element isolation region for separating these transistors. Therefore, the row main decoder 4
Has a problem that the occupied area of the device increases.

Further, since the sense amplifiers are arranged in each subarray, these sense amplifiers are
Must be selected via the sense amplifier decoder provided in the first column and the long column main decode line 7. Therefore, it takes time to decode the sense amplifier, and it has been difficult to speed up the read operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device capable of suppressing an increase in the area of a core portion and operating at high speed. It is intended to provide.

[0018]

According to the present invention, there is provided a semiconductor memory device having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the bit lines and the word lines to solve the above-mentioned problems. A plurality of memory cell arrays, a word line selection circuit provided in each of the memory cell arrays and selecting the word line, a first bit line selection circuit provided in each of the memory cell arrays and selecting the bit line, Shared by multiple memory cell arrays,
A second bit line selection circuit for selecting a bit line selected by the first bit line selection circuit; and a sense amplifier connected to the second bit line selection circuit for detecting a potential of the bit line. The word line is connected to a second-layer metal line at the same potential as the word line via a first-layer metal line having one end connected to the word-line selection circuit; The selection circuit is constituted by a logic circuit composed of complementary MOS transistors having one kind of gate oxide film thickness.

Further, the semiconductor memory device of the present invention comprises a plurality of memory cell arrays each having a plurality of first bit lines and word lines, and a plurality of memory cells connected to the first bit lines and the word lines. A word line selection circuit provided in each of the memory cell arrays and selecting the word line; a first bit line selection circuit provided in each of the memory cell arrays and selecting the first bit line; A plurality of second bit lines shared by the cell array and connected to the first bit line selected by the first bit line selection circuit; and a pair of second bit lines adjacent to the plurality of second bit lines. A second bit line selection circuit for selecting a bit line, and first and second input terminals. Data read from the memory cell is supplied to the first input terminal. of A sense amplifier to which a constant current source is supplied to the input terminal; and a pair of second bit lines selected by the second bit line selection circuit at the first input terminal of the sense amplifier when reading data. A second bit line connected to a first bit line is connected, and a first bit of a pair of second bit lines selected by the second bit line selection circuit is connected to the second input terminal. A switch circuit for connecting a second bit line to which no line is connected.

Further, a semiconductor memory device according to the present invention includes a core portion and a peripheral circuit region adjacent to the core portion,
A plurality of memory cell arrays each having a plurality of first bit lines, word lines, and a plurality of memory cells connected to the first bit lines and the word lines; and the core unit is provided in each of the memory cell arrays. A word line selection circuit that selects a word line; a first bit line selection circuit that is provided in each of the memory cell arrays, and selects the first bit line; A plurality of second bit lines to which the first bit line selected by the bit line selection circuit is connected, and the peripheral circuit region includes a pair of second bit lines adjacent to the plurality of second bit lines. A second bit line selection circuit for selecting a bit line, and first and second input terminals, wherein the first input terminal is supplied with data read from the memory cell,
A sense amplifier to which a constant current source is supplied to the second input terminal;
Of the pair of second bit lines selected by the second bit line selection circuit is connected to a second bit line to which a first bit line is connected, and the second input terminal is connected to the second input terminal. A second bit line to which the first bit line is not connected among the pair of second bit lines selected by the second bit line selection circuit;
And a switch circuit for connecting the bit lines.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A and 1B schematically show the configuration of a 4Mb macro according to the semiconductor memory device of the present invention. In this semiconductor memory device, the core unit 10 has, for example, eight sub-arrays (SBAs) 11. Each sub-array 11 has, for example, 64 KB (64 × 8 = 512 K).
b) the first-level metal wiring (M1)
, And a memory cell MC (not shown) formed of, for example, a flash EEPROM selected by the bit line BL and the word line WL.

Two row decoders (RDC) 12 are arranged between the two sub-arrays 11 adjacent to each other in the word line WL direction so as to correspond to each sub-array 11. These row decoders 12 select the word lines WL according to signals supplied from the peripheral circuit area 16.
At the same time, the row decoder 12 supplies a required voltage supplied from the peripheral circuit region 16 to the word line WL when reading, writing, and erasing data. That is, for example, 5 V is supplied from the peripheral circuit area 16 when reading data, 10 V is supplied when writing data, and -7 V is supplied when erasing data.

Further, on each of the sub-arrays 11, a wiring 13 composed of, for example, a second-layer metal wiring (M2) is arranged along each word line WL, and this wiring 13 is connected to the corresponding word line WL. Details of the wiring 13 will be described later.

A bit line selector (BLS) 14 for selecting the bit line BL is provided between the sub arrays 11 adjacent to each other in the bit line BL direction. A column decoder (CDC) adjacent to the bit line selector 14
15 are provided. The column decoder 15 is arranged between two sub-arrays 11 adjacent in the word line WL direction. The bit line selector 14 is selectively driven by the column decoder 15.

The selection of the bit line BL employs a double bit line decoding method. Therefore, on the plurality of sub-arrays 11 arranged in the direction of the bit line BL, a plurality of main bit lines MBL made of, for example, a third-layer metal wiring (M3) are arranged. These main bit lines M
As described later, the bit line BL of each sub-array 11 is connected to BL. These main bit lines MBL are connected to a sense amplifier via a main bit line selector (not shown) arranged in the peripheral circuit region 16. The transfer of the write data to the memory cell and the transfer of the data read from the memory cell are performed by these main bit lines MBL.
And using the bit line BL.

FIG. 2 schematically shows the configuration of one sub-array 11 and peripheral circuit area 16 of FIG. In the peripheral circuit area 16, a main bit line selector 21, a main bit line decoder (MBDC) 23 for driving the main bit line selector 21, a switch circuit 24 for selectively connecting the main bit line MBL to the sense amplifier 22, A switch decoder (SWDC) 25 for controlling the operation of the switch circuit 24 is provided.

FIGS. 3A, 3B and 3C show the relationship between the word line WL and the wiring 13. FIG. In FIG. 3A, for example, an N-type well 32 is provided in a P-type substrate 31.
Are formed, and a P-type well 33 is formed in the well 32. In the well 33, a plurality of memory cells (not shown) made of the EEPROM are formed.

In the substrate 31, for example, an N-type well 34 is formed adjacent to one end of the well 32, and, for example, an N-type well 35 is formed adjacent to the other end of the well 32. I have.

In the well 34, a P-channel MOS transistor 36 constituting the row decoder 12 is formed. In addition, an N ⁺ diffusion layer is formed in the well 34, and a voltage VSW is supplied to the N ⁺ diffusion layer. This voltage VSW is the same as the voltage supplied to the word line WL when reading, writing, and erasing data.

The row decoder 12 is formed by, for example, a CMOS logic circuit. Therefore, although not shown, a P-type well in which an N-channel MOS transistor is formed is also formed in the substrate 31.

In the well 35, a P ⁺ diffusion layer and an N ⁺ diffusion layer are formed, and a protection diode 37 is formed by the P ⁺ diffusion layer and the N ⁺ diffusion layer. Further, a voltage VSW is supplied to the N ⁺ diffusion layer.

Above the substrate 31, a word line WL connected to a control gate of a memory cell is arranged.
The word line WL has a polycide structure, and the wiring 13 is disposed above the word line WL. Both ends of the wiring 13 and a plurality of intermediate portions are connected to a word line WL via a first-layer metal wiring M1. Therefore, the word line WL and the wiring 13 become conductive. With such a configuration, the resistance of the word line WL can be reduced.

FIG. 3B shows a connection structure of the word line WL, the first-layer metal wiring M1, and the wiring 13. As described above, by connecting the word line WL and the wiring 13 via the first-layer metal wiring M1, the aspect ratio of the contact hole can be reduced as compared with the case where the word line WL is connected only by the wiring 13. Thus, the wiring 13 and the word line WL can be reliably connected.

However, when a contact hole for connecting the wiring 13 composed of the second-layer metal wiring M2 to the first-layer metal wiring M1 is formed by etching, excessive plasma at the time of etching destroys the gate oxide film of the memory cell. There is a risk of being done. To avoid this problem, FIG.
As shown in (a), one end of the word line WL is connected to the P-decoder constituting the row decoder 12 via a first-layer metal wiring M1.
It is connected to the P ⁺ diffusion layer of the channel MOS transistor 36. Further, the other end of the word line WL is connected to a P ⁺ diffusion layer constituting the protection diode 37 via a first-layer metal wiring M1.

FIG. 3C shows the structure of the protection diode 37. A plurality of P ⁺ diffusion layers are formed in the well 35, and the first-layer metal wiring M1 connected to each word line is connected to each of the P ⁺ diffusion layers.

With such a configuration, when forming a contact hole exposing the first layer metal wiring M1 by etching, excess plasma can be released to the wells 34 and 35, so that destruction of the gate oxide film is prevented. Can be prevented. Therefore, variations in the performance of the memory cells can be prevented.

The well 34 and the well 35 have the same structure, and a protection diode 37 formed in the well 35 is formed.
Can be formed in the same step as the step of forming the row decoder 36. Therefore, an increase in the number of manufacturing steps can be prevented.

FIG. 4 shows a schematic configuration of the row decoder 12, and the same parts as those in FIG. 3 are denoted by the same reference numerals. In the present invention, the row decoder 12 is constituted only by a CMOS logic circuit. That is, in the case of this embodiment, the row decoder 12 is constituted by AND circuits 41 and 42. These AND circuits 41 and 42 are connected to a plurality of wirings 43 connected to the peripheral circuit area 16.

FIG. 5A shows an example of the AND circuit 41. The AND circuit 41 includes a NAND circuit 41a and an inverter circuit 41b.

FIG. 5B shows an example of the NAND circuit 41a, and FIG. 5C shows an example of the inverter circuit 41b.

Further, as shown in FIG.
6 is provided with a voltage generator 44 for supplying a voltage corresponding to various operation modes of the memory cell to the row decoder 12. The voltage generator 44 has first and second paths 45 and 46 connected to an address buffer 52, and the output voltages of the first and second paths 46 and 47 are selectively switched by a switch circuit 48. It is configured to be output.

The first path 46 has a high-level shifter 49 and a low-level shifter 50 connected in series, and the second path 47 is composed of only the high-level shifter 51. The high-level shifters 49 and 51 are supplied with the voltage VSW and the ground voltage as the power supply, and the low-level shifter 50 is supplied with the voltage VSW and the low voltage VL at the time of erasing as the power supply. The voltage VSW is 5 V at the time of reading and 1 at the time of writing.
0V. The low voltage VL is 0 V at the time of reading and writing, and is -7 V at the time of erasing. The output terminal of the low-level shifter 50 and the output terminal of the high-level shifter 51 are connected to a switch circuit 52. The switch circuit 52 is supplied with a control signal CS, and the output voltage of the low-level shifter 50 or the output voltage of the high-level shifter 51 is selected according to the control signal CS.

The operation of the voltage generator 44 in the above configuration will be described. For example, the low potential VL is 0 V when reading and writing data. The output voltage of one of the high-level shifters 49 and 51 is the ground voltage (0 V). Therefore, at the time of the read operation, both of the first and second paths 45 and 46 can be used. However, when using the first route 45,
Since both the high-level shifter 49 and the low-level shifter 50 operate to convert the level, it takes time to determine the level of the output voltage. Therefore, at the time of the read operation, the switch circuit 48 selects the output voltage of the high-level shifter 51 on the second path 46 according to the control signal CS. By controlling in this manner, a required voltage can be output at high speed.

On the other hand, during an erasing operation other than the reading and writing operations, a negative potential is required. For this reason, the switch circuit 48 selects the output voltage of the low-level shifter 50 on the first path 45 according to the control signal CS. Generally, a high-speed operation is not required for selecting a memory cell during an erase operation as compared with a read operation. For this reason, speed does not matter.

In general, a high-speed operation is not required during a write operation as compared with a read operation. Therefore, either one of the first and second paths 45 and 46 may be selected by the switch circuit 48. However, in consideration of high-speed operation, it is better to select the output voltage of the high-level shifter 51.

Thus, the voltage selected by the switch circuit 48 is supplied to the row decoder 12 via the wiring 43.

As described above, the row decoder 12 is
By using only the S logic circuit, the conventional C
High-speed operation is possible as compared with the case where a MOS transfer gate is included.

Further, by arranging the voltage generating circuit 44 composed of the high breakdown voltage transistor and the low breakdown voltage transistor having different oxide film thicknesses in the peripheral circuit region 16 distant from the row decoder, the row decoder 12 can be constituted only by the high breakdown voltage transistor. Can be configured. That is, the row decoder 12 can be constituted by a transistor having one kind of oxide film thickness. When a plurality of transistors having different oxide film thicknesses are formed, an element isolation region for separating these transistors becomes large, and the row decoder 12 becomes large.
However, in this embodiment, the area occupied by the row decoder 12 can be reduced.

FIG. 6 shows a read circuit according to the double bit line system of the present invention, and specifically shows the circuits shown in FIGS. 6, FIG. 1 and FIG.
The same reference numerals are given to the same parts as.

The bit lines BL of each sub-array 11 are connected to the main bit lines MBL1, MBL via a bit line selector 14.
L2. Main bit lines MBL1, MBL
BL2 is connected to a switch circuit 24 via a main bit line selector 21 for selecting a pair of adjacent main bit lines from a plurality of main bit lines. The switch circuit 24 includes switch elements 24a, 24b, 24
c, 24d. This switch circuit 2
4 connects one of the main bit lines MBL1 and MBL2 to one input terminal IN1 of the sense amplifier 22. A reference current source 61 is connected to the other input terminal of the sense amplifier 22.

As shown in FIG.
a and 24d are on and the switch elements 24b and 24c are off, the main bit line MBL1 is connected to the sense amplifier 2
2, the main bit line MBL2 and the reference current source 61 are connected to the other input terminal IN2. Therefore, the potential of the bit line BL connected to the main bit line MBL1 is detected by the sense amplifier 22.

When the switch elements 24a and 24d are off and the switch elements 24b and 24c are on, the main bit line MBL2 is connected to one input terminal IN1 of the sense amplifier 22 and the other input terminal IN2 is connected to the main bit line. The line MBL1 is connected to the reference current source 61. Therefore, the bit line BL connected to the main bit line MBL2
Is detected by the sense amplifier 22.

As described above, a main bit line to which the selected bit line BL is not connected (hereinafter, referred to as an unselected main bit line) is connected to the other input terminal IN2 of the sense amplifier 22. Therefore, the capacitance of the unselected main bit line can be added to the other input terminal IN2 of the sense amplifier 22. Therefore, imbalance between both input terminals IN1 and IN2 of the sense amplifier 22 can be prevented, and the data reading operation can be sped up without being affected by power supply noise.

FIG. 7 shows a modification of FIG.
6 are given the same reference numerals, and only different parts will be described.

In the circuit shown in FIG. 7, bit line selectors 14 of adjacent sub-arrays 11 are arranged adjacent to each other. In such a configuration, the transistors constituting the two bit line selectors 14 can be formed in the same well 71. Therefore, the area of the well for forming the plurality of bit line selectors 14 can be reduced.

According to the above embodiment, the sense amplifiers 22 are not arranged in each sub-array 11, but are arranged in the peripheral circuit region 16. For this reason, it is not necessary to provide the same number of sense amplifiers as the number of the sub-arrays 11, so that the area of the core can be prevented from increasing.

The sense amplifier 22 is connected to the peripheral circuit area 1
6, the time required for decoding by the sense amplifier can be reduced, and high-speed operation is possible.

Further, a non-selected main bit line is connected to the other input terminal of the sense amplifier 22. For this reason,
An imbalance in capacitance at the input terminal of the sense amplifier 22 can be eliminated, and a high-speed read operation can be performed.

Further, since the row decoder 12 is constituted only by a CMOS logic circuit, the selection of a word line can be performed at a higher speed than in the case where a conventional CMOS transfer gate is included.

A voltage generator 44 for generating various voltages to be supplied to the word lines is provided in the peripheral circuit area 16. For this reason, the row decoder 12 can be constituted by a transistor having one kind of oxide film thickness. Therefore, the configuration of the row decoder 12 can be simplified, and the area occupied by the row decoder can be reduced.

In the above embodiment, the case where the present invention is applied to a nonvolatile semiconductor memory device has been described. However, the present invention is not limited to this and can be applied to other semiconductor memory devices.

The present invention is not limited to a semiconductor memory device mixed with a logic circuit, but can be applied to a general-purpose semiconductor memory device.

In addition, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0065]

As described in detail above, according to the present invention,
It is possible to provide a semiconductor memory device capable of suppressing an increase in the area of the core portion and operating at high speed.

[Brief description of the drawings]

FIG. 1A is a schematic configuration diagram showing one embodiment of the present invention, and FIG. 1B is a cross-sectional view showing a partial configuration of FIG. 1A.

FIG. 2 is a schematic configuration diagram showing a part of the configuration of FIG. 1;

3A is a schematic configuration diagram showing a configuration of the word line WL, FIG. 3B is a cross-sectional view showing a part of FIG. 3A, and FIG. The top view showing a part of (a).

FIG. 4 is a circuit diagram showing a row decoder of the present invention.

FIG. 5 is a circuit diagram showing an example of a row decoder shown in FIG. 4;

FIG. 6 is a circuit diagram showing an example of a read circuit using a double bit line method of the present invention.

FIG. 7 is a circuit diagram showing another example of FIG. 6;

FIG. 8 is a schematic configuration diagram showing a conventional semiconductor memory device.

FIG. 9 is a circuit diagram showing a conventional row decoder.

FIG. 10 is a circuit diagram showing a part of FIG. 9;

[Explanation of symbols]

 10 core part, 11 subarray, 12 row decoder, 13 wiring (M2), 14 bit line selector, 15 column decoder, 16 peripheral circuit area, 21 main bit line selector, 22 sense amplifier, 23: Main bit line decoder, 24: Switch circuit, 25: Switch decoder, 44: Voltage generator, 61: Reference current source, 71: Well, BL: Bit line, WL: Word line, MBL, MBL1, MBL2: Main Bit line.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 (72) Inventor Yoshinori Takano 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Corporation In the Microelectronics Center (72) Inventor Shigeru Atsumi 1-term, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba Microelectronics Center, Inc. ER22 GA01 JA53 KA18 LA03 LA05 LA10 MA06 MA16 ZA12

Claims (9)

[Claims] 1. A plurality of memory cell arrays each having a plurality of bit lines and word lines, and a plurality of memory cells connected to these bit lines and word lines, and provided in each of the memory cell arrays to select the word line. A word line selection circuit, a first bit line selection circuit provided in each of the memory cell arrays and selecting the bit line, shared by the plurality of memory cell arrays and selected by the first bit line selection circuit A second bit line selection circuit that selects a bit line; and a sense amplifier that is connected to the second bit line selection circuit and that detects a potential of the bit line. A first layer metal wiring connected to a word line selection circuit, connected to a second layer metal wiring having the same potential as the word line, And a logic circuit comprising a complementary MOS transistor having one kind of gate oxide film thickness. 2. The semiconductor memory device according to claim 1, wherein the other end of said first-layer metal wiring is connected to a protection diode. 3. The semiconductor memory device according to claim 2, wherein said protection diode is formed in a well having the same configuration as said word line selection circuit. 4. The semiconductor memory device according to claim 1, wherein said first bit line selection circuit is constituted by a logic circuit comprising complementary MOS transistors having one kind of gate oxide film thickness. . 5. A plurality of memory cell arrays each having a plurality of first bit lines and word lines, and a plurality of memory cells connected to the first bit lines and the word lines; A word line selection circuit that selects the word line; a first bit line selection circuit that is provided in each of the memory cell arrays and selects the first bit line; A plurality of second bit lines shared by the memory cell array and connected to the first bit lines selected by the first bit line selection circuit; and a pair of second bit lines adjacent to the plurality of second bit lines. A second bit line selection circuit for selecting two bit lines; and a first and a second input terminal, wherein data read from the memory cell is supplied to the first input terminal. 2
And a pair of second bit lines selected by the second bit line selection circuit at the first input terminal of the sense amplifier when reading data. A second bit line to which a first bit line is connected is connected, and the second input terminal is connected to the second bit line.
And a switch circuit for connecting a second bit line of the pair of second bit lines selected by the bit line selection circuit to which the first bit line is not connected. . 6. The first bit line selection circuits of two memory cell arrays adjacent in the bit line direction among the first bit line selection circuits arranged in each of the memory cell arrays, are arranged adjacent to each other, 6. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed in the same well. 7. The semiconductor memory device according to claim 1, wherein said sense amplifier is arranged in a peripheral circuit region. 8. A semiconductor device comprising: a core portion; and a peripheral circuit region adjacent to the core portion, wherein each of the core portions is connected to a plurality of first bit lines, word lines, and the first bit lines and the word lines. A plurality of memory cell arrays each including a plurality of memory cells, a word line selection circuit provided in each of the memory cell arrays, and selecting the word line, and a first bit line provided in each of the memory cell arrays. A first bit line selection circuit, and a plurality of second bit lines shared by the plurality of memory cell arrays and connected to the first bit line selected by the first bit line selection circuit. The peripheral circuit region includes a second bit line selection circuit that selects a pair of adjacent second bit lines from the plurality of second bit lines, and a first and a second input terminals. The first The data read from the memory cell is supplied to the input terminal, and the second
And a pair of second bit lines selected by the second bit line selection circuit at the first input terminal of the sense amplifier when reading data. A second bit line to which a first bit line is connected is connected, and the second input terminal is connected to the second bit line.
And a switch circuit for connecting a second bit line to which the first bit line is not connected among a pair of second bit lines selected by the bit line selection circuit. 9. A plurality of memory cell arrays each having a plurality of first bit lines, word lines, and a plurality of memory cells connected to the first bit lines and the word lines, the first bit lines and the word lines being made of a first layer metal wiring, A word line selection circuit that is provided in each memory cell array, is configured by a complementary MOS transistor having one type of gate oxide film thickness, selects the word line, and is arranged along the word line; A second wiring made of a second-layer metal wiring connected to the word line via a first wiring made of a first-layer metal wiring connected to the word line selection circuit; and a second wiring provided in each of the memory cell arrays. A first bit line selection circuit for selecting the first bit line; and a plurality of memory cell arrays arranged along each of the first bit lines. A plurality of second bit line formed from a shared third layer metal wiring first bit line selected by the first bit line selection circuit is connected to,
A second bit line selection circuit for selecting a pair of adjacent second bit lines from the plurality of second bit lines; a first and a second input terminal; A sense amplifier to which data read from a memory cell is supplied and a constant current source supplied to the second input terminal; and a second bit to the first input terminal of the sense amplifier when reading data. A second bit line to which a first bit line is connected among a pair of second bit lines selected by the line selection circuit is connected, and the second input terminal is connected to the second bit line by the second bit line selection circuit. And a switch circuit for connecting a second bit line of the selected pair of second bit lines to which the first bit line is not connected.