JP2001318625A - Optoelectronic device, method for manufacturing optoelectronic device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optoelectronic device which efficiently shields against light entering a channel region without decreasing the opening rate of pixels. SOLUTION: A liquid crystal device 300 as an optoelectronic device has a liquid crystal layer 50 held between a TFT array substrate 301 and a counter substrate 302. On the substrate 10 of the TFT array substrate 301, a recess 10a with a light shielding layer 11a on its surface is formed in the position corresponding to the channel region 1a'. Further, a recess 12a corresponding to the recess 10a is formed in a first interlayer insulating film 12, and the channel region 1a' is disposed in the recess 12a so that the light shielding layer 11a three-dimensionally surrounds the channel region 1a'. Thus, the light entering and returning obliquely is prevented by the light-shielding layer formed on the side faces of the recess.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of electro-optical devices, and more particularly, to an electro-optical device in which a light shielding layer is formed in a concave portion formed on a substrate surface.

[0002]

2. Description of the Related Art An electro-optical device, for example, a liquid crystal device has a structure in which a liquid crystal layer is sandwiched between a counter substrate and an array substrate. A plurality of scanning lines and data lines are arranged to intersect on a surface of the array substrate in contact with the liquid crystal layer, and a switching element and a pixel electrode are arranged at each intersection. On the other hand, a counter electrode is disposed on a surface of the counter substrate that is in contact with the liquid crystal layer.

[0003] In a projection type display device such as a projector using such a liquid crystal device, light is usually emitted from the counter substrate side of the liquid crystal device. In order to prevent this light from entering the channel region of the switching element formed on the array substrate and causing a light leakage current, a structure is provided in which a light shielding layer is provided on the opposite substrate. However, it is known that even if a light-blocking layer is provided on the counter substrate, part of the incident light passes through the liquid crystal device and then returns to the liquid crystal device as return light. This return light causes a photocurrent in the semiconductor film of the thin film transistor, which has a problem of adversely affecting the characteristics of the switching element. In order to prevent such return light from being incident on the switching element, a method has been considered in which a concave portion is provided in a portion corresponding to the switching element region of the substrate constituting the array substrate, and a light shielding layer is embedded in the concave portion. . In such a liquid crystal device, since the surface of the substrate in which the light-shielding layer is embedded is flattened, the switching element can be formed on the almost flattened surface.

[0004]

However, in such a liquid crystal device, the return light incident on the substrate in a direction substantially perpendicular to the substrate can be shielded by a light shielding layer embedded in the substrate, but is oblique to the substrate. In order to shield the incident return light, the area of the light shielding layer occupying the plane of the substrate must be sufficiently large. For this reason, there is a problem that the pixel aperture ratio is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is an object of the present invention to provide an electro-optical device and a projection display device for blocking return light obliquely incident without reducing the pixel aperture ratio. It is an object.

[0006]

According to an aspect of the present invention, there is provided an electro-optical device comprising: a substrate provided with a first concave portion having a surface covered with a light-shielding layer; A switching element having an insulating film provided on the surface of the substrate and having a second concave portion in a region corresponding to the first concave portion, and a channel region disposed on the second concave portion of the insulating film. And characterized in that:

According to such a configuration of the present invention, when the substrate is viewed from the thickness direction of the substrate, the channel region is arranged in the concave portion whose surface is covered with the light shielding layer. Are configured to surround the channel region. As a result, the return light obliquely incident is shielded by the light shielding layer formed on the side surface of the concave portion. Therefore, without increasing the area of the light-shielding layer occupying the plane of the substrate, it is possible to eliminate the influence of the incidence of the return light on the characteristics of the switching element, and to improve the pixel aperture ratio.

Here, the case where the insulating film having the second concave portion is used without changing the area of the light-shielding layer occupying the plane of the substrate and the case where the insulating film whose surface is flattened as in the prior art are used. Compare with In this case, the incident angle at which the return light obliquely incident can be shielded when the insulating film having the second concave portion is used, as compared with the case where the insulating film whose surface is flattened is used. Range becomes wider. That is, in the case where the influence of the incidence of the return light on the characteristics of the switching element is to be made equal, the present invention can improve the pixel aperture ratio as compared with the related art.

Further, the channel region is arranged below the uppermost part of the light shielding layer. According to such a configuration, the channel region is three-dimensionally
It will be located in the first recess. Thereby, the incidence of the return light to the channel region formed of the semiconductor layer can be completely blocked by the light-blocking layer, and the malfunction of the switching element due to the light incidence to the channel region can be prevented.

[0010] A surface and a side surface of the channel region on the substrate side are covered with the light shielding layer. By arranging the light-blocking layer so as to surround the channel region with respect to the channel region in this manner, incidence of return light to the channel region formed of the semiconductor layer can be completely blocked by the light-blocking layer. This has the effect that malfunction of the switching element due to light incident on the region can be prevented.

[0011] The semiconductor device may further include a gate electrode constituting the switching element, wherein the gate electrode is arranged below an uppermost portion of the light shielding layer. According to such a configuration, the gate electrode is three-dimensionally provided with the first electrode.
Will be arranged in the concave portion. Thus, it is possible to completely block the return light from being incident on the gate electrode made of a semiconductor layer, for example, by the light-shielding layer, thereby preventing a malfunction of the switching element due to the incident light on the gate electrode. Has an effect.

[0012] The semiconductor device may further include a gate electrode constituting the switching element, wherein a surface and a side surface of the gate electrode on the substrate side are covered with the light shielding layer. According to such a configuration, with respect to the gate electrode,
The light-shielding layer is arranged so as to surround the gate electrode. Thus, it is possible to completely block the return light from being incident on the gate electrode made of a semiconductor layer, for example, by the light-shielding layer, thereby preventing a malfunction of the switching element due to the incident light on the gate electrode. Has an effect.

Further, the gate electrode is made of polysilicon. According to such a configuration, there is an effect that a malfunction of a switching element having a gate electrode made of polysilicon, which may malfunction due to light incidence, can be prevented.

Further, the first concave portion has a tapered side surface whose opening is widened toward the substrate surface. With such a configuration, there is an effect that, when the light shielding layer is formed, the light shielding layer can be easily formed on the side surface of the first concave portion. Here, for example, when compared with the case where the side surface of the first concave portion is substantially perpendicular to the substrate surface or the case where the side surface of the first concave portion has a tapered shape in which the opening becomes narrower toward the substrate surface, In some cases, it is difficult to form a light shielding layer on the side surface.
For this reason, when the first concave portion has a structure having a tapered side surface in which the opening is widened toward the substrate surface, it is easier to form the light shielding film on the side surface in manufacturing.

An electronic apparatus according to the present invention includes a light source, an electro-optical device that receives light emitted from the light source, and performs modulation corresponding to image information, and a projection that projects light modulated by the electro-optical device. And an electro-optical device comprising the above-described electro-optical device. With such a configuration, the pixel aperture ratio is improved, and an electro-optical device that does not affect the characteristics of the switching element due to the incidence of return light is used, so that a high-performance electronic device can be obtained. Having.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. (Structure of Electro-Optical Device) The structure of a liquid crystal device as an electro-optical device according to the present invention will be described with reference to FIGS. 1 to 3 and FIG. FIG. 1 is an equivalent circuit diagram of various elements, wiring, and the like in a plurality of pixels formed in a matrix forming an image display area of a liquid crystal device. FIG.
FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which scanning lines, pixel electrodes, light-shielding layers, and the like are formed. FIG. 3 is a sectional view taken along line AA ′ of FIG. 2, and FIG. 8 is a sectional view taken along line BB ′ of FIG. In each of the drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

In FIG. 1, a plurality of pixels arranged in a matrix forming an image display area of a liquid crystal device according to the present embodiment have TFTs for controlling a pixel electrode 9a.
The data line 6a to which an image signal is supplied is electrically connected to the source of the TFT 30. Image signals S1 and S written to data line 6a
2,..., Sn may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. Also, the TFT 30
The scanning line 3a is electrically connected to the gate of the scanning line 3a, and the scanning signal G is pulsed to the scanning line 3a at a predetermined timing.
, Gm are applied line-sequentially in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30 as a switching element for a certain period, the image signals S1 and S1 supplied from the data line 6a.
2, ..., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are held for a certain period between the counter electrodes (described later) formed on the counter substrate (described later). . The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode.

In FIG. 2, a plurality of transparent pixel electrodes 9a are arranged in a matrix on a TFT array substrate of a liquid crystal device.
(The outline is indicated by the narrow dotted line 9a ')
Are provided, and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a is electrically connected to a later-described source region of the semiconductor layer 1a made of a polysilicon film or the like (outlined by a wide dotted line portion) via the contact hole 5, and the pixel electrode 9a is electrically connected to a later-described drain region in the semiconductor layer 1a via the contact hole 8. In addition, the scanning line 3a is arranged so as to face the channel region 1a '(the hatched region on the lower right in the figure) of the semiconductor layer 1a.
Functions as a gate electrode. Thus, the scanning line 3a
The TFTs 30 are provided at the intersections of the data lines 6a with the scanning lines 3a facing each other as gate electrodes in the channel region 1a '.

The capacitance line 3b has a main line portion extending substantially linearly along the scanning line 3a, and a protruding portion protruding forward (upward in the figure) along the data line 6a from a portion intersecting the data line 6a. And The capacitor line 3b is arranged with a storage capacitor electrode 1f described later in the semiconductor layer 1a via a gate insulating film 2 described later to form a storage capacitor.

Further, as shown in FIG.
A first light shielding layer 11a is provided corresponding to a '.

Next, as shown in the cross-sectional view of FIG. 3, in the liquid crystal device 300, a liquid crystal layer 50, which is an example of an electro-optical material, is sandwiched between a TFT array substrate 301 and a counter substrate 302 which are arranged to face each other. Structure. The liquid crystal layer 50
For example, it is composed of a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. Further, the substrate 10 forming a part of the TFT array substrate 301 is formed of, for example, a quartz substrate, and the substrate 20 forming a part of the counter substrate 302 is formed of, for example, a glass substrate or a quartz substrate.

The TFT array substrate 301 has a pixel electrode 9
a, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided on the upper side. The pixel electrode 9a is made of, for example, ITO (Indium Tin Oxid).
e) It consists of a transparent conductive thin film such as a film. Also, the alignment film 16
Is composed of an organic thin film such as a polyimide thin film. T
The FT array substrate 301 is provided with a pixel switching TFT 30 for controlling the switching of each pixel electrode 9a at a position adjacent to each pixel electrode 9a.

The structure of the TFT array substrate 301 will be described below. In the TFT array substrate 301, as shown in FIG. 3, a first interlayer insulating film 12 is formed on a quartz substrate 10. The quartz substrate 10 has a light shielding layer 1 at a position corresponding to a channel region 1a 'of a semiconductor layer 1a to be described later.
A recess 10a as a first recess covered by 1a is formed. The concave portion 10a has a depth of 700 to 800 nm, and the light shielding layer 11a is formed with a thickness of 200 nm. The recess 10a has a tapered shape in which the opening widens toward the substrate surface, and the taper angle is 1
10 to 115 °. The first interlayer insulating film formed on the substrate having such a recess 10a has a recess 10a
Is formed at a position corresponding to the second concave portion 12a as a second concave portion having substantially the same depth and taper angle as the concave portion 10a. Further, the first interlayer insulating film 12 is formed by forming the semiconductor layer 1 a constituting the pixel switching TFT 30 into the first light shielding layer 1.
1a to provide electrical insulation.

The semiconductor layer 1a of the TFT 30 is formed on the first interlayer insulating film. The semiconductor layer 1a has an LDD in which a low-concentration source region 1b and a low-concentration drain region 1c are arranged with a channel region 1a 'interposed therebetween, and further, a high-concentration source region 1d and a low-concentration region 1c are arranged with these regions interposed therebetween. (Lightly Doped Drain) structure.
The semiconductor layer 1a has a storage capacitor electrode 1f connected to the semiconductor layer portion in the LDD structure region. The channel region 1a 'is in a state of being arranged in a cross-sectional region obtained by cutting the groove 10a along a plane parallel to the substrate surface.

First interlayer insulating film 12 including semiconductor layer 1a
A gate insulating film 2 is formed thereon. The scanning lines 3a and the capacitance lines 3b are formed on the gate insulating film 2. Part of the scanning line is formed in the channel region 1 of the semiconductor layer 1a.
It is arranged at a position corresponding to a ′ and functions as a gate electrode. The capacitance line 3b and the capacitance electrode 1f form a storage capacitance via the gate insulating film 2.

Further, a second interlayer insulating film 4 is formed so as to cover the scanning lines 3a and the capacitance lines 3b, and the data lines 6a are arranged on the second interlayer insulating film 4. The data line 6a is electrically connected to the high-concentration source region 1d of the semiconductor layer 1a via a contact hole 5 formed in the gate insulating film 2 and the second interlayer insulating film 4. Further, the data line 6a
The pixel electrode 9a is arranged on the third interlayer insulating film 7 including. The pixel electrode 9a is connected to the high-concentration drain region 1 of the semiconductor layer 1a through a contact hole 8 formed in the gate insulating film 2, the second interlayer insulating film 4, and the third interlayer insulating film 7.
e.

On the other hand, as shown in FIG. 3, the counter substrate 302 is, for example, a counter electrode (common electrode) 21 on an entire surface of a glass substrate 20 and an alignment film on which a predetermined alignment process such as a rubbing process is performed. 22 are provided sequentially. Further, a second light-shielding film 23 called a black mask or a black matrix may be provided in the non-opening region of each pixel. Therefore, incident light does not enter the channel region 1a ', the source-side LDD region 1b, and the drain-side LDD region 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the side of the counter substrate 302. Further, the third light-shielding film 23 has a function of improving contrast, preventing color mixture of color materials when a color filter is formed, and the like.
The counter electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

As described above, the quartz substrate 10 is provided with the concave portion 10a as a first concave portion whose surface is covered with the light shielding layer 11a at a position corresponding to the channel region 1a 'of the semiconductor layer 1a to be described later. Is formed. This recess 10a
A cross-sectional structure when the cross section in the vicinity is viewed from a cross section different from FIG. 3 will be described with reference to FIG.

As shown in FIG. 8, the light-shielding layer 11a is formed on the surface of the concave portion 10a provided on the quartz substrate 10, that is, on the bottom surface and the side surface. The first interlayer insulating film 1 substantially follows the shape of the concave portion 10a.
2 also has a recess 12a. Channel area 1
a 'is in a state of being arranged in the concave portion 12a.
The light shielding layer 11a is made of, for example, T, which is an opaque refractory metal.
It is composed of a simple metal, an alloy, a metal silicide or the like containing at least one of i, Cr, W, Ta, Mo and Pb.

In the present invention, the second interlayer insulating film 12
By arranging the channel region 1a 'in the concave portion 12a formed in the above, the light shielding layer 11a three-dimensionally surrounds the channel region 1a'. Thereby, the return light that is obliquely incident is efficiently shielded by the light shielding layer formed on the side surface of the first concave portion. Therefore, channel region 1
The return light does not enter the channel region 1a ', and malfunction of the pixel switching TFT 30 due to generation of a photocurrent due to the incidence of the return light on the channel region 1a' can be prevented.

Here, without changing the area of the light-shielding layer 11a occupying the plane of the substrate, an insulating film having a concave portion is used as the first interlayer insulating film, and an insulating film whose surface is flattened as in the prior art. The case where a film is used is compared with FIG.
FIG. 9 is a cross-sectional view illustrating a positional relationship between the channel region 1a ′ and the light-shielding layer 11a. FIG. 9A shows the structure of the present embodiment, in which the first interlayer insulating film 12 having the recess 12a formed therein is formed.
This is the structure when using. FIG. 9B shows a conventional structure, in which a light shielding layer 1 is provided in a concave portion 10 a provided on a substrate 10.
This is a structure in which a first interlayer insulating film 12 having a flat surface 1a and a flat surface is used. 9 (a) and 9
In (b), the light shielding layer 11a and the channel region 1a '
Are the same, that is, the respective formation regions occupying the substrate plane are set to be the same.

In each of FIGS. 9A and 9B, the light-shielding layer 11a is provided at the upper end portions C and D of the channel region 1a '.
In FIG. 9A, the range in which the return light can be blocked by α is α,
In FIG. 9B, it is β. As shown in the figure, it can be seen that the light shielding range α in the present embodiment is wider than the conventional light shielding range β. That is, it is understood that the present embodiment has a wider range of incident angles at which obliquely incident return light can be shielded than the conventional structure. Therefore, when trying to equalize the influence of the incidence of return light on the characteristics of the switching element, in the conventional structure, it is necessary to increase the formation region of the light shielding layer, and the pixel aperture ratio is reduced. On the other hand, in the present invention, it is possible to eliminate the influence of the return light on the TFT characteristics while improving the pixel aperture ratio.

(Method of Manufacturing Electro-Optical Device) A process of manufacturing the array substrate of the electro-optical device will be described with reference to FIGS. FIGS. 4 to 7 show TFTs in each step.
FIG. 4 is a process diagram showing each layer on the array substrate side, corresponding to the AA ′ cross section in FIG. 2 as in FIG. 3.

First, as shown in FIG. 4A, a light shielding layer 11 on a quartz substrate 10 having a thickness of, for example, 1.1 mm is formed.
A recess 10a is formed by etching at a position corresponding to a. The concave portion has a tapered side surface whose opening is widened toward the substrate surface. The depth of this recess is 700
nm and the taper angle γ are 110 °.

Next, as shown in FIG.
The light-shielding film 11 is formed on the surface of the substrate 10 including the surface a. The light-shielding film 11 is obtained by, for example, depositing molybdenum to a thickness of about 200 nm by a sputtering method. At this time, since the concave portion 11a has a tapered shape in which the opening is widened toward the substrate surface, the light shielding film 11 is efficiently formed also on the side surface of the concave portion 11a. The material of the light-shielding film 11 is not limited to this embodiment, and any material may be used as long as the material is stable at the maximum temperature of the thermal process of the device to be manufactured. For example, a high melting point metal such as tungsten or tantalum or polycrystalline silicon, or a silicide such as tungsten silicide or molybdenum silicide is used as a preferable material.
Method, an electron beam heating evaporation method, or the like can be used.

Next, as shown in FIG.
The light-shielding film 11 on the surface of the substrate 10 other than the light-shielding film formed on the surface a is removed by polishing. As a method of planarization by polishing, for example, a CMP (chemical mechanical polishing) method can be used. Thereby, the surface of the concave portion 10a,
That is, the light-shielding layer 11a having a thickness of 200 nm is formed on the side and bottom portions.

Next, as shown in FIG.
a, TEOS (tetra-ethyl-ortho-silicate) gas, TEB (tetra-ethyl-borate) gas, and TMOP (tetra-methyl-oxy-phos) on the substrate 10 containing NSG, PSG, BSG, BPS
A first interlayer insulating film 12 made of a silicate glass film such as G, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the first interlayer insulating film 12 is, for example, about 500 to 2
000 nm. The first interlayer insulating film 12 has a substrate 1
A concave portion 12a is formed corresponding to the concave portion 10a formed on the zero. The recess 12a has substantially the same depth and taper angle as the recess 10a.

Next, as shown in FIG. 4 (5), a temperature of about 450 to 550.degree. C., preferably about 50.degree.
In a relatively low temperature environment of 0 ° C, the flow rate is about 400-600cc
An amorphous silicon film is formed by low-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like at a pressure of about 20 to 40 Pa. Thereafter, the polysilicon film 1 is subjected to an annealing treatment in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably for 4 to 6 hours, so that the polysilicon film 1 has a thickness of about 50 to 200 nm, preferably Is solid-phase grown to a thickness of about 100 nm. As a method for solid phase growth, RTA (Rapid
Thermal annealing may be used, or laser annealing using an excimer laser or the like may be used.

At this time, when an n-channel type pixel switching TFT 30 is formed as the pixel switching TFT 30 shown in FIG.
V such as b (antimony), As (arsenic), and P (phosphorus)
A group element dopant may be slightly doped by ion implantation or the like. Also, the pixel switching TFT 30 is set to p
In the case of a channel type, a dopant of a group III element such as B (boron), Ga (gallium), or In (indium) may be slightly doped by ion implantation or the like.
The polysilicon film 1 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by a low-pressure CVD method or the like to make the polysilicon film once amorphous (amorphized), and then recrystallize by annealing or the like.

Next, as shown in FIG. 4 (6), a semiconductor layer 1a having a predetermined pattern including the first storage capacitor electrode 1f as shown in FIG. 2 is formed by a photolithography process, an etching process and the like.

Next, as shown in FIG.
On the first interlayer insulating film 12 containing a, an insulating film made of a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a thickness of about 100 nm by a low pressure CVD method or the like to obtain the gate insulating film 2. Here, as the gate insulating film 2, a thermally oxidized silicon film is provided on the semiconductor layer by thermal oxidation, and a silicon nitride film or the like is further provided to cover the thermally oxidized silicon film to form a gate insulating film having a two-layer structure. You may.
Alternatively, a gate insulating film consisting of only a thermal silicon oxide film may be formed by thermal oxidation.

Next, as shown in FIG. 5 (8), a resist layer 50 is formed by a photolithography process, an etching process, or the like.
0 is the semiconductor layer 1 excluding the portion serving as the first storage capacitor electrode 1f
a. Thereafter, for example, P ions are doped at a dose of about 3 × 10 ¹² / cm ² to form the first storage capacitor electrode 1f.
To lower the resistance.

Next, as shown in FIG. 5 (9), after removing the resist layer 500, a polysilicon film 3 is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to form the polysilicon film 3. Is made conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. The thickness of the polysilicon film 3 is about 100 to 50.
Deposit to a thickness of 0 nm, preferably about 300 nm.

Next, as shown in FIG. 5 (10), a scanning line 3 having a predetermined pattern as shown in FIG. 2 is formed by a photolithography process using a resist mask, an etching process and the like.
A capacitor line 3b is formed together with a. The scanning line 3a and the capacitance line 3b may be formed of a metal alloy film such as a high melting point metal or a metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like. Here, the gate electrode forming a part of the scanning line 3a is formed so as to be located inside the concave portion 12a.

Next, as shown in FIG. 5 (11), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel type TFT having an LDD structure, first, the low concentration source region 1b and the lightly doped source region 1b are formed in the semiconductor layer 1a. In order to form the low-concentration drain region 1c, the scanning line 3a (gate electrode) is used as a mask, and a dopant of a group V element such as P is used at a low concentration (for example, P ions are used at a concentration of 1 to 3 × 10 ¹³ / cm ² ). (Dose amount). Thereby, the semiconductor layer 1 under the scanning line 3a
a becomes the channel region 1a '. The resistance of the capacitance line 3b and the scanning line 3a is further reduced by the doping of the impurity.

Next, as shown in FIG. 5 (12), in order to form the high-concentration source region 1d and the high-concentration drain region 1e constituting the pixel switching TFT 30, a mask wider than the scanning line 3a is used. After forming the resist layer 600 on the scanning line 3a, similarly, a dopant of a group V element such as P is applied at a high concentration (for example, P ions are added to 1 to 3 × 10
Doping at a dose of ¹⁵ / cm ² ). This allows
A low-concentration source region 1b and a low-concentration drain region 1c in which impurity ions are lightly doped are disposed on both sides of the channel region 1a '. Drain region 1e
Are formed to form an LDD structure. Note that, for example, a TFT having an offset structure may be used without performing low-concentration doping, or a self-aligned TFT may be formed by an ion implantation technique using P ions or the like using the scanning line 3a as a mask. The resistance of the capacitance line 3b and the scanning line 3a is further reduced by the doping of the impurity.

Next, as shown in FIG. 6 (13), after the resist layer 600 is removed, the normal pressure or low pressure CVD method, TEOS gas or the like is formed on the capacitance line 3b, the scanning line 3a, and the gate insulating film 2. Using NSG, PSG (phosphorus silicate glass), BSG (boron silicate glass),
A second interlayer insulating film 4 made of a silicate glass film such as BPSG (boron phosphorus silicate glass), a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm. If the thickness of the second interlayer insulating film 4 is 500 nm or more, the data line 6a
Also, the parasitic capacitance between the scanning lines 3a does not cause much or little problem. Thereafter, an annealing process at about 1000 ° C. is performed for about 20 minutes to activate the high-concentration source region 1d and the high-concentration drain region 1e.

Next, as shown in FIG. 6 (14), a contact hole 5 for the data line 6a is formed in the second interlayer insulating film.

Next, as shown in FIG. 6 (15), a low-resistance metal such as Al or a metal silicide having a light-shielding property is formed as a metal film 6 on the second interlayer insulating film 4 by sputtering or the like. 100-500 nm thickness, preferably about 300
nm.

Next, as shown in FIG. 6 (16), a data line 6a is formed by a photolithography process, an etching process and the like. Thereby, data line 6a is electrically connected to high-concentration source region 1d through contact hole 5 formed in second interlayer insulating film 4.

Next, as shown in FIG. 7 (17), NSG, PSG, BSG, BSG are formed so as to cover the data lines 6a by using, for example, normal pressure or reduced pressure CVD or TEOS gas.
A third interlayer insulating film 7 made of a silicate glass film such as PSG, a silicon nitride film, a silicon oxide film, or the like is formed.
The thickness of the third interlayer insulating film 7 is preferably about 500 to 1500 nm.

Next, as shown in FIG. 7 (18), a contact hole 8 for electrically connecting the pixel electrode 9a and the high concentration drain region 1e is formed by reactive ion etching.
It is formed by dry etching such as reactive ion beam etching. Further, wet etching may be used to form a tapered shape.

Next, as shown in FIG. 7E, a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. Then, as shown in step (20), a pixel electrode 9a is formed by a photolithography step, an etching step, or the like.

Subsequently, a coating solution of a polyimide-based alignment film is applied onto the pixel electrode 9a, and then rubbed in a predetermined direction so as to have a predetermined pretilt angle, and the like, so that the alignment film 16 (FIG. 3) is formed. As a result, a TFT array substrate 301 is formed.

On the other hand, as for the counter substrate 302 shown in FIG. 3, the glass substrate 20 is first prepared. Next, the substrate 2
After, for example, metal chromium is sputtered on 0, the second light shielding film 23 and the frame light shielding film are formed through a photolithography process and an etching process. These light-shielding films may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist, in addition to a metal material such as Cr, Ni, or Al.

Next, a transparent conductive thin film of ITO or the like is formed on the entire surface of the substrate 20 by sputtering or the like to a thickness of about 50 to 200 nm.
To form a counter electrode 21. Furthermore, by applying a coating liquid of a polyimide-based alignment film on the entire surface of the counter electrode 21, by performing a rubbing treatment in a predetermined direction so as to have a predetermined pretilt angle, and the like.
An alignment film 22 (see FIG. 3) is formed. As a result, a counter substrate 302 is formed.

As described above, the TFT array substrate 301 on which each layer is formed and the counter substrate 302 are aligned with the alignment films 16 and 2.
2 are bonded together by a sealing material so as to face each other. Thereafter, a liquid crystal obtained by mixing a plurality of types of nematic liquid crystals is sucked into a space between the two substrates by vacuum suction or the like, and a liquid crystal layer 50 having a predetermined thickness is formed, thereby forming a liquid crystal device.

(Projection Display Apparatus) Next, an embodiment of a projection display apparatus including the liquid crystal device 300 described in detail above will be described with reference to FIG.

As shown in FIG. 12, the projection type display device 11
00, three liquid crystal display modules including the above-described liquid crystal device 300 are prepared, and RGB liquid crystal devices 962R,
FIG. 2 shows a schematic configuration diagram of an optical system of a projection type liquid crystal device used as 962G and 962B. Projection display device 110 of this example
The optical system 0 includes a light source device 920 and a uniform illumination optical system 9.
23 are employed. The projection display apparatus further includes a color separation optical system 924 as a color separation unit that separates the light beam W emitted from the uniform illumination optical system 923 into red (R), green (G), and blue (B). Three light valves 925R, 9 as modulation means for modulating each color light flux R, G, B
25G, 925B, a color synthesizing prism 910 as a color synthesizing means for re-synthesizing the modulated color light flux, and a projection lens unit 906 as a projection means for enlarging and projecting the synthesized light flux onto the surface of the projection surface 100. Have. Further, a light guide system 927 for guiding the blue light flux B to the corresponding light valve 925B is also provided.

The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931. The two lens plates 921 and 922 are arranged so as to be orthogonal to each other with the reflection mirror 931 interposed therebetween. Uniform illumination optical system 923
The two lens plates 921 and 922 each include a plurality of rectangular lenses arranged in a matrix. The light beam emitted from the light source device 920 is transmitted to the first lens plate 92.
The light is split into a plurality of partial light beams by one rectangular lens.
Then, these partial light beams are divided into three light valves 925R and 925R by the rectangular lens of the second lens plate 922.
Superimposed around 5G and 925B. Therefore, by using the uniform illumination optical system 923, even when the light source device 920 has an uneven illuminance distribution in the cross section of the emitted light beam, the three light valves 925R, 925G, and 925B are used.
Can be illuminated with uniform illumination light.

Each color separation optical system 924 includes a blue-green reflecting dichroic mirror 941, a green reflecting dichroic mirror 942, and a reflecting mirror 943. First, in the blue-green reflecting dichroic mirror 941, the blue light beam B and the green light beam G included in the light beam W are reflected at right angles, and head toward the green reflecting dichroic mirror 942. The red light beam R passes through the mirror 941, is reflected at a right angle by the rear reflection mirror 943, and is emitted from the emission unit 944 of the red light beam R to the prism unit 910 side.

Next, a green reflecting dichroic mirror 942
Of the blue and green light fluxes B and G reflected by the blue-green reflection dichroic mirror 941,
Only the green light beam G is reflected at a right angle, and is emitted from the emission unit 945 of the green light beam G to the color combining optical system side. The blue light flux B that has passed through the green reflection dichroic mirror 942 is emitted from the emission section 946 of the blue light flux B to the light guide system 927 side. In this example, the emission portions 944 and 94 of the color light beams in the color separation optical system 924 from the emission portion of the light beam W of the uniform illumination optical element.
The distances to 5,946 are set to be substantially equal.

The red and green luminous flux R of the color separation optical system 924
Condensing lenses 951 and 952 are arranged on the emission sides of the G emission sections 944 and 945, respectively. Therefore,
The red and green luminous fluxes R and G emitted from the respective emission sections are incident on these condenser lenses 951 and 952 and are parallelized.

The red and green luminous fluxes R and G thus collimated enter the light valves 925R and 925G and are modulated to add image information corresponding to each color light. That is, the switching of these liquid crystal devices is controlled by driving means (not shown) in accordance with the image information, whereby each color light passing therethrough is modulated. On the other hand, the blue light flux B is guided to the corresponding light valve 925B via the light guide system 927, where it is similarly modulated according to image information. In addition, the light valve 925 of this example
R, 925G, and 925B further include a liquid crystal light further including incident-side polarization means 960R, 960G, and 960B, emission-side polarization means 961R, 961G, and 961B, and liquid crystal devices 962R, 962G, and 962B disposed therebetween. It is a valve.

The light guide system 927 is a light emitting section 94 for the blue light beam B.
6, a condenser lens 954 disposed on the exit side, an incident-side reflection mirror 971, an exit-side reflection mirror 972, an intermediate lens 973 disposed between these reflection mirrors, and disposed on the front side of the light valve 925B. And a condenser lens 953. The blue light flux B emitted from the condenser lens 946 is transmitted through the light guide system 927 to the liquid crystal device 962B.
And modulated. The optical path length of each color beam, that is,
Each liquid crystal device 962R, 962G, 9
The distance to 62B is the longest for the blue luminous flux B, and therefore the loss of light quantity of the blue luminous flux is the largest. However, by interposing the light guide system 927, the loss of light amount can be suppressed.

Each light valve 925R, 925G, 92
The color light fluxes R, G, and B modulated through 5B are incident on a color combining prism 910, where they are combined. The light combined by the color combining prism 910 is enlarged and projected on the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.

In this example, the liquid crystal devices 962R, 962G,
Since a light-blocking layer is provided on the lower side of the TFT in the 962B, the light reflected and projected by the projection optical system in the liquid crystal projector based on the light projected from the liquid crystal devices 962R, 962G, and 962B passes. Even if reflected light from the surface of the TFT array substrate, part of the projected light that passes through the projection optical system after being emitted from another liquid crystal device, etc., is incident on the TFT array substrate side as return light, the pixel electrode It is possible to sufficiently shield the channel of the switching TFT from light.

As described above, since a liquid crystal device that efficiently blocks return light that is incident obliquely efficiently while maintaining a high pixel aperture ratio is used, a high-performance projection display device can be obtained.

In the above-described embodiment, the light shielding layer is arranged only in the region corresponding to the channel region. However, for example, a structure in which the light shielding layer is arranged corresponding to the channel region, the source region and the drain region may be adopted. In this case, it is possible to prevent the malfunction of the TFT due to the return light entering the channel region and to prevent the deterioration of the TFT due to the return light entering the aus region and the drain region.

In the above-described embodiment, the concave portion 10a whose surface is covered with the light-shielding layer has a tapered shape. However, as shown in FIG. The shape may be substantially perpendicular to the substrate. In this case, the first interlayer insulating film 112 includes
A recess 112a having a side surface substantially perpendicular to the substrate is formed along the shape of the recess 110a. The channel region 1a 'is arranged in the concave portion 112a.
Needless to say, even with such a structure, the same effect as in the above-described embodiment can be obtained. Note that FIG.
Corresponds to a cross-sectional view taken along line BB 'in FIG. 2, and in FIG. 10, the same reference numerals are given to the same components as those in the above-described embodiment.

In the above-described embodiment, the channel region 1 is formed in the recess 12 a formed in the first interlayer insulating film 12.
Although the structure is such that a ′ is arranged, the channel region 1a ′ may be arranged in the recess 10a without forming the first interlayer insulating film 12, as shown in FIG. In this case, a material having a high insulating property may be used as the light-shielding layer 211a covering the surface of the concave portion 10a.

In the above-described embodiment, as shown in FIG. 3, in the cross-sectional shape, the position of the surface of the channel region 1a 'is higher than the position of the surface of the substrate excluding the groove 10a formed in the substrate 10. It has become. However, as shown in FIG. 13, the position of the surface of the channel region 1a 'is equal to or lower than the position of the surface of the substrate excluding the groove 10a formed on the substrate 10, in other words, the groove 10a
It may be configured such that the channel region 1a 'is disposed in the region a. As a result, it is possible to completely block the return light from entering the channel region 1a 'of the semiconductor layer,
A malfunction of the TFT due to light incident on the channel region can be prevented. In order to obtain such a structure, the depth of the groove, the material and thickness of the first interlayer insulating film 12, the thickness of the semiconductor layer, and the like may be appropriately adjusted.

Further, in the above-described embodiment, the position of the surface of the channel region 1a 'and the position of the surface of the gate electrode 3a are different from those of the substrate 10 in the sectional shape as shown in FIG.
Is higher than the position on the substrate surface excluding the groove 10a formed in the substrate. However, as shown in FIG. 14, the position of the surface of the channel region 1a ′ and the position of the surface of the gate electrode 3a are equal to or lower than the position of the substrate surface excluding the groove 10a formed in the substrate 10, in other words. ,
The channel region 1a 'and the gate electrode 3a are formed in the groove 10a.
May be configured to be placed. As a result, it is possible to completely block the return light from entering the channel region 1a 'of the semiconductor layer, and to prevent the TFT from malfunctioning due to the light entering the channel region. Further, the incidence of return light on the gate electrode 3a can be completely blocked. Thus, when polysilicon is used as the material of the gate electrode 3a, it is possible to prevent the TFT from being turned on due to light incident on the gate electrode and malfunctioning. In order to obtain such a structure, the depth of the groove, the material and thickness of the first interlayer insulating film 12, the thickness of the semiconductor layer, the material and thickness of the gate insulating film 2, the gate electrode 3a, and the like are appropriately adjusted. good.

In FIGS. 13 and 14, various films and electrodes formed after the step of forming the gate electrode are not shown.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wiring, and the like provided in a plurality of pixels in a matrix forming an image forming area in an embodiment of a liquid crystal device.

FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light shielding layer, and the like are formed in the embodiment of the liquid crystal device.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the embodiment of the liquid crystal device.

FIG. 5 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the embodiment of the liquid crystal device.

FIG. 6 is a process diagram (part 3) for sequentially illustrating the manufacturing process of the embodiment of the liquid crystal device.

FIG. 7 is a process view (part 4) for sequentially illustrating the manufacturing process of the embodiment of the liquid crystal device.

8 is a sectional view taken along the line B-B 'of FIG.

FIG. 9 is a cross-sectional view of the vicinity of a channel region for comparing a structure in the embodiment with a conventional structure.

FIG. 10 is a cross-sectional view near a channel region in another embodiment of a liquid crystal device.

FIG. 11 is a cross-sectional view near a channel region in still another embodiment of the liquid crystal device.

FIG. 12 is a configuration diagram of a projection display device using a liquid crystal device.

FIG. 13 is a cross-sectional view near a channel region in another embodiment of a liquid crystal device.

FIG. 14 is a cross-sectional view near a channel region in still another embodiment of the liquid crystal device.

[Explanation of symbols]

 1a semiconductor layer 1a 'channel region 10 quartz substrate 10a recess 11a first light-shielding layer 12 first interlayer insulating film 12a recess 30 TFT 300 liquid crystal device 906 projection lens unit 920 light source device 925R 925G, 925B… Light valve

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 626C F-term (Reference) 2H091 FA05X FA34Y FB08 FC02 FC26 FD04 FD21 GA13 LA03 LA11 LA12 MA07 2H092 JA25 JA29 JA38 JA42 JA44 JA46 JB13 JB23 JB32. BB01 CC02 DD02 DD03 DD12 DD13 DD14 DD21 EE09 EE45 FF02 FF03 FF09 FF23 FF32 GG02 GG13 GG25 GG32 GG47 HJ01 HJ04 HJ13 HJ23 HL03 HL05 HL07 HL23 HM14 HM15 NN03 NN04 NN23 NN23 NN23 NN22 NN23 NN23 NN23

Claims (8)

[Claims] 1. A first recess having a surface covered with a light-shielding layer,
A substrate provided on the surface of the substrate, an insulating film provided on the surface of the substrate including the light-shielding layer and having a second concave portion in a region corresponding to the first concave portion, and the second concave portion of the insulating film And a switching element having a channel region disposed thereon. 2. The device according to claim 1, wherein the channel region is disposed below an uppermost portion of the light shielding layer.
An electro-optical device according to claim 1. 3. The electro-optical device according to claim 1, wherein a surface and a side surface of the channel region on the substrate side are covered with the light shielding layer. 4. The electric device according to claim 1, further comprising a gate electrode forming the switching element, wherein the gate electrode is disposed below an uppermost portion of the light shielding layer. Optical device. 5. The semiconductor device according to claim 1, further comprising a gate electrode forming the switching element, wherein a surface and a side surface of the gate electrode on the substrate side are covered with the light shielding layer. Electro-optical device. 6. The electro-optical device according to claim 4, wherein the gate electrode is made of polysilicon. 7. The electro-optical device according to claim 1, wherein the first recess has a tapered side surface whose opening is widened toward the substrate surface. 8. A light source, and an electro-optical device that receives light emitted from the light source and performs modulation corresponding to image information,
An electronic apparatus comprising: a projection unit configured to project light modulated by the electro-optical device, wherein the electro-optical device includes the electro-optical device according to any one of claims 1 to 7. And electronic equipment.