|
US6782469B1
(en)
*
|
2000-09-29 |
2004-08-24 |
Intel Corporation |
Runtime critical load/data ordering
|
|
US6681317B1
(en)
*
|
2000-09-29 |
2004-01-20 |
Intel Corporation |
Method and apparatus to provide advanced load ordering
|
|
US7149878B1
(en)
*
|
2000-10-30 |
2006-12-12 |
Mips Technologies, Inc. |
Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
|
|
US6826681B2
(en)
*
|
2001-06-18 |
2004-11-30 |
Mips Technologies, Inc. |
Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
|
|
US7107439B2
(en)
*
|
2001-08-10 |
2006-09-12 |
Mips Technologies, Inc. |
System and method of controlling software decompression through exceptions
|
|
US6970895B2
(en)
*
|
2001-10-01 |
2005-11-29 |
Koninklijke Philips Electronics N.V. |
Programmable delay indexed data path register file for array processing
|
|
US6941449B2
(en)
*
|
2002-03-04 |
2005-09-06 |
Hewlett-Packard Development Company, L.P. |
Method and apparatus for performing critical tasks using speculative operations
|
|
US20030177312A1
(en)
*
|
2002-03-15 |
2003-09-18 |
Aravindh Baktha |
Controlling a store data forwarding mechanism during execution of a load operation
|
|
WO2003091972A1
(en)
*
|
2002-04-26 |
2003-11-06 |
Telefonaktiebolaget Lm Ericsson |
Memory access register file
|
|
US7062636B2
(en)
*
|
2002-09-19 |
2006-06-13 |
Intel Corporation |
Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operation
|
|
US7080231B2
(en)
*
|
2002-10-18 |
2006-07-18 |
Sun Microsystems, Inc. |
Processor with tagging buffer and methods for avoiding memory collisions
|
|
US7325228B1
(en)
*
|
2003-04-30 |
2008-01-29 |
Hewlett-Packard Development Company, L.P. |
Data speculation across a procedure call using an advanced load address table
|
|
US7103880B1
(en)
*
|
2003-04-30 |
2006-09-05 |
Hewlett-Packard Development Company, L.P. |
Floating-point data speculation across a procedure call using an advanced load address table
|
|
CN100390755C
(zh)
*
|
2003-10-14 |
2008-05-28 |
中国科学院计算技术研究所 |
含有显式高速缓冲存储器的计算机微体系结构
|
|
US20080052687A1
(en)
*
|
2003-11-03 |
2008-02-28 |
Agustin Gonzales-Tuchmann |
Development environment for data transformation applications
|
|
CN1306401C
(zh)
*
|
2004-03-19 |
2007-03-21 |
中国科学院计算技术研究所 |
一种支持有向有环图的微调度方法
|
|
US7757237B2
(en)
*
|
2004-06-16 |
2010-07-13 |
Hewlett-Packard Development Company, L.P. |
Synchronization of threads in a multithreaded computer program
|
|
US7366956B2
(en)
*
|
2004-06-16 |
2008-04-29 |
Hewlett-Packard Development Company, L.P. |
Detecting data races in multithreaded computer programs
|
|
US20050283770A1
(en)
*
|
2004-06-18 |
2005-12-22 |
Karp Alan H |
Detecting memory address bounds violations
|
|
US7324106B1
(en)
*
|
2004-07-27 |
2008-01-29 |
Nvidia Corporation |
Translation of register-combiner state into shader microcode
|
|
US20060242390A1
(en)
*
|
2005-04-26 |
2006-10-26 |
Intel Corporation |
Advanced load address table buffer
|
|
US8266413B2
(en)
|
2006-03-14 |
2012-09-11 |
The Board Of Trustees Of The University Of Illinois |
Processor architecture for multipass processing of instructions downstream of a stalled instruction
|
|
US8127117B2
(en)
*
|
2006-05-10 |
2012-02-28 |
Qualcomm Incorporated |
Method and system to combine corresponding half word units from multiple register units within a microprocessor
|
|
JP5289688B2
(ja)
*
|
2006-07-05 |
2013-09-11 |
ルネサスエレクトロニクス株式会社 |
プロセッサシステム及びプロセッサシステムを動作させるオペレーティングシステムプログラムの処理方法
|
|
US8417922B2
(en)
*
|
2006-08-02 |
2013-04-09 |
Qualcomm Incorporated |
Method and system to combine multiple register units within a microprocessor
|
|
CN104823168B
(zh)
|
2012-06-15 |
2018-11-09 |
英特尔公司 |
用于实现从由加载存储重新排序和优化导致的推测性转发遗漏预测/错误中恢复的方法和系统
|
|
CN107748673B
(zh)
|
2012-06-15 |
2022-03-25 |
英特尔公司 |
包括虚拟加载存储队列的处理器和系统
|
|
CN104583957B
(zh)
|
2012-06-15 |
2018-08-10 |
英特尔公司 |
具有无消歧乱序加载存储队列的重新排序的推测性指令序列
|
|
EP2862062B1
(en)
|
2012-06-15 |
2024-03-06 |
Intel Corporation |
A virtual load store queue having a dynamic dispatch window with a distributed structure
|
|
EP2862069A4
(en)
|
2012-06-15 |
2016-12-28 |
Soft Machines Inc |
INSTRUCTION DEFINITION FOR IMPLEMENTING LOAD MEMORY TRANSFER AND OPTIMIZATION
|
|
TWI646422B
(zh)
|
2012-06-15 |
2019-01-01 |
英特爾股份有限公司 |
在處理器中之免消歧義失序載入／儲存佇列方法、微處理器、和非暫態性電腦可讀取儲存媒體
|
|
CN111723921B
(zh)
*
|
2019-03-22 |
2024-05-14 |
中科寒武纪科技股份有限公司 |
人工智能计算装置及相关产品
|
|
CN112052041B
(zh)
*
|
2020-10-10 |
2022-03-11 |
乐鑫信息科技（上海）股份有限公司 |
更新寄存器的方法
|
|
JP2023133850A
(ja)
*
|
2022-03-14 |
2023-09-27 |
富士通株式会社 |
演算処理装置および演算処理方法
|