JP2001312405A5 - - Google Patents

Download PDF

Info

Publication number
JP2001312405A5
JP2001312405A5 JP2001112660A JP2001112660A JP2001312405A5 JP 2001312405 A5 JP2001312405 A5 JP 2001312405A5 JP 2001112660 A JP2001112660 A JP 2001112660A JP 2001112660 A JP2001112660 A JP 2001112660A JP 2001312405 A5 JP2001312405 A5 JP 2001312405A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001112660A
Other versions
JP2001312405A (ja
Filing date
Publication date
Priority claimed from US09/559,508 external-priority patent/US6631460B1/en
Application filed filed Critical
Publication of JP2001312405A publication Critical patent/JP2001312405A/ja
Publication of JP2001312405A5 publication Critical patent/JP2001312405A5/ja
Withdrawn legal-status Critical Current

Links

JP2001112660A 2000-04-27 2001-04-11 コンピュータ・システム Withdrawn JP2001312405A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/559508 2000-04-27
US09/559,508 US6631460B1 (en) 2000-04-27 2000-04-27 Advanced load address table entry invalidation based on register address wraparound

Publications (2)

Publication Number Publication Date
JP2001312405A JP2001312405A (ja) 2001-11-09
JP2001312405A5 true JP2001312405A5 (ja) 2008-05-29

Family

ID=24233848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001112660A Withdrawn JP2001312405A (ja) 2000-04-27 2001-04-11 コンピュータ・システム

Country Status (4)

Country Link
US (1) US6631460B1 (ja)
EP (1) EP1150202A3 (ja)
JP (1) JP2001312405A (ja)
CN (1) CN1184564C (ja)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6782469B1 (en) * 2000-09-29 2004-08-24 Intel Corporation Runtime critical load/data ordering
US6681317B1 (en) * 2000-09-29 2004-01-20 Intel Corporation Method and apparatus to provide advanced load ordering
US7149878B1 (en) * 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US6826681B2 (en) * 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US6970895B2 (en) * 2001-10-01 2005-11-29 Koninklijke Philips Electronics N.V. Programmable delay indexed data path register file for array processing
US6941449B2 (en) * 2002-03-04 2005-09-06 Hewlett-Packard Development Company, L.P. Method and apparatus for performing critical tasks using speculative operations
US20030177312A1 (en) * 2002-03-15 2003-09-18 Aravindh Baktha Controlling a store data forwarding mechanism during execution of a load operation
US20050166031A1 (en) * 2002-04-26 2005-07-28 Holmberg Anders P. Memory access register file
US7062636B2 (en) * 2002-09-19 2006-06-13 Intel Corporation Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operation
US7080231B2 (en) * 2002-10-18 2006-07-18 Sun Microsystems, Inc. Processor with tagging buffer and methods for avoiding memory collisions
US7325228B1 (en) * 2003-04-30 2008-01-29 Hewlett-Packard Development Company, L.P. Data speculation across a procedure call using an advanced load address table
US7103880B1 (en) * 2003-04-30 2006-09-05 Hewlett-Packard Development Company, L.P. Floating-point data speculation across a procedure call using an advanced load address table
CN100390755C (zh) * 2003-10-14 2008-05-28 中国科学院计算技术研究所 含有显式高速缓冲存储器的计算机微体系结构
US7743382B2 (en) * 2003-11-03 2010-06-22 Ramal Acquisition Corp. System for deadlock condition detection and correction by allowing a queue limit of a number of data tokens on the queue to increase
CN1306401C (zh) * 2004-03-19 2007-03-21 中国科学院计算技术研究所 一种支持有向有环图的微调度方法
US7366956B2 (en) * 2004-06-16 2008-04-29 Hewlett-Packard Development Company, L.P. Detecting data races in multithreaded computer programs
US7757237B2 (en) * 2004-06-16 2010-07-13 Hewlett-Packard Development Company, L.P. Synchronization of threads in a multithreaded computer program
US20050283770A1 (en) * 2004-06-18 2005-12-22 Karp Alan H Detecting memory address bounds violations
US7324106B1 (en) * 2004-07-27 2008-01-29 Nvidia Corporation Translation of register-combiner state into shader microcode
US20060242390A1 (en) * 2005-04-26 2006-10-26 Intel Corporation Advanced load address table buffer
US8266413B2 (en) 2006-03-14 2012-09-11 The Board Of Trustees Of The University Of Illinois Processor architecture for multipass processing of instructions downstream of a stalled instruction
US8127117B2 (en) * 2006-05-10 2012-02-28 Qualcomm Incorporated Method and system to combine corresponding half word units from multiple register units within a microprocessor
JP5289688B2 (ja) * 2006-07-05 2013-09-11 ルネサスエレクトロニクス株式会社 プロセッサシステム及びプロセッサシステムを動作させるオペレーティングシステムプログラムの処理方法
US8417922B2 (en) * 2006-08-02 2013-04-09 Qualcomm Incorporated Method and system to combine multiple register units within a microprocessor
KR101826399B1 (ko) * 2012-06-15 2018-02-06 인텔 코포레이션 Load store 재정렬 및 최적화를 구현하는 명령어 정의
CN107220032B (zh) 2012-06-15 2020-12-15 英特尔公司 无消歧乱序加载存储队列
WO2013188701A1 (en) 2012-06-15 2013-12-19 Soft Machines, Inc. A method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization
KR20170102576A (ko) 2012-06-15 2017-09-11 인텔 코포레이션 분산된 구조를 갖는 동적 디스패치 윈도우를 가지는 가상 load store 큐
EP2862061A4 (en) 2012-06-15 2016-12-21 Soft Machines Inc MEMORY PRECISION FOR VIRTUAL LOAD WITH DYNAMIC SHIPPING WINDOW WITH UNIFORM STRUCTURE
EP2862068B1 (en) 2012-06-15 2022-07-06 Intel Corporation Reordered speculative instruction sequences with a disambiguation-free out of order load store queue
CN111723921B (zh) * 2019-03-22 2024-05-14 中科寒武纪科技股份有限公司 人工智能计算装置及相关产品
CN112052041B (zh) 2020-10-10 2022-03-11 乐鑫信息科技（上海）股份有限公司 更新寄存器的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778219A (en) 1990-12-14 1998-07-07 Hewlett-Packard Company Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations
JP2786574B2 (ja) 1992-05-06 1998-08-13 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システムにおける順不同ロード動作の性能を改善する方法と装置
US5438677A (en) 1992-08-17 1995-08-01 Intel Corporation Mutual exclusion for computer system
US5421022A (en) 1993-06-17 1995-05-30 Digital Equipment Corporation Apparatus and method for speculatively executing instructions in a computer system
US5634023A (en) 1994-07-01 1997-05-27 Digital Equipment Corporation Software mechanism for accurately handling exceptions generated by speculatively scheduled instructions
US5799179A (en) 1995-01-24 1998-08-25 International Business Machines Corporation Handling of exceptions in speculative instructions
US5625835A (en) 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor
US5694577A (en) 1995-06-06 1997-12-02 Matsushita Electric Industrial Co., Ltd. Memory conflict buffer for achieving memory disambiguation in compile-time code schedule
US5903749A (en) 1996-07-02 1999-05-11 Institute For The Development Of Emerging Architecture, L.L.C. Method and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occurs
WO1998006038A1 (en) 1996-08-07 1998-02-12 Sun Microsystems, Inc. Architectural support for software pipelining of loops
US5941977A (en) 1997-06-25 1999-08-24 Sun Microsystems, Inc. Apparatus for handling register windows in an out-of-order processor
US6128728A (en) * 1997-08-01 2000-10-03 Micron Technology, Inc. Virtual shadow registers and virtual register windows
US5915117A (en) 1997-10-13 1999-06-22 Institute For The Development Of Emerging Architectures, L.L.C. Computer architecture for the deferral of exceptions on speculative instructions
AU1078099A (en) 1997-10-13 1999-05-03 Institute For The Development Of Emerging Architectures, Llc Method and apparatus for optimizing instruction execution
US6487630B2 (en) * 1999-02-26 2002-11-26 Intel Corporation Processor with register stack engine that dynamically spills/fills physical registers to backing store

Similar Documents

Publication Publication Date Title
BE2017C056I2 (ja)
BE2017C051I2 (ja)
BE2017C032I2 (ja)
BE2016C051I2 (ja)
BE2015C077I2 (ja)
BE2015C046I2 (ja)
BE2014C052I2 (ja)
BE2014C036I2 (ja)
BE2014C026I2 (ja)
BE2017C050I2 (ja)
BE2014C004I2 (ja)
BE2014C006I2 (ja)
FR12C0036I1 (ja)
BE2011C034I2 (ja)
BE2007C047I2 (ja)
JP2002190992A5 (ja)
AU2002307149A8 (ja)
JP2002180903A5 (ja)
JP2001346047A5 (ja)
BRPI0209186B1 (ja)
BE2016C021I2 (ja)
BE2014C008I2 (ja)
JP2001312405A5 (ja)
CH1379220H1 (ja)
BE2012C051I2 (ja)