JP2001308270A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001308270A JP2001308270A JP2000124148A JP2000124148A JP2001308270A JP 2001308270 A JP2001308270 A JP 2001308270A JP 2000124148 A JP2000124148 A JP 2000124148A JP 2000124148 A JP2000124148 A JP 2000124148A JP 2001308270 A JP2001308270 A JP 2001308270A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- polycrystalline silicon
- temperature coefficient
- resistor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、抵抗素子を含む半
導体装置に関する。The present invention relates to a semiconductor device including a resistance element.
【０００２】[0002]
【従来の技術】高速信号処理行う集積回路においては、
入出力部のインピーダンス整合を取ることは伝播効率を
よくするために重要なことであり、伝送ラインの特性イ
ンピーダンスに相当する抵抗値の抵抗器を挿入すること
が一般に行われる。2. Description of the Related Art In an integrated circuit that performs high-speed signal processing,
Matching the impedance of the input / output unit is important for improving the propagation efficiency, and a resistor having a resistance value corresponding to the characteristic impedance of the transmission line is generally inserted.
【０００３】この抵抗器の抵抗誤差は反射による損失を
抑制するために、高い精度が要求される。この用途で用
いられる抵抗器としては、多結晶シリコンの抵抗器が用
いられている。多結晶シリコンは、不純物のドープ量に
よって温度係数が異なることが知られており、温度係数
が０ppm/℃となるような１０20ｃｍ-3程度のドープ量と
して、抵抗器として用いる方法が考えられている。[0003] The resistance error of this resistor requires high precision in order to suppress the loss due to reflection. As a resistor used in this application, a resistor made of polycrystalline silicon is used. It is known that the temperature coefficient of polycrystalline silicon varies depending on the doping amount of impurities, and a method of using it as a resistor with a doping amount of about 10 20 cm −3 at which the temperature coefficient becomes 0 ppm / ° C. is considered. ing.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、通常多
結晶シリコン抵抗器は、例えば、バイポーラトランジス
タにおいては、npnトランジスタのベース引き出し部と
同時形成され、その不純物ドープ量はおよそ１０22ｃｍ
-3であるため、別途フォトリソグラフィ技術を用いて別
工程で行わなければならず、工程の追加が必要となる。However, in general, for example, in a bipolar transistor, a polycrystalline silicon resistor is formed at the same time as a base lead portion of an npn transistor, and its impurity doping amount is about 10 22 cm.
Since it is -3 , it must be performed in a separate process using a separate photolithography technique, and an additional process is required.
【０００５】本発明では、工程の追加をすることなく、
温度係数を実質的に持たない抵抗器を有する半導体装置
を提供することを目的とする。[0005] In the present invention, without adding a step,
An object of the present invention is to provide a semiconductor device having a resistor having substantially no temperature coefficient.
【０００６】[0006]
【課題を解決するための手段】本発明では、上記目的を
達成するために、半導体装置の構成として、第１の抵抗
値を有し、温度係数が正である第１の抵抗部分と、第１
の抵抗部分と直列に接続される、第２の抵抗値を有し、
温度係数が負である第２の抵抗部分と、を含み、第１の
抵抗値に対する第２の抵抗値の比と、第２の抵抗部分が
有する温度係数の絶対値に対する第１の抵抗部分が有す
る温度係数の絶対値の比とが実質的に等しくなるように
している。In order to achieve the above object, the present invention provides a semiconductor device having a first resistance portion having a first resistance value and a positive temperature coefficient; 1
Having a second resistance value connected in series with the resistance portion of
A second resistance portion having a negative temperature coefficient, wherein the ratio of the second resistance value to the first resistance value and the first resistance portion to the absolute value of the temperature coefficient of the second resistance portion are different. The ratio of the absolute values of the temperature coefficients is made substantially equal.
【０００７】[0007]
【発明の実施の形態】以下、図１を参照して本発明の第
１の実施形態について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIG.
【０００８】図１（ａ）は本発明の第１の実施形態を示
す平面図、図１（ｂ）は図１（ａ）におけるＡ−Ａ’断
面図である。FIG. 1A is a plan view showing a first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA ′ in FIG. 1A.
【０００９】図１において、半導体基板１上には、第１
の抵抗体としての多結晶シリコン膜２が形成されてい
る。この多結晶シリコン膜２は、例えば、ボロンが６×
１０15ions/cm2注入され、熱処理が施され、シート抵抗
が１００Ω／□となっている。多結晶シリコン膜２の形
状は、幅Ｗを５μm、コンタクト間の長さＬを２．５μ
m、厚さ３００nmの寸法にパターニングされ、その抵抗
値が５０Ωの抵抗体として用いられる。In FIG. 1, a first substrate is provided on a semiconductor substrate 1.
A polycrystalline silicon film 2 is formed as a resistor. This polycrystalline silicon film 2 is made of, for example, boron
10 15 ions / cm 2 are implanted, and a heat treatment is performed, so that the sheet resistance is 100 Ω / □. The shape of the polycrystalline silicon film 2 is such that the width W is 5 μm and the length L between contacts is 2.5 μm.
m, is patterned to have a thickness of 300 nm, and is used as a resistor having a resistance value of 50Ω.
【００１０】この多結晶シリコン膜２は、例えば、バイ
ポーラトランジスタを形成する製造工程において、図示
しないnpnトランジスタのベース引き出し部と同時に形
成することが可能である。The polycrystalline silicon film 2 can be formed at the same time as, for example, a base lead portion of an npn transistor (not shown) in a manufacturing process for forming a bipolar transistor.
【００１１】多結晶シリコン２は、例えばＣＶＤ法によ
り形成されるシリコン酸化膜３に覆われている。シリコ
ン酸化膜３における、第１の抵抗体２の端部に対応する
領域には、コンタクト孔４が形成されている。The polycrystalline silicon 2 is covered with a silicon oxide film 3 formed by, for example, a CVD method. A contact hole 4 is formed in a region of the silicon oxide film 3 corresponding to an end of the first resistor 2.
【００１２】コンタクト孔４内には、密着層としてのチ
タン膜５、バリアメタルとしての窒化チタン膜６が形成
されており、残りがタングステン膜７で埋め込まれてい
る。なお、チタン膜５と多結晶シリコン膜２とは、互い
に反応し、チタンシリサイドが形成される。In the contact hole 4, a titanium film 5 as an adhesion layer and a titanium nitride film 6 as a barrier metal are formed, and the rest is buried with a tungsten film 7. The titanium film 5 and the polycrystalline silicon film 2 react with each other to form titanium silicide.
【００１３】コンタクト孔４は、例えば、0.5μm×4.0
μmの大きさに形成されており、そのコンタクト孔４に
露出している多結晶シリコン膜２上およびコンタクト孔
４の側面に８０ｎｍの厚さにチタン膜５を被着させ、そ
の後の熱処理を経て、チタン膜５を多結晶シリコン膜２
と共晶させることによりチタンシリサイド膜９が形成さ
れる。The contact hole 4 is, for example, 0.5 μm × 4.0
A titanium film 5 having a thickness of 80 nm is formed on the polycrystalline silicon film 2 exposed to the contact hole 4 and on the side surface of the contact hole 4 with a thickness of 80 μm. , Titanium film 5 and polycrystalline silicon film 2
Then, a titanium silicide film 9 is formed.
【００１４】窒化チタン膜６は、チタン膜５の表面に５
０ｎｍの厚さに被着されている。The titanium nitride film 6 has a thickness of 5
It is deposited to a thickness of 0 nm.
【００１５】コンタクト孔４をチタン膜５、窒化チタン
膜６、タングステン膜７で埋め込むための方法として
は、例えば、公知のスパッタリング法により、チタン膜
５、窒化チタン膜６、をシリコン酸化膜３の表面および
コンタクト孔４内に順次堆積させRTN(Rapid Thermal Ni
triding)法の熱処理を経て、再度タングステン膜をシリ
コン酸化膜３の表面およびコンタクト孔４内にスパッタ
リング法により堆積させ、ＣＭＰ(Chemical Mechanical
Polishing)法によりシリコン酸化膜３の表面が露出す
るまで研磨し、平坦化することにより形成することがで
きる。As a method for filling the contact hole 4 with the titanium film 5, the titanium nitride film 6, and the tungsten film 7, for example, the titanium film 5, the titanium nitride film 6, and the silicon oxide film 3 are formed by a known sputtering method. RTN (Rapid Thermal Ni) is sequentially deposited on the surface and in the contact hole 4.
After the heat treatment of the triding method, a tungsten film is again deposited on the surface of the silicon oxide film 3 and in the contact hole 4 by a sputtering method, and then a CMP (Chemical Mechanical) method.
Polishing) until the surface of the silicon oxide film 3 is exposed, and then planarized.
【００１６】平坦化されたシリコン酸化膜３上には、コ
ンタクト孔４に埋め込まれたチタン膜５、窒化チタン膜
６、タングステン膜７と接続する例えばアルミなどの金
属配線８が形成される。On the flattened silicon oxide film 3, a metal wiring 8 made of, for example, aluminum or the like connected to the titanium film 5, the titanium nitride film 6, and the tungsten film 7 embedded in the contact hole 4 is formed.
【００１７】ここで、多結晶シリコン膜２は、ボロンが
６×１０15ions/cm2イオン注入されており、およそ６０
０ppm/℃の温度係数を持っている。The polycrystalline silicon film 2 is implanted with boron at 6 × 10 15 ions / cm 2 ,
It has a temperature coefficient of 0 ppm / ° C.
【００１８】また、チタン膜５、窒化チタン膜６、タン
グステン膜７、チタンシリサイド膜９からなる配線プラ
グと多結晶シリコン膜２との接触抵抗は、−１０００pp
m/℃の温度係数を持っており、接触抵抗の抵抗値はそれ
ぞれ１５オームであり、両端の接触抵抗の合計が３０Ω
となる。The contact resistance between the wiring plug composed of the titanium film 5, the titanium nitride film 6, the tungsten film 7, and the titanium silicide film 9 and the polycrystalline silicon film 2 is -1000 pp.
m / ° C, the contact resistance is 15 ohms each, and the total contact resistance at both ends is 30Ω
Becomes
【００１９】本実施形態では、多結晶シリコン２による
抵抗値に対する接触抵抗による抵抗値の比が５０：３０
であり、接触抵抗の温度係数の絶対値に対する多結晶シ
リコン２における温度係数の絶対値の比が１０００：６
００となるようにそれぞれの抵抗成分が直列に接続され
ている。そして、この多結晶シリコン２は半導体装置に
おける他の素子を形成する工程で、同時に形成すること
ができる。In this embodiment, the ratio of the resistance value of the contact resistance to the resistance value of the polycrystalline silicon 2 is 50:30.
And the ratio of the absolute value of the temperature coefficient of the polycrystalline silicon 2 to the absolute value of the temperature coefficient of the contact resistance is 1000: 6.
The respective resistance components are connected in series so as to be 00. Then, this polycrystalline silicon 2 can be formed simultaneously in the step of forming another element in the semiconductor device.
【００２０】このため、新たな工程を追加することな
く、それぞれの抵抗性分の温度係数が互いに相殺されて
全体として温度係数を持たない抵抗器を得ることができ
る。Therefore, without adding a new process, the temperature coefficients of the respective resistances cancel each other out, and a resistor having no temperature coefficient as a whole can be obtained.
【００２１】また、本実施形態では、抵抗値が５０Ωの
多結晶シリコン２による抵抗成分と、抵抗値がそれぞれ
１５Ωで合計で３０Ωとなる接触抵抗による抵抗成分と
を直列に接続して、８０Ωの抵抗器を形成する場合につ
いて説明したが、より高抵抗の抵抗器が必要とされる場
合は、本実施形態で説明した、多結晶シリコンによる抵
抗と接触抵抗とから構成される組を複数組直列に接続す
ることによりより高抵抗の抵抗器を形成することが可能
である。In this embodiment, the resistance component of the polycrystalline silicon 2 having a resistance value of 50Ω and the resistance component of a contact resistance having a resistance value of 15Ω each and a total of 30Ω are connected in series to form an 80Ω resistance component. Although the case where a resistor is formed has been described, when a resistor having a higher resistance is required, a plurality of sets each including a resistor made of polycrystalline silicon and a contact resistance described in the present embodiment are connected in series. , It is possible to form a resistor having a higher resistance.
【００２２】また、本実施形態では、多結晶シリコン２
の幅を５μｍとしたが、この多結晶シリコンの幅に比例
した配線プラグの接触面積にすると、多結晶シリコン自
体の抵抗長が２．５μｍであれば、温度係数は実質的に
０ppm/℃である。従って、より低い抵抗値が必要とされ
る場合は、多結晶シリコンの幅を適宜広げることで対応
することが可能である。In this embodiment, the polycrystalline silicon 2
Is 5 μm, but if the contact area of the wiring plug is proportional to the width of the polycrystalline silicon, if the resistance length of the polycrystalline silicon itself is 2.5 μm, the temperature coefficient is substantially 0 ppm / ° C. is there. Therefore, when a lower resistance value is required, it can be dealt with by appropriately increasing the width of the polycrystalline silicon.
【００２３】従って、高抵抗の抵抗器が要求され、複数
組直列に接続した場合でも、多結晶シリコンの幅を適宜
広くした抵抗を組むことで様々な抵抗値にも設計するこ
とが可能である。Therefore, even if a high-resistance resistor is required and a plurality of sets are connected in series, it is possible to design various resistance values by assembling a resistor in which the width of the polycrystalline silicon is appropriately widened. .
【００２４】[0024]
【発明の効果】本発明に係る半導体装置では、多結晶シ
リコンによる抵抗成分と、接触抵抗における抵抗成分を
直列に接続し、多結晶シリコン２による抵抗値に対する
接触抵抗による抵抗値の比と、接触抵抗の温度係数の絶
対値に対する多結晶シリコンにおける温度係数の絶対値
の比とが実質的に等しくなるようにしている。In the semiconductor device according to the present invention, the resistance component of the polycrystalline silicon and the resistance component of the contact resistance are connected in series, and the ratio of the resistance value of the contact resistance to the resistance value of the polycrystalline silicon 2 and the contact The ratio of the absolute value of the temperature coefficient of the polycrystalline silicon to the absolute value of the temperature coefficient of the resistor is made substantially equal.
【００２５】このため、新たな工程を追加することなく
温度係数を持たない抵抗器を形成することができる。Therefore, a resistor having no temperature coefficient can be formed without adding a new process.
【図１】本発明の第１の実施形態を示す平面図および断
面図である。FIG. 1 is a plan view and a cross-sectional view showing a first embodiment of the present invention.
１ 半導体基板 ２ 多結晶シリコン ３ シリコン酸化膜 ４ コンタクト孔 ５ チタン膜 ６ 窒化チタン膜 ７ タングステン膜 ８ アルミ配線 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Polycrystalline silicon 3 Silicon oxide film 4 Contact hole 5 Titanium film 6 Titanium nitride film 7 Tungsten film 8 Aluminum wiring
Claims (4)
る第１の抵抗部分と、 前記第１の抵抗部分と直列に接続される、第２の抵抗値
を有し、温度係数が負である第２の抵抗部分と、を含
み、 前記第１の抵抗値に対する前記第２の抵抗値の比と、前
記第２の抵抗部分が有する温度係数の絶対値に対する前
記第１の抵抗部分が有する温度係数の絶対値の比とが実
質的に同等であることを特徴とする半導体装置。A first resistance portion having a first resistance value and a positive temperature coefficient; and a second resistance value connected in series with the first resistance portion and having a second resistance value. A second resistance portion having a negative coefficient; a ratio of the second resistance value to the first resistance value; and a first resistance value relative to an absolute value of a temperature coefficient of the second resistance portion. A semiconductor device, wherein the ratio of the absolute value of the temperature coefficient of the resistance portion is substantially the same.
記第１の抵抗体は不純物がドープされた多結晶シリコン
であり、前記第２の抵抗体は、前記第１の抵抗と接続さ
れる金属と前記第１の抵抗体との接触抵抗であることを
特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein said first resistor is polycrystalline silicon doped with impurities, and said second resistor is a metal connected to said first resistor. A contact resistance between the first resistor and the first resistor.
記金属は、前記多結晶シリコン上の絶縁層に形成された
コンタクトホール内に埋め込まれた、前記多結晶シリコ
ンの上層に形成される配線と前記多結晶シリコンとを接
続する配線プラグであることを特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein the metal is buried in a contact hole formed in an insulating layer on the polycrystalline silicon and a wiring formed on the polycrystalline silicon. A semiconductor device, which is a wiring plug for connecting to the polycrystalline silicon.
る多結晶シリコン抵抗と、を含み、 前記導電層と前記多結晶シリコン抵抗との間には、負の
温度係数をもつ１対の接触抵抗が形成され、 前記多結晶シリコン抵抗の抵抗値に対する前記１対の接
触抵抗の抵抗値の和の比と、前記接触抵抗が有する温度
係数の絶対値に対する多結晶シリコン抵抗が有する温度
係数の絶対値の比とが実質的に同等であることを特徴と
する半導体装置。4. A pair of conductive layers, and a polycrystalline silicon resistor having both ends connected to the pair of conductive layers and having a positive temperature coefficient, wherein: A pair of contact resistances having a negative temperature coefficient is formed between them, a ratio of the sum of the resistance of the pair of contact resistances to the resistance of the polycrystalline silicon resistance, and a temperature coefficient of the contact resistance. A ratio of the absolute value of the temperature coefficient of the polycrystalline silicon resistance to the absolute value of the semiconductor device is substantially equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000124148A JP3476414B2 (en) | 2000-04-25 | 2000-04-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000124148A JP3476414B2 (en) | 2000-04-25 | 2000-04-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001308270A true JP2001308270A (en) | 2001-11-02 |
| JP3476414B2 JP3476414B2 (en) | 2003-12-10 |
Family
ID=18634323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000124148A Expired - Fee Related JP3476414B2 (en) | 2000-04-25 | 2000-04-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3476414B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008130938A (en) * | 2006-11-22 | 2008-06-05 | Idemitsu Kosan Co Ltd | Conductive molding, electronic component, electric device, electrical characteristics recognition device and method |
| JP2009049167A (en) * | 2007-08-20 | 2009-03-05 | Fujitsu Microelectronics Ltd | Method of manufacturing semiconductor device |
-
2000
- 2000-04-25 JP JP2000124148A patent/JP3476414B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008130938A (en) * | 2006-11-22 | 2008-06-05 | Idemitsu Kosan Co Ltd | Conductive molding, electronic component, electric device, electrical characteristics recognition device and method |
| JP2009049167A (en) * | 2007-08-20 | 2009-03-05 | Fujitsu Microelectronics Ltd | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3476414B2 (en) | 2003-12-10 |
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