JP2001306646A - Timing verifying method for logical simulation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To materialize efficient timing verification by adjustment processing wherein a buffer cell for delay adjustment is virtually inserted in case of a timing error. SOLUTION: When the setup time or hold time during simulation has a positive value and it is evident that there is a timing violation smaller than the prescribed specification value of the setup time or hold time during the simulation, a sequential circuit cell in an internal circuit virtually adds the buffer cell for delay adjustment to a clock or data input terminal of the sequential circuit cell from a delay adjustment buffer information file 107 and adds its addition information in a result storage file 106, and also has a delay adjustment processing flow for carrying on the simulation 102 up to the end time of the event without changing the delay time in the sequential circuit cell, thereby obtaining a simulation result having the timing violation solved by the virtual insertion of the buffer cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for verifying the timing of a logic simulation, and more particularly, to minimizing the number of times of timing error analysis, circuit correction and re-simulation until the circuit design in a semiconductor integrated circuit converges, and a design period The present invention relates to a logic simulation timing verification method that is effective in shortening the timing.

[0002]

2. Description of the Related Art Conventionally, when designing a logic circuit in a semiconductor integrated circuit device, a logic simulation device has been used as a tool for verifying its logic operation and timing. As one method in the logic simulation apparatus for verifying the logical operation, there is, for example, a method called an event driven method.

In the event-driven system, a change in a logic level of a clock signal, a data signal, or the like is registered in a storage unit as an event that affects the logic state of a circuit, and the contents of data are updated while sequentially reading the event. I do. The internal logic circuit that receives this data as input is subjected to arithmetic processing, and if there is a change in its output signal, it is sequentially registered as an event while taking into account the amount of delay, and a simulation is executed.

[0004] The above-described logic simulation is performed by using a sequential circuit cell (hereinafter, referred to as an internal circuit) in an internal circuit of a semiconductor integrated circuit device.
When the timing is verified for setup time and hold time,
This circuit internal cell is provided with a clock signal and two input terminals for reading data in synchronization with the clock signal. The potential of these input terminals changes at different times depending on the skew of the clock signal and the data signal between the time when they are supplied from the outside and the time when they arrive at the input terminals.

Therefore, when a timing violation between the clock signal and the data signal occurs, the event-driven type simulation apparatus detects a timing violation for each address terminal at different times.

Here, the timing violation means that a stable period is required between the data signal and the clock signal for transmission and reception of a normal signal. In order to cope with this, a setup time is defined as a timing specification. And a hold time. If the setup time and the hold time are not observed, the cells inside the circuit will malfunction.

That is, as will be described later, referring to FIG. 4B showing a timing specification of a data flip-flop (hereinafter, referred to as a DFF) as an example of a circuit internal cell, the setup time is based on a clock signal. The data signal must be determined before the change timing, and the time between the determination of the data signal and the change timing of the clock signal (the rise of the logic level from a low level to a high level) is defined as It is defined as a setup, and its timing specification is 0.5 ns.

On the other hand, the hold time requires that the data signal be determined at a point in time after the change timing with respect to the clock signal, and the hold time between the clock signal change timing and the point in time when the data signal is determined is determined. The time is defined as a hold time, and its timing specification is set to 0.5 ns.

As a method for verifying whether the setup time and the hold time satisfy the timing specifications, a timing verification of a logic simulation is employed.

A procedure for handling all timing error information output to the result storage file after the above-described conventional logic simulation timing verification will be described. First, the location of the error is grasped from the internal instance names of all the error cells in the internal circuit, and the internal node state values of the cells around the error cell are simulated.

A propagation path of the output state value of the error cell;
The operating state is analyzed, the circuit is corrected, and a re-simulation is executed using the corrected circuit.

A buffer cell for delay adjustment is inserted into an input terminal of a circuit internal cell in which a timing error has occurred to correct the circuit. The simulation is executed again by the change of the delay value due to the insertion of the buffer cell,
The timing of a circuit connected to the subsequent stage of the circuit internal cell is checked, and the simulation is repeatedly executed until the timing error converges to zero. Therefore, the number of simulations has increased, and the analysis of the results has taken a very long time.

The above-described conventional processing will be described in further detail. First, a description will be given with reference to FIG.

Delay / timing constraint information file D30
The circuit SDFD 302 of each cell in the circuit generated from the delay calculation program S301 based on the information from No. 1 and a circuit connection information file (hereinafter, referred to as a circuit netlist)
D303, a library D304, a verification pattern (input pattern) D305, and a result storage file D306 for storing simulation results. Result storage file D
The files other than 306 need to be read in advance at the time of simulation execution.

A simulation process S312 is executed by the simulation device using the information of each file described above. After the simulation processing S312 is completed, the result is output to the result storage file D306.
In the result storage file D306, timing error information generated during the execution of the simulation and a logical operation value of each verification pattern are described. Result storage file D306
The circuit designer confirms the presence or absence of an error based on (step S31).
4) If there is an error, the circuit is corrected using the circuit netlist D303 in the simulation processing S312.

The process S312 schematically shows the simulation process S312, and the event input process S3
21, a timing check process S322, a logical operation process S323, and a schedule process S324.

Next, the processing flow will be described in detail based on the above-described conventional processing configuration. Referring to FIG. 10 showing a flow of the timing verification process, first, an input event detection process S3 for detecting that an event has occurred at an input terminal of a circuit internal cell in the simulation target circuit.
Execute 31.

When an input event is detected in a circuit internal cell in the simulation circuit by the input event detection processing S331, a time difference calculation processing S332 for calculating a time difference between the event terminal change time and the target terminal change time is executed. The target terminal described here indicates a terminal having a relationship in which a timing specification value is defined with the event input terminal. For example, if the event input terminal is a clock terminal, the target terminal is a data terminal, while if the event input terminal is a data terminal, the target terminal is a clock terminal.

Next, it is determined whether or not the time difference calculated in the time difference calculation processing S332 is larger than the timing specification value, and if it is smaller, a timing specification determination processing S333 is performed, which is regarded as a timing error.

In the timing specification discriminating process S333,
If the time difference is smaller than the timing specification value and it is determined that the execution error has occurred (no), a first logical operation process S33 for performing a logical operation on the circuit internal cell to be verified is performed.
Execute Step 4.

As a result of executing the first logical operation processing S334, a first output state determination processing S335 for determining whether the output state value as the operation result changes is executed.

When it is determined that the output state value changes (yes), a first delay value adding process S336 for adding the delay value of the output state value change path to the event is executed.

Next, a first state value scheduling process S337 for scheduling the output state value to which the delay value has been added in the first delay value adding process S336 and storing the output state value in the result storage file D306 is executed.

An error information output process S for storing the output status values scheduled in the first status value schedule process S337 as error information in the result storage file D306.
Execute 338.

Also, when it is determined in the first output state determination processing S335 that the output state value does not change (no), the process proceeds to the error information output processing S338, and the timing error information is stored in the result storage file D306.

Following the error information output processing S338, an end time determination processing S339 for determining whether the timing verification is the end time is executed. If the end time is not the end time, the process returns to the input event detection processing S331. End verification.

In the timing specification discriminating process S333,
If it is determined that the time difference is larger than the timing specification value and it is not an execution error (yes), a second logical operation process S340 for performing a logical operation on a circuit internal cell to be verified is executed.

Next, a second output state value discriminating process S341 for judging whether or not the output state value which is the operation result of the second logical operation process S340 changes.

If it is determined that the output state value changes (yes), a second delay value adding process S342 for adding the delay value of the output state value change path to the event is executed.

After adding the delay value, a second state value scheduling process S343 for scheduling the output state value and storing it in the result storage file D306 is executed, and in the next end time discrimination process S339, whether the verification pattern indicates the end time is determined. If it is not the end time, the flow shifts to the input event verification wait in step S331, and if it is the end time, the process ends.

[0031]

In the conventional simulation described above, only one circuit can flow in one simulation, and only a logical operation of a specific circuit can be performed.

Therefore, even if a delay adjustment buffer is simply inserted, the circuit must be corrected and a simulation must be executed.

However, in the past, the simulation on the circuit scale was not a method having a particularly serious effect, but due to the recent increase in the circuit scale due to the high integration of the LSI, the conventional method requires a lot of time for the simulation. The impact is growing because it requires it.

An object of the present invention has been made in view of the above-described drawbacks of the related art. When a timing error occurs internally during the first simulation, a buffer cell for delay adjustment is virtually inserted. As a result of the adjustment processing, the simulation is continuously performed assuming a circuit in which a buffer is inserted in the first circuit. As a result, two, and in some cases, two or more circuits are flown, and one An object of the present invention is to provide a logic simulation timing verification method capable of executing an efficient simulation because the second simulation is only confirmation without being specified by a circuit.

[0035]

SUMMARY OF THE INVENTION The present invention relates to a timing verification method for a logic simulation using an event-driven logic simulation apparatus for an internal circuit to be verified. Delay adjustment processing flow for automatically inserting a buffer cell for delay adjustment into at least one of the terminals in response to a timing error between a target terminal for which a timing specification value is defined between the input terminal and the event terminal Is executed until the event end time, and the resulting treatment information and the operation result after the treatment are output to the result storage file, and the circuit is corrected with reference to the result storage file and then re-simulated. , The number of executions of the logic simulation Characterized in that win.

Another feature of the present invention is that in a timing verification method of a logic simulation using an event-driven logic simulation apparatus for an internal circuit to be verified, a delay calculation program is used based on circuit connection information and delay / timing constraint information. The generated wiring delay definition information, the circuit connection information, the operation verification pattern, the logic information of the cell in the circuit net list stored in the cell library, and the information of the buffer cell for delay adjustment are read. At the same time, the first logic simulation is executed using the read information, and if there is a timing error during the execution, the buffer cell for delay adjustment is virtually added to the sequential circuit cell to be verified. The process of scheduling the output state value is performed for all events until the verification end time. Sequentially repeatedly performed for each preparative, and then output to the timing error information to the buffer cell indicating that eliminates timing errors due to the addition of virtually recovered information and the result storage file,
As a result, the circuit designer confirms the contents of the storage file, and if there is the timing error, corrects the circuit using the circuit netlist. By executing the second logic simulation with reference to confirming the circuit correction only, the timing verification converges only by executing the logic simulation twice.

The delay adjustment buffer information file in which the information of the buffer cells for delay adjustment is stored is a delay adjustment buffer information file in which delay information of all cells usable for circuit design and timing specification values of sequential circuit cells are stored. A delay of only the buffer cells for delay adjustment based on the timing constraint information and a block list storing a list of buffer cell names that can be added for delay adjustment among all cells available for circuit design; Further, the logic simulation is performed by an input event detection process of detecting an event at an input terminal of the sequential circuit cell to be verified, and the buffer for delay adjustment is already provided at the input terminal. If the cell is a virtually added event input terminal, the time delayed by the added delay value Event time change processing for replacing with the terminal change time;
A timing check process is performed to calculate a time difference between the input terminal and a target terminal change time at a verification target terminal for which a timing specification value is defined, and if the timing error is detected, the timing adjustment processing is performed from the delay adjustment buffer information file. A selection process of selecting and virtually adding a buffer cell for delay adjustment, and performing a logical operation on the sequential circuit cell to be verified in a state where the buffer cell is virtually added to schedule an output state value. Logical operation
And delay schedule processing.

Further, in the event time changing process, when an input event is detected at the input terminal of the sequential circuit cell, a delay adjustment buffer is added to the input terminal between the start of simulation and the input event detection time. A buffer addition determining process of determining whether the input terminal is the event input terminal by referring to the result storage file. If the input terminal is determined to be the event input terminal in the buffer addition determining process, A delay value search process for searching for a delay value of the buffer cell for delay adjustment added with reference to the buffer information.

In the timing check processing, when it is determined in the determination processing in the event time change processing that the buffer cell for delay adjustment is not added to the input terminal of the sequential circuit cell, the current time is changed. Is the event terminal change time, and when the buffer cell for delay adjustment is added to the input terminal, a delay adjustment buffer delay value search process for searching for a delay value of the added buffer cell; Further comprising: an event terminal change time change process for adding the delay value to the event terminal change time; and a time difference calculation process for calculating a time difference between the event terminal change time change process and the target terminal change time. It is determined whether the time difference obtained in the time difference calculation process is greater than a timing specification value. A time difference determination process for determining an imming error, and in the case of the timing error, a shortage time calculation process of a difference between a timing specification value and the time difference and a specification value for calculating a time required for eliminating the timing error, A virtual buffer that refers to the delay adjustment buffer information file, selects a buffer cell having a delay value greater than the time required for eliminating the timing error, and virtually adds the selected buffer cell to the input terminal Further, the logic operation / delay schedule processing is a state in which the buffer cell having a delay value larger than the shortage time with the timing specification value is added to an event input terminal of the sequential circuit cell to be verified. A first logical operation process of executing a logical operation by A first output state value determining process for determining whether or not a certain output state value changes; and, if it is determined that the output state value changes, the output state value corresponding to the generated event is added to the virtual buffer adding process. A first delay value adding process for adding a delay value of the selected and virtually added buffer cell is performed, and an output state value to which the delay value is added is scheduled. The schedule result is stored in the result storage file. Storing and outputting the timing error information and the recovery information indicating that the timing error has been resolved assuming that the buffer cell has been added, to the result storage file, and outputting the output in the output state value determination processing. Even when it is determined that the status value does not change, the timing error information and the recover information are stored in the result. If the time difference is greater than the timing specification value as a result of the first state value schedule processing to be output to a file and the time difference determination processing, the buffer operation is added to the logic operation of the sequential circuit cell to be verified. A second logical operation to be performed without
A second output state value determining process for determining whether an output state value as a result of the second logical operation changes; and, when determining that the output state value changes, a change path of the output state value for the event. A second delay value adding process for adding a delay value, and a schedule of the output state value to which the delay value is added in the second delay value adding process, and storing the schedule result in the result storage file. 2 state value schedule processing.

Further, instead of the virtual buffer addition processing, an allowable maximum delay value reading processing for reading an allowable maximum delay value of the buffer cell for delay adjustment, and a shortage time required for eliminating the timing error are as follows. A determination process of a maximum allowable delay value for determining whether the delay cell is larger than the allowable maximum delay value, and a delay for selecting a buffer cell name having a delay value smaller than the allowable maximum delay value by referring to the delay adjustment buffer file if the value is larger. Small value buffer cell selection processing, first virtual addition processing for virtually adding the selected buffer cell to the event input terminal, and time obtained by subtracting the delay value of the added buffer cell from the shortage time Is replaced with a new shortage time, and the shortage time change process returns to the process of determining the maximum allowable delay value. If the shortage time required to resolve the timing error in the value determination processing is smaller than the allowable maximum delay value, the buffer for delay adjustment having a delay value larger than the shortage time by referring to the delay adjustment buffer file A buffer cell selection process with a large delay value for selecting a cell and a second virtual addition process for virtually adding the selected buffer cell to the event input terminal are applied.

Still another feature of the present invention is that in a timing verification method of a logic simulation using a logic simulation device of an event driven method for a predetermined internal circuit to be verified, a timing specification value is defined by the internal circuit. If an event occurs at the input terminal of the sequential circuit cell, it is determined whether the input terminal is an event input terminal to which a buffer cell for delay adjustment has been added during the processing up to the current time. The current time is used as the event time, and if it is an event input terminal, the delay information of the added delay adjustment buffer is searched from the delay adjustment buffer information file storing the information of the buffer cell for delay adjustment. The next processing is performed by delaying the event occurrence time by the delay value of the delay adjustment buffer. And the time difference between the change time of the event input terminal of the sequential circuit cell and the target terminal change time at the timing verification target terminal for which the timing specification value is defined between the input terminal is calculated. If the time difference is smaller than a value defined as a timing specification value in the sequential circuit cell, a process of calculating a time required to resolve the timing error that is a difference between the timing specification value and the time difference; Created from a list of delay / timing constraint information files for all cells that can be used for circuit design and a list of buffer cell names that can be used for delay adjustment.
Refer to the delay adjustment buffer information file that stores buffer cell names and delay information that can be used for delay adjustment,
It is assumed that a buffer cell name for delay adjustment having a delay value larger than the time required to resolve the timing error is extracted, and the buffer cell for delay adjustment is added to the event input terminal at the current time. And when the output state value of the sequential circuit cell changes as a result of the logical operation of the sequential circuit cell, the delay value of the buffer cell for delay adjustment is added to the delay value of the output change path due to the event. A process of performing a delay schedule of the output state value, a process of outputting recovery information indicating that timing error information and a buffer cell for delay adjustment have been added to a result storage file, and a verification pattern at the end time. If not, the process waits until the next event is detected, and if it is the end time, ends the timing verification. A logic simulation assuming that a timing error occurring in the sequential circuit cell is automatically resolved by performing a delay schedule of the output state value based on information of the result storage file without changing input circuit data. Is to do.

Further, the operation of the circuit to be verified is guaranteed by individually and arbitrarily changing the delay values of the clock input line and the data input line.

In place of the buffer cell for delay adjustment having a predetermined delay value, a plurality of buffer cells having a delay value smaller than the predetermined delay value are connected in series and added.

Still another feature of the present invention is that in a timing verification method of a logic simulation using a logic simulation device of an event driven system for a predetermined internal circuit to be verified, a sequential circuit cell in the internal circuit is When the setup time or the hold time during the simulation is a positive value, and a timing violation smaller than the predetermined setup time specification value or the hold time specification value is found during the simulation execution, a buffer for delay adjustment is used. A simulation result in which a cell is virtually inserted into a clock or data input terminal of the sequential circuit cell and the timing violation is eliminated by virtually inserting the buffer cell without changing a delay time inside the sequential circuit cell. Get In the door.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of the present invention will be described.
A buffer cell for delay adjustment is automatically provided in at least one of terminals in response to a timing error between an event input terminal of a circuit internal cell generated during a simulation and a target terminal for which a timing specification value is defined between the event input terminal and the event terminal. Is executed until the event end time, the processing information of the result and the operation result after the processing are output to the result storage file, and the circuit correction processing is performed with reference to the result storage file. Is performed and then re-simulated, so that only two simulations are required, and the number of times of timing error analysis, circuit correction, and re-simulation until the circuit design converges is minimized.

Next, the overall configuration of the embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 1 showing the entire configuration of the embodiment of the present invention, the internal delay value and the timing specification of each cell in the circuit generated from the delay calculation program S101 based on the information from the delay / timing constraint information file D101 are shown. Stored circuit SDFD102, circuit netlist D10
3. A file (hereinafter referred to as a library) D10 in which logic information of cells in the circuit netlist D103 is stored.
4. It has input signal data for operation verification (hereinafter referred to as verification pattern) D105, a result storage file D106 for storing simulation results, and a delay adjustment buffer information file D107.

In executing the simulation in the circuit verification, as described above, the circuit netlist D10
3. It is necessary to read each information of the verification pattern D105, the delay / timing constraint information file D101, and the circuit SDFD102.

Using the information in each file described above, a simulation process S202 is performed by the logic simulation apparatus.
After the simulation processing is completed, the simulation result is output to the result storage file D106.

In the result storage file D106, timing error information generated at the time of executing the simulation, a logical operation value of each verification pattern, and the like are described.

Based on the result storage file D106, the circuit designer confirms the presence or absence of an error in the error confirmation processing S103. If there is an error, the circuit is corrected using the circuit netlist D103 in the circuit correction processing S204, and the error confirmation processing is performed. If there is no error in S203, the circuit verification ends.

Process S110 schematically shows the simulation process S202. In the simulation process S110, an event input process S111 for detecting an event at an input terminal of a circuit internal cell to be verified.
Event time change processing S112 for replacing the time delayed by the added delay value with the event terminal change time if the event input terminal already has a buffer cell for delay adjustment virtually added to the input terminal; And a timing check process S113 for calculating a time difference from the target terminal change time in the verification target terminal for which the timing specification value is defined, and if a timing error occurs, the delay adjustment buffer information file D107 reads out the delay adjustment buffer information file D107. A selection process S114 for selecting and virtually adding a buffer cell, and a logic operation process S115 for performing a logic operation on a circuit internal cell to be verified in a state where the buffer cell is virtually added and scheduling an output state value. , Delay schedule processing S116.

Next, the timing verification method of the present invention based on the above-described configuration will be described with reference to FIGS. 2 and 3 which show the processing flow of the timing verification method of the present invention.

The whole structure is obtained by connecting the nodes shown in FIGS. 2 and 3 respectively.

First, an information file that needs to be created in advance when executing a simulation will be described. The delay / timing constraint information file D101 is a file storing delay information of all cells usable for circuit design and timing specification values of cells inside the circuit.

In addition to the file used in the present invention, this file is a circuit SDF which is a wiring delay definition in which wiring delay and timing specification information between all cells in the design circuit are defined.
It is also referred to when creating D102.

The block list D108 is a buffer file used in the present invention among all cells usable for circuit design, and is a list file of buffer cell names that can be added to the design circuit for delay adjustment purposes. is there.

The data processing S200 performs data processing with reference to these two files, the delay / timing constraint information file D101 and the block list D102, and extracts and stores delay information of only buffer cells for delay adjustment. A delay adjustment buffer information file D107 is created.

Delay adjustment buffer information file D107
Is a file directly referenced in the present invention. Note that the delay adjustment buffer information file D107 does not need to be created for each event.

Next, the processing flow of the timing verification method of the present invention will be described.

The input event detection process S201 is a process for detecting an event when an event occurs at an input terminal of a circuit internal cell.

The buffer addition determining process S202 is performed when an input event is detected in the input event detecting process S102.
This processing is to determine whether the input terminal of the circuit internal cell is an event input terminal to which a buffer cell for delay adjustment has been added from the start of the simulation to the input event detection time, by referring to the result storage file D106. .

Delay adjustment buffer delay value search processing S203
When the input terminal is determined to be the event input terminal to which the buffer cell for delay adjustment is added in the buffer addition determination processing S202, the delay value of the buffer cell for delay adjustment is added to the delay value. This is a process of searching with reference to the buffer information file D107.

Event terminal change time change processing S204
Is a process of delaying the event terminal change time by the delay value searched in S203 and replacing the delayed time with the event terminal change time.

On the other hand, if it is determined in the buffer addition determining process S202 that the input terminal is a terminal to which a buffer cell for delay adjustment is not added (no),
The next processing S105 is performed using the current time as the event terminal change time.
Move to

The time difference calculation process S205 is a process for calculating the time difference between the event terminal change time determined in the event terminal change time change process S204 or the buffer addition determination process S202 and the target terminal change time.

The target terminal described here is a terminal having a relationship in which a timing specification value is defined with the event input terminal. If the event input terminal is a clock terminal, the target terminal is a data terminal. Conversely, if the event input terminal is a data terminal, the target terminal is a clock terminal.

The time difference determination processing S206 determines whether the time difference calculated in the time difference calculation processing S205 is larger than the timing specification value. If the time difference is smaller, it is determined as a timing error (no). If larger, it is determined that it is not a timing error (yes). ).

Insufficient time calculation processing with specification value S207
Is the time of the difference between the timing specification and the previously obtained time difference, based on the result that the time difference is smaller than the timing specification value in the time difference determination processing S206, and the timing error is eliminated. This is a process for calculating the time required for the operation.

The virtual buffer addition processing S208 refers to the delay adjustment buffer information file D107, selects a buffer cell name having a delay value larger than the time calculated in the shortage calculation processing S207 with the specification value, and This is a process of virtually adding the buffer cell to the event input terminal.

The first logical operation process S209 is a process of performing a logical operation on a cell inside the circuit in a state where a buffer cell having a delay value larger than the shortage time with the timing specification value is virtually added to the event input terminal. It is.

The first output state value discriminating process S210 is a process for discriminating whether the output state value, which is the result of the first logical operation process S209, changes.

The first delay value addition processing S211 determines that the output state value changes in the first output state value determination processing S210 (yes). This is a process of adding the delay value of the buffer cell for delay adjustment selected in the virtual buffer addition process S208.

First state value schedule processing S212
Is a process of performing a delay schedule of the output state value to which the delay value of the buffer cell for delay adjustment is added, storing the result in the result storage file D106, and then proceeding to the next error information and recovery information output process S213.

The first output state value discrimination processing S210
Also in the case where it is determined (No) that the output state value does not change in the above, the next error information and recovered information output processing S2
13, assuming that timing error information and a buffer cell for delay adjustment have been added, recovery information indicating that the timing error has been eliminated is output to the result storage file D106, and the next end time determination process is performed. S21
Move to 4.

On the other hand, in the time difference determination processing S206, S
Processing when the time difference calculated in 205 is larger than the timing specification value will be described.

The second logical operation process S215 is a process for executing a logical operation on a circuit internal cell to be verified without adding a buffer cell.

The second output state value discriminating process S216 is a process for discriminating whether or not the output state value, which is the result of the second logical operation process S215, changes.

The second delay value adding process S217 is a process of adding a delay value of a change path of the output state value to the event when it is determined that the output state value changes.

Second state value schedule processing S218
Is a process of scheduling the output state value to which the delay value has been added in the second delay value adding process S217, and storing the schedule result in the result storage file D106.

The end time determination process S214 is a process for determining whether or not the verification pattern is the end time. If the end time is not the end time, the process proceeds to the input event detection process S201.

The timing verification method will be specifically described with reference to FIGS. 2, 3, 4, 5, 6, and 7 based on the above-described processes.

Referring to FIG. 4 showing an example of a circuit netlist used in the following description, this circuit netlist is composed of circuit internal cells of three DFFs, and each circuit internal cell name is A1, A2, A3 (hereinafter, each circuit internal cell name is A1, A2, A3).
3). In the terminal names of A1, A2, and A3, D indicates a data terminal, C indicates a clock terminal, and Q indicates an output terminal.

FIG. 5 (a) shows A1, A2, A3 described above.
5B is a truth table of the DFF, and FIG. 5B shows a timing specification. Clock signal row (L
Assuming that the pulse widths (Width) of the ow) level and the high level period are 1 ns, respectively, as described above, the setup time of the data signal at the change point before the change timing is determined based on the clock signal. The time between the time when the data signal is determined (R = Rise / F = Fall) and the rise (R) of the clock signal is defined as setup (Setup), and its timing specification is 0.5 ns.

On the other hand, the hold time is based on the clock signal, and it is necessary for the data signal to be determined at a point after the change timing, and the hold time is determined between the clock signal change timing and the point at which the data signal is determined. The time is defined as a hold time, and its timing specification is set to 0.5 ns.

FIG. 4 and FIG. 6 showing an example of the verification pattern.
(A) and FIG. 6 showing a description example of a result storage file.
Referring also to FIG. 6B, in the present embodiment, the circuit netlist shown in FIG. 4 will be described assuming that simulation is performed using the verification pattern of FIG. 6A. In addition,
D1, D2, C1, C2, N1, and N2 in FIG. 6A are terminals D1, D2, C1, and C in the netlist in FIG.
2, N1 and N2.

First, a description will be given of a delay adjustment buffer information file that needs to be created in advance when executing a simulation for performing timing verification according to the present invention.

FIG. 7 shows a process for creating a delay adjustment buffer information file in advance. In the description example of the delay / timing constraint information file D101 in FIG.
1 (BUF01) represents a block name (BUF01).
In the tpd table, in H01 R indicates that the value of the input terminal (H01) is R (rise). out N01 R is the value of the output terminal (N01) is R
(Rise). In the table, min 0.1000 is the delay value of the min condition, type
0.2000 is the delay value of the type condition, max 0.30
00 indicates a delay value under the max condition.

The block list D108 includes buffer cells BUF01, BUF02, BUF03, B for delay adjustment.
UF04 is described.

As for the delay adjustment buffer information file D107, the delay / timing constraint information file D101
The file has changed the format.

BUF01-4 are block names, IOPAT
H H01 N01 is a terminal name representing an input terminal (H01) and an output terminal (N01). In the left side (1: 2: 3), when the value of the input terminal changes in some way, N01 is R (ris)
e) Delay value when performing (min condition: type condition: max)
Condition). (1: 2: 3) on the right side represents a delay value (min condition: type condition: max condition) when N01 changes to F (Fall) when the value of the input terminal changes in some way.

On the other hand, referring to FIG. 6B, at time 2000, A1
The time difference between the clock terminal C and the data terminal D of (DFF) is four times, and the specified spec value is five times. Therefore, it is described that BUF01 is added to the clock terminal C of A1. Further, as the hold error information, at time 4000, the time difference between the clock terminal C and the data terminal D of A3 (DFF) is one time, and the specified spec value is five times. Therefore, it is described that BUF02 is added to the data terminal D of A3.

The buffer cell names of these content description examples,
The delay value and the like will be referred to at any time in the description of the embodiment described below.

The process S200 includes a delay / timing constraint information file D101 in which delay values of delay conditions of all cells in the circuit net list shown in FIG. Of these, a delay adjustment buffer information file D107 in which delay information of only delay adjustment buffer cells is extracted is created with reference to a block list file D108 of a buffer cell name that can be added to the circuit for the purpose of delay adjustment.

Since the delay adjustment buffer information file D107 created in the above-described process S200 can be created in advance, it is not necessary to create it for each event.

First, at time T2 in FIG.
1 and a Hold timing error at A3 at time T6 in FIG. 6A will be described with reference to FIGS. 2 and 3.

In order to facilitate the following description, the delay value of the output change with respect to the input event of each circuit internal cell is described using the same value, and the maximum value is used as the delay condition.

The time shown in FIG.
The 2000 time of 2 is obtained by converting 0.1 ns to 1 time.

First, at time T2 in FIG.
Will be described with reference to the processing when a Setup timing error occurs.

At time T2, when an input event is detected in the circuit internal cell A1 in the simulation circuit, the input terminal C serving as the event terminal of the circuit internal cell A1 is changed from the start of the simulation to the current time T2 in the buffer addition determining process S202. Whether the terminal is a terminal to which a buffer cell for delay adjustment is added is stored in the result storage file D10.
6 is determined.

As a result, during the period from the start of the simulation to the current time T2, no timing error has occurred at the input terminal C of A1. Therefore, the time 2000 at the current time T2 is set as the event terminal change time, and the process proceeds to the time difference calculation processing S205. .

In the time difference calculation process S205, a time difference between the event terminal change time T2 and the time T1 is calculated.
That is, a timing specification value is defined between the input terminal C (clock terminal) and the input terminal D (data terminal) of A1, and T1 is an event at the input terminal D, and an event terminal change time of the input terminal C. This is an event before T2.

As described above, here, 0.1 ns is set to 1
Since the time difference is expressed as time, the time difference to be obtained is the current time T2 (2000 time) −T1 (1996 time) = 4 times.

Since the time difference = 4 times has been calculated in the time difference calculation processing S205, it is determined in the time difference determination processing S206 whether the time difference = 4 times is greater than the timing specification value of A1.

Since the time difference calculated in the time difference calculation processing S205 is four times and the timing specification value of A1 is five times, the time difference calculated in the time difference calculation processing S205 is smaller than the timing specification value. Is determined to have occurred.

Next, shortage time calculation processing S2 with the specification value
At 07, a time required for eliminating the timing error is obtained. That is, when the shortage time between the time difference calculated in the time difference calculation process S205 and the timing specification value is calculated, one time is short by five times and four times. This is the time required to resolve the timing error.

Since the time required to eliminate the timing error is obtained, in the virtual buffer adding process S208, a delay having a delay value larger than the shortage time calculated in the shortage time calculation process S207 with the specification value is calculated. The buffer cell for adjustment is stored in the delay adjustment buffer information file D.
The buffer cell is selected (BUF01) from 107 and the buffer cell is virtually added to the event terminal (the C terminal in A1 for this timing error item).

In the description of the present embodiment, as an example, only one buffer cell for delay adjustment is added in order to eliminate a timing error. However, the present invention is not limited to this, and the timing error is eliminated. If the shortage time is not possible for a single cell in the delay adjustment buffer information file, the delay value is added in order from the buffer with the largest delay value, and all buffers when the shortage time is reached are selected It is clear that the virtual delay can be added by performing the above.

Thereafter, a logical operation is performed in a first logical operation processing S209, and a first output state value determination processing S210 is performed.
Then, it is determined whether or not the output state value as the calculation result changes.

In the present verification pattern, the output state value changes when the clock of the input terminal C of A1 changes to the high-level state value "1". Move to S211.

In the first delay value adding process S211, the BU selected as the buffer cell for delay adjustment is added to the delay value of the output state value change path (from the start of simulation to the output state value change time) for the event.
The delay value of F01 (from FIG. 6, the delay value of BUF01 is max
= 3 time).

Thereafter, the first state value schedule processing S
In 212, a delay schedule of the output state value of the operation result calculated in the first logical operation process S209 is performed, and in the error information and recover information output process S213, the error information and the virtual buffer addition process S208 are selected. Under the assumption that the delay adjustment buffer name has been added, the recovery information indicating that the timing error has been resolved is output to the result storage file D106.

Thereafter, the flow shifts to end time determination processing S214.
In the end time determination process S214, it is determined whether or not the current time is the end time of the pattern. Since the time is not the end time, the process proceeds to the input event detection process S201.

At the next event occurrence time T3, an input event is detected again in a circuit internal cell in the simulation circuit in the input event detection processing S201. afterwards,
In the buffer addition determination process S202, the circuit internal cell A
It is determined by referring to the result storage file D106 whether the event terminal C of No. 1 is a terminal to which the delay adjustment buffer is added during the processing from the start of the simulation to the current time T3.

At time T2, since a timing error has occurred at the event terminal C of A1, the delay adjustment buffer BUF01 has already been virtually added. Therefore, the process proceeds to the delay adjustment buffer delay value search processing S203.

Delay adjustment buffer delay value search processing S203
, The delay value (= 3 times) of the added delay adjustment buffer cell BUF01 is searched for and extracted with reference to the delay adjustment buffer information file D107.

In the event terminal change time change processing S204, the buffer cell BUF for delay adjustment is set at the current time T3.
01 is extracted and the time T4 delayed by the delay value is replaced with the event terminal change time.

In the time difference calculation process S205, the event terminal change time T4 and the event time before the event terminal change time at the input terminal D (data terminal) of the input terminal A1 whose timing specification value is defined between the event terminal C and the event terminal C are defined. The time difference from T1 is calculated.

In the time difference determination processing S206, it is determined whether the time difference calculated in the time difference calculation processing S205 is larger than the timing specification value.

The time difference calculated in the time difference calculation processing S205 is T4 (2503 time) −T1 (1996 time) = 507 time, which is larger than the five time of the timing specification value of A1, so that a timing error has occurred. It is determined that there is not.

Thereafter, the flow shifts to a second logical operation process S215, where a logical operation is performed.

Since the level of the data signal at the input terminal D of A1 remains at the low level state value "0" and no change has occurred, the output state value does not change. Therefore, the process proceeds to the end time determination process S214.

In the end time determination processing S214, it is determined whether or not it is the end time of the pattern. After that, it moves to the input event detection processing S201.

From the time T3 to the end time, the event time of the input terminal C of A1 is the delay value of BUF01 (= 3 times).
Are virtually added, and the simulation process is performed on the assumption that the buffer cell BUF01 for delay adjustment is added to the input terminal C of A1.

Further, it is assumed that the added buffer cell for delay adjustment is always added immediately before the input terminal C of A1. Therefore, the input terminal C of A1
There is no effect on the clock terminal A3 in FIG. 4 to which the same clock is distributed.

Next, at time T6 in FIG.
The process when a Hold timing error occurs in No. 3 will be described.

At time T6, when an input event is detected in the circuit internal cell A3 in the simulation circuit, in the buffer addition determining process S202, the event terminal D of the circuit internal cell A3 is delayed from the start of the simulation to the current time T6. It is determined whether or not the terminal is a terminal to which an adjustment buffer cell is added by referring to the result storage file D106.

Since no timing error has occurred at the input terminal D of A3 between the start of the simulation and the current time T6, the time at T6 is set as the event terminal change time, and the processing shifts to the time difference calculation processing S205.

In the time difference calculation process S205, the input terminal C of A3 in which the timing specification value is defined between the event terminal change time T6 and the event terminal D
(Clock terminal) event time T5, that is, the time T5 of the event before the event terminal change time T6
Is calculated.

As a result, T6 (4000 time) -T5
(3999 time) = 1 time difference is obtained.

Next, in the time difference determination processing S206,
It is determined whether the time difference calculated in the time difference calculation process S205 is larger than the timing specification value of A3.

As a result of the determination, the time difference calculated in the time difference calculation processing S205 is one time, and the timing specification value is five times. Therefore, the time difference calculated in the time difference calculation processing S205 is smaller than the timing specification value.
It is determined that a timing error has occurred.

Next, shortage time calculation processing S with the specification value
In 207, the time required to resolve the timing error, that is, the shortage time between the time difference calculated in the time difference calculation processing S205 and the timing specification value is calculated, and as a result, 5 times-1 time is short by 4 times. That is what you do.

Thereafter, in the virtual buffer addition process S208, a buffer cell for delay adjustment having a delay larger than the shortage time calculated in the shortage time calculation process S207 with the specification value is stored in the delay adjustment buffer information file D107 in FIG. And the event terminal D
To the buffer cell.

As a result, BUF02 is selected as a buffer cell for delay adjustment having a delay value of 4 hours or more, which is the shortage time calculated in the shortage time calculation processing S207 with the specification value.

In the description of the present embodiment, only one delay adjustment buffer is used to eliminate the timing error. However, the present invention is not limited to this, and the shortage time for eliminating the timing error is not limited to this. If it is not possible with a single cell in the delay adjustment buffer information file, the delay value is added in order from the buffer with the largest delay value, and all the buffers when the shortage time is reached are selected, so that the virtual delay Is added.

The delay adjustment buffer cell to be added is always assumed to be added immediately before the input terminal D of A3.

Next, a logical operation is performed in a first logical operation processing S209, and a first output state value determination processing S210 is performed.
It is determined whether the output state value, which is the calculation result, changes in, and before the event change time T6, since the input terminal D of A3 has not changed, it is determined that the output state value does not change. The process proceeds to error information and recovery information output processing S213.

Next, in the error information and recovery information output processing S213, the error information and the delay adjustment buffer name selected in the virtual buffer addition processing S208 are virtually added to indicate that the timing error has been resolved. The recovery information is output to the result storage file D106, and the process proceeds to the time end determination processing S214.

In the time end determination processing S214, it is determined whether or not the current time is the end time of the pattern. Since it is not the end time, the flow shifts to the input event detection processing S201.

Next, at the next event occurrence time T7 at the input terminal D of A3, the input event detection processing S
At 201, an input event to the circuit internal cell A3 of the simulation circuit is detected.

Next, in the buffer addition determining process S202, it is determined whether or not the event terminal D of the circuit internal cell A3 is the terminal to which the delay adjustment buffer is added during the process from the start of the simulation to the current time T7. The determination is made with reference to D104.

As a result, at time T6, a timing error occurs at the event terminal D of A3, and the buffer cell BUF02 for delay adjustment is virtually added.
The process proceeds to the delay adjustment buffer delay value search processing S203.

Delay adjustment buffer delay value search processing S203
, With reference to the delay adjustment buffer information file D107, the added delay adjustment buffer cell BUF02
Search and extract the delay value of.

In the event terminal change time change processing S204, the buffer cell BU for delay adjustment is set at the current time T7.
F02 is extracted, and the time T8 delayed by the delay value is replaced with the event terminal change time.

In the time difference calculation processing S205, the time difference between the event terminal change time T8 and the event change time T5 at the input terminal C (clock terminal) of A3, whose timing specification value is defined between the event terminal, is calculated. .

In the time difference determination processing S206, it is determined whether the time difference calculated in the time difference calculation processing S205 is larger than the timing specification value.

The time difference obtained in the time difference calculation processing S205 is T8 (4810 time) −T5 (3999 time) = 8
It is 11 hours, which is greater than 5 times of the timing specification value, so it is considered that no timing error has occurred,
The process proceeds to a second logical operation process S215 to perform a logical operation.

At the event change time T8, since the input terminal C of A3 has not changed, the output state value does not change, and the flow shifts to end time determination processing S214.

After it is determined in the end time determination processing S214 whether the current time is the end time of the pattern, the input event detection processing S
Move to 201.

From the time T8 to the end time, the event time of the input terminal D of A3 includes the delay value of BUF02 (5 times).
Is virtually added, and the simulation process is performed under the assumption that the buffer cell BUF02 for delay adjustment is added to the input terminal D of A3.

As described above, the circuit internal cell in the internal circuit has a positive value for the setup time or the hold time during the execution of the simulation, and the specification value of the setup time or the hold time for the predetermined setup time during the execution of the simulation. When a timing violation smaller than the value is found, a buffer cell for delay adjustment is virtually inserted into the clock or data input terminal of the circuit internal cell, and the delay time of the buffer cell is changed without changing the internal delay time of the circuit internal cell. A simulation result in which the timing violation is eliminated by the virtual insertion can be obtained.

In the logic simulation timing verification method of this embodiment, the circuit data is changed to a delay adjustment buffer cell for eliminating the timing error at the input terminal of the circuit internal cell where the timing error has occurred. It is possible to perform the logical operation and the timing check until the verification end time, assuming that the insertion is performed without any problem.

That is, in response to a timing error between the event input terminal of the circuit internal cell generated during the simulation and the target terminal whose timing specification value is defined between the event input terminal and the event terminal, at least one of the terminals automatically receives the timing error. Execute the delay adjustment process of virtually inserting a buffer cell for delay adjustment until the event end time,
The resulting treatment information and the calculation result after the treatment are output to the result storage file, the circuit is corrected with reference to the result storage file, and then the simulation is performed again.

This can minimize the number of timing error analysis, circuit correction, and re-simulation until the circuit design converges, which is effective in shortening the design period.

For example, conventionally, when a timing error is detected in a simulation of a circuit having about 2000 circuit cells, a circuit is corrected based on the timing error information in a result storage file and re-simulated. On average, the above measures until the circuit design converges about six times, ie, timing error detection, circuit correction,
It required repeated re-simulation.

The reason why the number of executions increases is that when a timing error occurs, the result of the timing verification of the circuit connected to the subsequent stage of the error cell is the corrected circuit netlist after the timing error of the error cell is eliminated by circuit correction. This was necessary because the simulations used would have to be understood unless executed.

Therefore, if the circuit scale requires about 30 hours for one circuit simulation, a design period of about 180 hours is required.

On the other hand, according to the present invention, when the circuit is corrected by referring to the result storage file obtained by one simulation, the circuit design can be converged only by confirming the second simulation. With the same circuit scale as above, the circuit design converges in about 60 hours, and
The effect of shortening the circuit design period of 20 hours can be obtained.

Further, from the viewpoint of assuring circuit operation by automatically inserting buffer cells for delay adjustment, the CTS (clock tree synthesis) method is the same as that of the prior art, but the CTS is In contrast to the method of assuring circuit operation by keeping only the skew within a certain value, the timing verification method of the present invention allows the circuit operation to individually and arbitrarily change the delay value of the clock line and the data line. It has a different function, and has different effects.

Next, another embodiment of the present invention will be described.

In the above-described present invention, a buffer cell for delay adjustment having a delay value larger than the difference between the timing specification value and the time difference between the input signal change times of the event terminal and the target terminal is used as the buffer cell for delay adjustment. However, depending on the relationship between the input terminal load capacitance due to the nature and configuration of the simulation circuit, a buffer cell for delay adjustment with a small delay value may be used instead of a buffer cell for delay adjustment having one large delay value. In some cases, it is possible to propagate a signal waveform without disturbing it by adding a plurality of serially connected ones.

To realize signal propagation without disturbing the signal waveform,
In particular, a circuit operating at a high frequency has an effect of reducing a decrease in the operating frequency.

According to the present invention, a plurality of buffer cells for delay adjustment having a delay value equal to or less than the specific delay value can be selected and added. That is, it can be realized only by changing the setting of the allowable maximum delay value and a part of the virtual buffer adding process S208 in FIG. The method will be described below.

Referring to FIG. 8, which shows a flowchart in which the virtual buffer addition process S208 is replaced with another process, the allowable maximum delay value reading process is a process subsequent to the shortage time calculation process S208 in FIG. Execute S301. In the allowable maximum delay value reading process S301, the allowable maximum delay value among the delay values of the buffer cells for delay adjustment in the simulation of the circuit is read with reference to the delay adjustment buffer information file D107.

Next, processing S302 for determining the allowable maximum delay value
Then, it is determined whether the shortage time required to resolve the timing error is larger than the allowable maximum delay value.

In the small delay value buffer selection processing S303, if the shortage time is larger than the maximum allowable delay value in the result of the determination in the maximum allowable delay value determination processing S302, the delay adjustment buffer file is referred to and the delay equal to or less than the maximum allowable delay value is determined. Select a buffer cell name that has a value.

In the first virtual addition process S304, the buffer cell selected in the small delay value buffer selection process S303 is virtually added to the event terminal.

In the shortage time change processing S305, the time obtained by subtracting the delay value of the selected buffer cell from the shortage time is set as a new shortage time, and the process returns to the allowable maximum delay value determination processing S302.

If it is determined in the allowable maximum delay value determination processing S302 that the shortage time required to resolve the timing error is smaller than the allowable maximum delay value, the delay adjustment buffer selection processing S306 selects a delay adjustment buffer. A buffer having a delay value larger than the shortage time is selected with reference to the file D103.

In the second virtual addition process S307, the buffer cell selected in the delay value large buffer selection process S306 is virtually added to the event terminal, and the first cell shown in FIG.
The processing moves to the logical operation processing S209.

Also in this embodiment, when the circuit is corrected by referring to the result storage file obtained by one simulation, the circuit design can be converged only by confirmation in the second simulation execution, and one Rather than adding a delay adjustment buffer cell having a large delay value, a plurality of delay adjustment buffer cells having a small delay value connected in series can be added to propagate a signal waveform without disturbing the signal waveform. .

[0172]

As described above, according to the timing verification method of the logic simulation of the present invention, an event input terminal of a circuit internal cell generated during a simulation and an object whose timing specification value is defined between the event input terminal and the event input terminal are defined. For timing errors between terminals,
A delay adjustment processing flow for automatically inserting a buffer cell for delay adjustment into at least one of the terminals is executed until the event end time, and the resulting treatment information and the calculation result after the treatment are output to a result storage file. Since the results are re-simulated after referring to the storage file and performing circuit correction, the number of times of timing error analysis, circuit correction, and re-simulation until the circuit design converges can be minimized. This is effective in shortening the design period.

Therefore, according to the present invention, when a circuit is modified with reference to a result file obtained by one simulation,
The circuit design can be converged only by the second simulation execution confirmation.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a first half of a processing flow of a timing verification method of the present invention.

FIG. 3 is a diagram showing the latter half of the processing flow of the timing verification method of the present invention.

FIG. 4 is a diagram showing an example of a circuit netlist.

FIG. 5A is a truth table of a DFF. (B) is a diagram showing a timing specification.

FIG. 6A illustrates an example of a verification pattern. (B) is a diagram showing a description example of a result storage file.

FIG. 7 is a diagram showing a process for creating a delay adjustment buffer information file in advance.

FIG. 8 is a diagram illustrating processing when the virtual buffer addition processing S208 is replaced with another processing.

FIG. 9 is a diagram showing an entire configuration of a conventional timing verification.

FIG. 10 is a diagram showing a flow of a conventional timing verification process.

[Explanation of symbols]

A1, A2, A3 DFF D1, D2, C1, C2, N1, N2 Terminals in the netlist D101, D301 Delay / timing constraint information file D102, D302 Circuit SDF D103, D303 Circuit netlist D104, D304 Library D105, D305 Verification pattern D106, D306 Result storage file D107 Delay adjustment buffer information file D108 Block list S101, S311 Delay calculation program S102, S312 Simulation processing S111, S321 Event input processing S112 Event time change processing S113 Timing check processing S114 Selection processing S115 Logical operation processing S116 Delay Schedule processing S200 Data processing S201, S321, S331 Input event detection processing S2 02 Buffer addition determination processing S203 Delay adjustment buffer delay value search processing S204 Event terminal change time change processing S205 Time difference calculation processing S206 Time difference determination processing S207 Insufficient time calculation processing with specification values S208 Virtual buffer addition processing S209, S334 First logic Calculation processing S210, S335 First output state value discrimination processing S211, S336 First delay value addition processing S212, S337 First state value schedule processing S213 Error information and recovery information output processing S214, S339 End time discrimination processing S215, S340 Second logical operation processing S216, S341 Second output state value discrimination processing S217, S342 Second delay value addition processing S218, S343 Second state value schedule processing S301 Permissible maximum delay value read Physical S302 allowable maximum delay value determination process S303 delay value small buffer selection process S304 first virtual additional processing S305 insufficient time changing process S306 delay value sized buffer selection processing S307 second virtual additional processing

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 19/00 110 G06F 19/00 110 H01L 21/82 H01L 21/82 CF term (Reference) 5B046 AA08 BA03 JA01 JA05 5B049 AA06 BB07 CC23 CC32 EE01 EE31 EE42 EE56 EE59 GG04 GG07 5F064 BB19 BB28 EE02 EE47 HH06 HH09 HH12

Claims (13)

[Claims] In a method for verifying the timing of a logic simulation using an event-driven logic simulation device for an internal circuit to be verified, an event input terminal of a sequential circuit cell generated during the logic simulation and the event input terminal. In response to a timing error between target terminals for which a timing specification value is defined, a delay adjustment process flow for automatically inserting a buffer cell for delay adjustment into at least one of the terminals is executed until the event end time. Output the resulting treatment information and the operation result after the treatment to a result storage file, perform a circuit correction process with reference to the result storage file, and re-simulate, thereby executing the logic simulation Characterized by suppressing Logic simulation timing verification method. 2. A method for verifying the timing of a logic simulation using an event-driven logic simulation device for an internal circuit to be verified, wherein a wiring delay definition generated by a delay calculation program from circuit connection information and delay / timing constraint information. Information, the circuit connection information, the operation verification pattern, and the logic information of the cells in the circuit netlist stored in the cell library,
The information of the buffer cells for delay adjustment is read, and the first logic simulation is executed using the read information, and if there is a timing error during the execution, the buffer cells for delay adjustment are virtualized. To sequentially schedule the output state value of the sequential circuit cell to be verified and sequentially executed for every event until the verification end time, and virtually adds the timing error information and the buffer cell. Output to the result storage file indicating that the timing error has been eliminated by the operation, and the circuit designer confirms the contents of the result storage file and corrects the circuit using the circuit netlist if there is the timing error. Then, for the circuit to be verified after the circuit correction, the result storage file Performing the second logic simulation while confirming the circuit correction while referring to the contents, whereby the timing verification converges only by executing the logic simulation twice, wherein the timing verification converges. Method. 3. A delay adjustment buffer information file in which information on the buffer cells for delay adjustment is stored, the delay adjustment buffer information file includes delay information in which delay information of all cells usable in circuit design and timing specification values of sequential circuit cells are stored. A delay of only the buffer cells for delay adjustment based on the timing constraint information and a block list storing a list of buffer cell names that can be added for delay adjustment among all cells available for circuit design; 3. The logic verification timing verification method according to claim 2, wherein the timing is created by data processing for extracting information. 4. The logic simulation includes an input event detection process of detecting an event at an input terminal of the sequential circuit cell to be verified, and the buffer cell for delay adjustment is already virtually added to the input terminal. Event input terminal, an event time change process for replacing a time delayed by the added delay value with an event terminal change time, and a target terminal in a verification target terminal for which a timing specification value is defined between the input terminal and the event input terminal. Performing a timing check process of calculating a time difference from the change time, and selecting the buffer cell for delay adjustment from the delay adjustment buffer information file and virtually adding the buffer cell if the timing error is detected; Performs a logical operation on the sequential circuit cell to be verified in a state where the cells are virtually added, and outputs the result. 3. A logic operation / delay schedule process for scheduling a force state value.
The timing verification method of the logic simulation described. 5. The event time change processing includes detecting an input event at the input terminal of the sequential circuit cell.
A buffer addition determining process for determining whether the input terminal is an event input terminal to which a delay adjustment buffer is added from the start of the simulation to an input event detection time by referring to the result storage file; In the case where the input terminal is determined to be the event input terminal, a delay value search process for searching for a delay value of the buffer cell for delay adjustment added with reference to the delay adjustment buffer information. 5. The logic simulation timing verification method according to claim 4. 6. The timing check processing is performed, when it is determined in the determination processing in the event time change processing that the buffer cell for delay adjustment is not added to the input terminal of the sequential circuit cell, Is the event terminal change time, and when the buffer cell for delay adjustment is added to the input terminal, a delay adjustment buffer delay value search process for searching for a delay value of the added buffer cell; 5. The event terminal change time changing process of adding the delay value to the event terminal change time, and a time difference calculating process of calculating a time difference between the event terminal change time change process and the target terminal change time. Timing verification method for logic simulation. 7. The selection process includes a process for comparing whether the time difference obtained in the time difference calculation process is greater than a timing specification value, and determining a time error if the time difference is smaller, and a timing specification value for the timing error. A shortage time calculation process for calculating a time required for eliminating the timing error, which is a difference between the timing error and the time difference, and referring to the delay adjustment buffer information file to perform the operation for eliminating the timing error. 5. The logic simulation timing verification method according to claim 4, further comprising: a virtual buffer addition process of selecting a buffer cell having a delay value greater than a predetermined time and virtually adding the selected buffer cell to the input terminal. 8. The logical operation / delay schedule processing is performed in a state where the buffer cell having a delay value larger than the shortage time with the timing specification value is added to an event input terminal of the sequential circuit cell to be verified. And a first output state value determining process of determining whether an output state value as a result of the logical operation changes, and a case where the output state value is determined to change , The output state value for the event that occurred,
A first delay value adding process for adding a delay value of the buffer cell selected and virtually added in the virtual buffer adding process, and an output state value to which the delay value is added are scheduled. A result is stored in the result storage file, and timing error information and recovery information indicating that the timing error has been resolved assuming that the buffer cell has been added are output to the result storage file, respectively. A first state value schedule process for outputting the timing error information and the recover information to the result storage file also when the output state value is determined not to change in the state value determination process, and the time difference determination process. If the time difference is larger than the timing specification value in the determination result of A second logical operation to perform a logical operation of the sequential circuit cell without adding the buffer cell,
A second output state value determining process for determining whether an output state value as a result of the second logical operation changes; and, when determining that the output state value changes, a change path of the output state value for the event. A second delay value adding process for adding a delay value, and a schedule of the output state value to which the delay value is added in the second delay value adding process, and storing the schedule result in the result storage file. 5. The logic verification timing verification method according to claim 4, comprising a two-state value schedule process. 9. Instead of the virtual buffer addition processing,
An allowable maximum delay value reading process for reading the allowable maximum delay value of the buffer cell for delay adjustment, and a maximum allowable delay value for determining whether the shortage time required to resolve the timing error is larger than the allowable maximum delay value. And a delay value small buffer cell selecting process of selecting a buffer cell name having a delay value smaller than the allowable maximum delay value by referring to the delay adjustment buffer file if the buffer cell size is larger, and the selected buffer cell Virtual addition processing for virtually adding the delay time to the event input terminal, replacing the time obtained by subtracting the delay value of the added buffer cell from the shortage time as a new shortage time, and determining the maximum allowable delay value. Shortage time change processing returning to the processing,
If the shortage time required to resolve the timing error in the process of determining the maximum allowable delay value is smaller than the allowable maximum delay value, the delay adjustment is performed by referring to the delay adjustment buffer file and having a delay value larger than the shortage time. 8. The logic according to claim 7, wherein a buffer value selecting process for selecting a buffer cell for a large delay value and a second virtual adding process for virtually adding the selected buffer cell to the event input terminal are applied. Simulation timing verification method. 10. A timing verification method for a logic simulation using a logic simulation device based on an event-driven system for a predetermined internal circuit to be verified, wherein an input terminal of a sequential circuit cell in which a timing specification value is defined in the internal circuit. If an event occurs, it is determined whether the input terminal is an event input terminal to which a buffer cell for delay adjustment has been added during the processing up to the current time. If the input terminal is an event input terminal, the delay information of the added delay adjustment buffer is searched from the delay adjustment buffer information file storing the information of the buffer cells for delay adjustment, and the delay value of the searched delay adjustment buffer is calculated. Processing for delaying the event occurrence time and performing the next processing; A time difference between a change time of the event input terminal of the cell and a target terminal change time at a timing verification target terminal whose timing specification value is defined between the input terminal is calculated, and the calculated time difference is calculated by the sequential circuit cell. If the value is smaller than the value defined as the timing specification value, a process for calculating a time required to resolve the timing error, which is a difference between the timing specification value and the time difference, and a circuit design prepared in advance as a reference library Adjustment buffer that stores buffer cell names and delay information that can be used for delay adjustment, created from the delay / timing constraint information file of all cells that can be used for delay adjustment and a list of buffer cell names that can be used for delay adjustment Referring to the information file, a delay larger than the time required to resolve the timing error is used. Extracting a buffer cell name for delay adjustment having a value, assuming that the buffer cell for delay adjustment has been added to the event input terminal at the current time, and as a result of a logical operation of the sequential circuit cell When the output state value of the sequential circuit cell changes, a process of adding the delay value of the buffer cell for delay adjustment to the delay value of the output change path due to the event to perform a delay schedule of the output state value; The process of outputting the error information and the recovery information to the effect that the buffer cell for delay adjustment is added to the result storage file, and if the verification pattern is not the end time, the process waits until the next event is detected and the end time. Processing for ending timing verification, if any, in the input circuit A logic simulation assuming that a delay schedule of the output state value is made based on the information of the result storage file and that the output state value is automatically canceled without changing the data. . 11. The logic simulation timing verification method according to claim 2, wherein the delay values of the clock input line and the data input line are individually and arbitrarily changed to guarantee the operation of the circuit to be verified. 12. A plurality of buffer cells having a delay value smaller than the predetermined delay value are connected in series and added in place of the buffer cells for delay adjustment having a predetermined delay value. 11. The logic simulation timing verification method according to 1, 2, or 10. 13. A timing verification method for a logic simulation using an event-driven logic simulation apparatus for a predetermined internal circuit to be verified, wherein a sequential circuit cell in the internal circuit has a setup time or hold during simulation execution. If the time is a positive value and a timing violation smaller than the setup time specification value or the hold time specification value specified in advance during simulation execution is found, a buffer cell for delay adjustment is clocked by the sequential circuit cell. Alternatively, a simulation result in which the timing violation has been eliminated by virtually inserting the buffer cell without changing the delay time inside the sequential circuit cell is virtually obtained by inserting the buffer cell into the data input terminal. simulation How to verify the timing of the solution.