CN109388813A - A kind of method and device constructing the Clock Tree for IC design - Google Patents
A kind of method and device constructing the Clock Tree for IC design Download PDFInfo
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- CN109388813A CN109388813A CN201710657076.5A CN201710657076A CN109388813A CN 109388813 A CN109388813 A CN 109388813A CN 201710657076 A CN201710657076 A CN 201710657076A CN 109388813 A CN109388813 A CN 109388813A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/06—Structured ASICs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
A method of building is used for the Clock Tree of IC design, comprising: by carrying out Time-Series analysis to the register in the complete Clock Tree netlist of length, determines the destination register group for occurring settling time fault in the netlist；One is inserted under the clock interface of source for guiding Clock Tree to generate the clock buffer in direction, the clock buffer placement position is close to the region of the destination register group.A kind of device constructing the Clock Tree for IC design, this programme can solve repairs the too long caused settling time fault problem of long Clock Tree in a chip design.
Description
Technical field
The present embodiments relate to but be not limited to technical field of integrated circuits, espespecially it is a kind of building be used for IC design
Clock Tree method and device.
Background technique
Chip manufacturing process continues to develop, and the especially development of deep sub-micron technique collects the chip of unit area
Whole system at more gate circuits, or even with certain function can be integrated into a chip, with consumer electricity
Son flourishes, and consumer chip uses system-on-chip designs technology more and more widely, and chip-scale is increasing, function
It becoming increasingly complex, speed is getting faster, and integrated IP (intellectual property) is also more and more, and the development cycle is also shorter and shorter,
So when having foundation (setup) time fault problem, if rear end can be by adjusting Clock Tree to solve and without changing
In generation, arrives developer's Optimized code, that can greatly shorten entire design time.
Wherein, settling time refers to that before the rising edge clock signal of register arrives, data-signal is stablized constant
Time, if timing path delay is too big, settling time is inadequate, and data cannot accurately be squeezed into register, will lead to establish
Time breaks rules.
It is logic or people from rear end optimized on data path in developer that tradition, which repairs the method that settling time breaks rules,
Member replaces the biggish cell of delay with other smaller VT cell (threshold voltage unit) of delay (delay).The first is needed
It iterates to exploitation to optimize over there, the design cycle can be elongated, and second can be to affecting on chip power-consumption or cost.
Summary of the invention
The embodiment of the present invention provides a kind of method and device for constructing the Clock Tree for IC design, to solve to exist
The too long caused settling time fault problem of long Clock Tree is repaired in chip design.
A method of building is used for the Clock Tree of IC design, comprising:
By carrying out Time-Series analysis to the register in the complete Clock Tree netlist of length, determine settling time occur in the netlist
The destination register group of fault；
One is inserted under the clock interface of source for guiding Clock Tree to generate the clock buffer in direction, the clock buffer
Device placement position is close to the region of the destination register group.
Optionally, it is naturally raw to be less than the Clock Tree for distance of the clock buffer of insertion away from the source clock interface
Length need to increase the default distance of clock buffer.
Optionally, described that one is inserted on the clock interface of source for guiding Clock Tree to generate the clock buffer in direction
Afterwards, further includes:
Time-Series analysis is carried out to Clock Tree netlist has currently been grown, to be disobeyed as there is also settling times in the destination register group
The destination register of example, then it is slow in the clock end insertion clock of the destination register back to the stage before long Clock Tree
Device is rushed, the number for being inserted into clock buffer is determined according to the size that the settling time of the destination register breaks rules, then again
Start long Clock Tree.
Optionally, it is described restart long Clock Tree after, further includes:
Remove the clock buffer in the clock end insertion of the destination register.
Optionally, the source clock, which is located at, can not turn off region, and the register-bit in the netlist by layout is in can
Region is turned off, the clock buffer of insertion, which is located at, can turn off region.
A kind of device constructing the Clock Tree for IC design, wherein include:
Analysis module, for determining the netlist by carrying out Time-Series analysis to the register in the complete Clock Tree netlist of length
The middle destination register group for settling time fault occur；
Pop-in upgrades, for being inserted into one under the clock interface of source for guiding the clock buffer of the Clock Tree direction of growth
Device, the clock buffer placement position are close to the region of the destination register group.
Optionally, the clock buffer of the pop-in upgrades, insertion is less than institute away from the distance of the source clock interface
State the default distance that need to increase clock buffer when Clock Tree is grown naturally.
Optionally, the analysis module is also used to be inserted into one on the clock interface of source in the pop-in upgrades for drawing
After leading the clock buffer that Clock Tree generates direction, Time-Series analysis is carried out to Clock Tree netlist has currently been grown, determines the target
Whether there is also the destination registers of settling time fault in register group；
The pop-in upgrades, the case where the analysis module determines the destination register to break rules there is also settling time
Under, in the stage back to before long Clock Tree, be inserted into clock buffer near the destination register, the number of insertion according to
The size that the settling time of the destination register breaks rules determines, then restarts long Clock Tree.
Optionally, the pop-in upgrades, it is described restart long Clock Tree after be also used to: remove in the destination register
Clock end insertion clock buffer.
Optionally, the source clock, which is located at, can not turn off region, and the register-bit in the netlist by layout is in can
Region is turned off, the clock buffer of insertion, which is located at, can turn off region.
To sum up, the embodiment of the present invention provides a kind of method and device for constructing the Clock Tree for IC design, can
To solve the problems, such as to repair the too long caused settling time fault of long Clock Tree in a chip design.
Detailed description of the invention
Fig. 1 is the flow chart for the method that a kind of building of the embodiment of the present invention is used for the Clock Tree of IC design；
Fig. 2 is the line map schematic diagram that Clock Tree is long under normal circumstances；
Fig. 3 is Clock Tree path schematic diagram after the insertion clock buffer of the embodiment of the present invention；
Fig. 4 is the Clock Tree path schematic diagram of the virtual insertion clock buffer of the embodiment of the present invention；
Fig. 5 is the schematic diagram for the device that a kind of building of the embodiment of the present invention is used for the Clock Tree of IC design.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Fig. 1 is the flow chart for the method that a kind of building of the embodiment of the present invention is used for the Clock Tree of IC design, such as
Shown in Fig. 1, the method for the present embodiment includes:
Step 11, by the complete Clock Tree netlist of length register carry out Time-Series analysis, determine occur in the netlist
The destination register group that settling time breaks rules；
Step 12 is inserted into the clock buffer for being used to that Clock Tree to be guided to generate direction under the clock interface of source, described
Clock buffer placement position is close to the region of the destination register group.
In low power dissipation design, region (Always on powerdomain) can not be turned off and can turn off region by existing
(lowpowerdomain), (High Definition Multimedia Interface, high-definition multimedia connect HDMI
Mouthful) physical module (phy) of this IP is can not to turn off region, and associated control logic can turn off region, from HDMI object
The clock phy_clk driving that reason module comes out can turn off many registers in region, but have the output of one group of register directly to make
It is inputted for the data of HDMI phy, and there are settling time fault for this group of register, become the critical path on phy_clk Clock Tree
Diameter, and when the logic on data path can not optimize space, however the timing of the prime of this group of register is patrolled
Volume but there is the surplus (margin) that can be borrowed, this time can the mode of adjustment Clock Tree through this embodiment repair this
The problem of settling time existing for group register breaks rules.
Fig. 2 is the conspectus of Clock Tree growth under normal circumstances, as shown in Fig. 2, when not increasing intervention, no
An output port of the HDMI inside region can be turned off as the clock source that can turn off component register inside region, clock
Entrance can turn off in region after tree can grow to always the left side from the right in figure along narrow passage, and Clock Tree is every to pass through default distance meeting
Automatically increase a clock buffer.
In Fig. 2 several groups of registers arrangement position immediately below HDMI middle position, such Clock Tree from the right around
The length of Clock Tree is come in virtually to increase again in the left side, and the output of this several groups of registers is as HDMI partial data end
Input, so that the settling time of this several groups of registers to HDMI break rules.
According to the method for the present embodiment, before long Clock Tree, a clock buffer is selected, Clock Tree source is inserted into,
And the clock buffer of insertion is arranged in HDMI can turn off in region, as shown in figure 3, the Clock Tree of register in this way will not be from
The left side grows to always the right, but directly grows from top to bottom, and this substantially reduces the Clock Trees of this group of register, to solve
The problem of settling time caused by this group of register clock tree is too long breaks rules.
After step 12, can also include:
Time-Series analysis is carried out to Clock Tree netlist has currently been grown, if established there is also individual in the destination register group
The destination register that time breaks rules is inserted into then back to the stage before long Clock Tree in the clock end of the destination register
Clock buffer is inserted into the size determination that the number of clock buffer breaks rules according to the settling time of the destination register, so
After restart long Clock Tree.After restarting long Clock Tree, removal is when the clock end of the destination register is inserted into
Clock buffer
After being inserted into a clock buffer under the clock interface of source, it there is also component register sometimes and do not solve to build
The problem of breaking rules between immediately can be solved, for example, in length in this case by being virtually inserted into the method for clock buffer
At these, there is also the ends CLK of the register of settling time fault to be inserted into clock buffer, isometric complete Clock Tree before Clock Tree
Clock buffer virtual on the end these registers CLK is removed again afterwards, as shown in figure 4, also shortening this group of register in this way
Clock Tree, so that the settling time fault problem of this group of related register all is solved to fall.
For example having 10 registers in one group of register group, the position put is variant from clock source, in long Clock Tree
When the clock buffer number that each register is inserted into will be different according to scheduled algorithm, and the length of Clock Tree is
The principal element that settling time breaks rules, in ceteris paribus, if the Clock Tree of the register is long, just
It is possible that there is settling time fault.And after being virtually inserted into clock buffer, calculating this 10 register clocks to be inserted into
Buffer number when these virtual clock buffers can be taken into account.
Need to be inserted into 12 clock buffers assuming that calculating according to scheduled algorithm to register A, since Clock Tree is too long,
There is settling time fault in register A, and 2 are virtually inserted at the clock end of register A according to the size that settling time breaks rules
Clock buffer for register A other than 2 clock buffers being virtually inserted into, also needs in this way in long Clock Tree again
Be inserted into 10 clock buffers, Clock Tree has grown 2 clock buffers moved back except being virtually inserted into, such register A when
10 clock buffers of Zhong Shuwei, Clock Tree length obviously shortens, to solve the problems, such as settling time fault.
Virtual insertion clock buffer can have following two method:
1, the clock end in specified register that can be artificial before long Clock Tree is inserted into clock buffer, isochronon
Tree removes the clock buffer being artificially inserted into after having grown again；
2, before long Clock Tree, the clock end setting unit with order in the register for settling time fault occur is prolonged
Late, it is assumed that the delay of a clock buffer is 50ps, and the register clock end, which is arranged before long Clock Tree, has had 200ps to prolong
Late, it is equivalent to virtually be inserted into 4 clock buffers.
The embodiment of the present invention is by being inserted directly into a clock buffer at the hour at source to draw before long Clock Tree
The direction for leading long Clock Tree prevents that region can be turned off and can not turn off the problem of Clock Tree is around long line between region, allows critical path
The Clock Tree length as far as possible of one group of register of diameter is a little.
If finally found that individual register clock trees in this group of register in the case where no coiling or exist
A little settling times break rules, and the Clock Tree of component register can also be made to grow by being virtually inserted into clock buffer more shorter, from
And solve the problems, such as that Clock Tree is too long and data path does not have settling time fault caused by surplus.Avoid the iteration of modification code
Time reduces the period of chip development.
Fig. 5 is the schematic diagram for the device that a kind of building of the embodiment of the present invention is used for the Clock Tree of IC design, such as
Shown in Fig. 5, the device of the present embodiment may include:
Analysis module, for determining the netlist by carrying out Time-Series analysis to the register in the complete Clock Tree netlist of length
The middle destination register group for settling time fault occur；
Pop-in upgrades, for being inserted into one under the clock interface of source for guiding the clock buffer of the Clock Tree direction of growth
Device, the clock buffer placement position are close to the region of the destination register group.
In one embodiment, the pop-in upgrades, the clock buffer of insertion is away from the distance of the source clock interface
The default distance of clock buffer need to be increased when growing naturally less than the Clock Tree.
In one embodiment, the analysis module is also used to be inserted into one on the clock interface of source in the pop-in upgrades
After clock buffer for guiding Clock Tree to generate direction, Time-Series analysis is carried out to Clock Tree netlist has currently been grown, determines institute
State in destination register group whether there is also the destination registers of settling time fault；
The pop-in upgrades, the case where the analysis module determines the destination register to break rules there is also settling time
Under, in the stage back to before long Clock Tree, be inserted into clock buffer near the destination register, the number of insertion according to
The size that the settling time of the destination register breaks rules determines, then restarts long Clock Tree.
In one embodiment, the pop-in upgrades, it is described restart long Clock Tree after be also used to: remove in the target
The clock buffer of the clock end insertion of register.
In one embodiment, the source clock, which is located at, can not turn off region, the register in the netlist by layout
Positioned at that can turn off region, the clock buffer of insertion, which is located at, can turn off region.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program
Related hardware is completed, and described program can store in computer readable storage medium, such as read-only memory, disk or CD
Deng.Optionally, one or more integrated circuits can be used also to realize in all or part of the steps of above-described embodiment.Accordingly
Ground, each module/unit in above-described embodiment can take the form of hardware realization, can also use the shape of software function module
Formula is realized.The present invention is not limited to the combinations of the hardware and software of any particular form.
The above is only a preferred embodiment of the present invention, and certainly, the invention may also have other embodiments, without departing substantially from this
In the case where spirit and its essence, those skilled in the art make various corresponding changes in accordance with the present invention
And deformation, but these corresponding changes and modifications all should fall within the scope of protection of the appended claims of the present invention.
Claims (10)
1. a kind of method of Clock Tree of building for IC design, comprising:
By carrying out Time-Series analysis to the register in the complete Clock Tree netlist of length, determine occur settling time fault in the netlist
Destination register group；
One is inserted under the clock interface of source for guiding Clock Tree to generate the clock buffer in direction, the clock buffer pendulum
Putting position is close to the region of the destination register group.
2. the method as described in claim 1, it is characterised in that:
Distance of the clock buffer away from the source clock interface of insertion is grown less than the Clock Tree naturally when need to increase
The default distance of clock buffer.
3. the method as described in claim 1, it is characterised in that: described to be inserted into one on the clock interface of source for guiding clock
After tree generates the clock buffer in direction, further includes:
Time-Series analysis is carried out to Clock Tree netlist has currently been grown, as broken rules in the destination register group there is also settling time
Destination register is inserted into clock buffer in the clock end of the destination register then back to the stage before long Clock Tree,
The number for being inserted into clock buffer is determined according to the size that the settling time of the destination register breaks rules, and then restarts to grow
Clock Tree.
4. method as claimed in claim 3, it is characterised in that: it is described restart long Clock Tree after, further includes:
Remove the clock buffer in the clock end insertion of the destination register.
5. method according to any of claims 1-4, it is characterised in that:
The source clock, which is located at, can not turn off region, and the register-bit in the netlist by layout is inserted in that can turn off region
The clock buffer entered, which is located at, can turn off region.
6. a kind of device of Clock Tree of building for IC design characterized by comprising
Analysis module, for determining to go out in the netlist by carrying out Time-Series analysis to the register in the complete Clock Tree netlist of length
The destination register group that existing settling time breaks rules；
Pop-in upgrades, for being inserted into one under the clock interface of source for guiding the clock buffer of the Clock Tree direction of growth, institute
Stating clock buffer placement position is close to the region of the destination register group.
7. device as claimed in claim 6, it is characterised in that:
The clock buffer of the pop-in upgrades, insertion is less than the Clock Tree nature away from the distance of the source clock interface
The default distance of clock buffer need to be increased when growth.
8. device as claimed in claim 6, it is characterised in that:
The analysis module is also used to be inserted into one on the clock interface of source in the pop-in upgrades for guiding Clock Tree to generate
After the clock buffer in direction, Time-Series analysis is carried out to Clock Tree netlist has currently been grown, determining in the destination register group is
The no destination register to break rules there is also settling time；
The pop-in upgrades returns in the case where the analysis module determining destination register to break rules there is also settling time
The stage before long Clock Tree is returned to, clock buffer is inserted near the destination register, the number of insertion is according to
The size that the settling time of destination register breaks rules determines, then restarts long Clock Tree.
9. device as claimed in claim 8, it is characterised in that:
The pop-in upgrades, it is described restart long Clock Tree after be also used to: remove the destination register clock end insert
The clock buffer entered.
10. device as claim in any one of claims 6-9, it is characterised in that:
The source clock, which is located at, can not turn off region, and the register-bit in the netlist by layout is inserted in that can turn off region
The clock buffer entered, which is located at, can turn off region.
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| CN201710657076.5A CN109388813B (en) | 2017-08-03 | 2017-08-03 | Method and device for constructing clock tree for integrated circuit design |
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| CN201710657076.5A CN109388813B (en) | 2017-08-03 | 2017-08-03 | Method and device for constructing clock tree for integrated circuit design |
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Cited By (5)
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| CN110555269A (en) * | 2019-09-02 | 2019-12-10 | 天津飞腾信息技术有限公司 | Top-level clock tree structure of system on chip |
| CN111046624A (en) * | 2019-12-17 | 2020-04-21 | 天津飞腾信息技术有限公司 | Method, device, equipment and medium for constructing chip module interface clock structure |
| CN112131810A (en) * | 2020-09-29 | 2020-12-25 | 天津飞腾信息技术有限公司 | Method and device for restoring set-up time violation, electronic equipment and readable storage medium |
| CN114578895A (en) * | 2020-12-02 | 2022-06-03 | 京东方科技集团股份有限公司 | Integrated circuit and clock signal distribution method thereof |
| CN114676658A (en) * | 2022-05-20 | 2022-06-28 | 飞腾信息技术有限公司 | Time sequence violation repairing method and device, storage medium and electronic equipment |
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|---|---|---|---|---|
| CN110555269A (en) * | 2019-09-02 | 2019-12-10 | 天津飞腾信息技术有限公司 | Top-level clock tree structure of system on chip |
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| CN112131810A (en) * | 2020-09-29 | 2020-12-25 | 天津飞腾信息技术有限公司 | Method and device for restoring set-up time violation, electronic equipment and readable storage medium |
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| CN114578895A (en) * | 2020-12-02 | 2022-06-03 | 京东方科技集团股份有限公司 | Integrated circuit and clock signal distribution method thereof |
| CN114676658A (en) * | 2022-05-20 | 2022-06-28 | 飞腾信息技术有限公司 | Time sequence violation repairing method and device, storage medium and electronic equipment |
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|---|---|
| CN109388813B (en) | 2023-04-14 |
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