JP2001306496A - Data output device and data output method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data output device in which the processing burden on a data receiver can be reduced and also the wiring can be saved while simplifying its installing work. SOLUTION: A counter 11 has a CK output circuit 62, a CK input circuit 63, an STB output circuit 66, an STB input circuit 69, a master-slave identification circuit 71 and a DATA output circuit 72. When an STB OUT signal is coincident with an STB IN signal a state where the counter 11 is mounted on a connector 92a or 92b of a sequencer 91, the circuits 62 and 66 are actuated as master counters to output a clock signal and a strobe signal (STB1) to a clock signal line 61 and a strobe signal line 65. When no coincidence is secured between the STB OUT and STB IN signals, the circuits 63 and 69 are actuated as slave counters, and all counters 11 output data to the sequencer 91 with the same clock and strobe signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data output device and method for outputting data to an external device such as a sequencer.

[0002]

2. Description of the Related Art Conventionally, as such a data output device, an in-line built-in measuring device for transmitting data to an external device such as a sequencer has been known. Is used for data transmission. When transmitting 6 digits of BCD data in parallel, 24 (= 6 digits × 4 bits) signal lines are required. Therefore, when connecting a plurality of measuring instruments to the sequencer, the wiring cost is high. turn into. For this reason, conventionally, serial transmission of BCD data is also performed.

[0003]

However, the BCD
When transmitting data serially, if multiple measuring instruments are connected to one sequencer, the data output from each measuring instrument will be performed at irregular timing, making the data acquisition process of the receiving sequencer complicated. There was a problem that would be. Further, it has been desired to further reduce the number of signal lines without complicating an installation operation for connecting a plurality of measuring instruments to the sequencer.

Therefore, the present invention can reduce the processing load on the data receiving side when a plurality of external devices such as a sequencer are connected to perform data transmission, simplify the installation work, and reduce wiring. It is an object to provide a data output device and method that can be realized.

[0005]

In order to achieve the above object, a data output device according to a first aspect of the present invention is a data output device having a timing connected between at least one of a plurality of data output devices and an external device. A data output device that serially outputs data to the external device according to a timing signal transmitted via a signal line, and a timing signal output unit that outputs the timing signal; and a timing signal input from the timing signal line. Timing signal input means, and a timing signal input from the timing signal line and a timing signal output from the timing signal output means are compared, and when both timing signals match and are identified as a master, Outputting a timing signal output from the timing signal output means to the timing signal line; On the other hand, if the two timing signals do not match and are identified as a slave, master / slave identification control means for stopping output from the timing signal output means to the timing signal line; and And a data transmitting means for transmitting the data.

In addition, the timing signal is a transmission of data output in synchronization with a clock signal transmitted via a clock signal line connected between at least one of a plurality of data output devices and the external device. A clock signal output means for outputting the clock signal toward the clock signal line, and a clock signal input means for inputting a clock signal from the clock signal line; The identification control means outputs the clock signal output from the clock signal output means to the clock signal line when the identification is made as the master, and outputs the clock signal output when the identification is made as the slave. Preferably, output from the means to the clock signal line is stopped.

Further, when the output line of the timing signal output means is attached to a connector connected to the timing signal line, it is preferable that the two timing signals match.

Further, when the output line of the timing signal output means is attached to a connector that is not connected to the timing signal line, it is preferable that the two timing signals do not match.

According to a fifth aspect of the present invention, there is provided a data output method according to the first aspect, wherein at least one of the plurality of data output devices is transmitted from the data output device according to a timing signal transmitted via a timing signal line connected between the external device and the external device. A data output method for serially outputting data to the external device, comprising: outputting the timing signal; inputting a timing signal from the timing signal line; and outputting the output timing signal and the timing signal line. Comparing the timing signal with the timing signal input from the controller; and, as a result of the comparison, outputting the timing signal to the timing signal line when both timing signals match and are identified as a master. As a result, if both timing signals do not match and it is identified as a slave, A step of stopping the output of said timing signal to Line, characterized in that a step of transmitting the data according to the timing signal.

When a plurality of data output devices of the present invention are connected to an external device, the data output device compares the timing signal output from the timing signal output means with the timing input from the timing signal line, and compares both the timing signals. Are matched and identified as a master, a timing signal is output to the timing signal line to operate as a master. On the other hand, if the two timing signals do not match and are identified as a slave, the device operates as a slave by inputting a timing signal from the timing signal line. Therefore, all data output devices output data to an external device according to the same timing signal.

Thus, the load on the data receiving process of the external device on the data receiving side can be reduced. Further, since the data output device can be automatically set as a master or a slave simply by connecting to an external device without previously setting the data output device as a master or a slave, installation work can be simplified. Further, the number of signal lines connected to the external device can be reduced, and further wiring reduction can be realized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data output device and method according to the present invention will be described. The data output device of the present embodiment is applied to a measuring device (counter) that counts pulse signals output from a gauge for measuring a displacement amount and outputs measurement data to an external device such as a sequencer.

FIG. 1 is a diagram showing a configuration of a counter according to the embodiment. The counter 11 includes a connector 21 to which a connector attached to a signal line connected to a device such as a gauge 14, a printer 16 or a presetter 18 is removably mounted, and a connected device identification for identifying a device connected to the connector 21. A circuit 23, an input / output switching circuit 26 for switching input / output in accordance with the identified device, a counting circuit 28 for counting pulse signals output from the gauge 14, and calculating a difference between the counted value and a target value as an output value. Arithmetic circuit 3
1. A printer output circuit 33 for outputting data such as output values to the printer 16, a display 35 for displaying data such as output values, and a destination of the count value and the output value. , An output selector 37 for performing a tolerance determination of the output value, a BCD for converting the output value to BCD data
Output circuit 40, connector 41 for outputting the converted BCD data to the outside, output value (digital output data)
A resolution setting circuit 44 for setting the resolution to change the gain of the D / A converter, a D / A conversion circuit 45 for converting the digital output data into an analog output voltage, and a plurality of target value setting registers 47 (a plurality of target values are respectively set). 1 to n), a selector 49 for selecting any of the plurality of target value setting registers 47 (1 to n), and each of the target value setting registers 47 (1 to n).
Set value input circuit 5 for inputting a target value set in n)
1 and a selection input circuit 54 for selectively receiving an instruction (RS232C, external selection signal, key input) from an external device.

The gauge 14 connected to the connector 21 of the counter 11 outputs a displacement amount as a pulse signal when the tip of the gauge 14 is displaced by contacting the work. As such a gauge, for example, a resolution 1
μm, a measurement range of 10 mm, and an output pulse number of 10 / μm. The gauge is not limited to one that outputs a number of pulse signals corresponding to the amount of displacement, one that outputs a pulse signal having a cycle corresponding to the amount of displacement, or one that outputs the amount of displacement itself as digital data. Can be used.

The printer 16 connected to the connector 21 of the counter 11 prints measurement data, and various types such as a thermal transfer type, a dot impact type, and an ink jet type can be used.

The presetter 18 connected to the connector 21 of the counter 11 has a target value setting register 47.
A target value is set to (1 to n), and a numeric keypad or the like is arranged on the front surface thereof.

The BCD output circuit 40 of the counter 11
4 for outputting BCD data converted by
1 is connected to an external device such as a sequencer, which is a control device for performing automatic measurement. The connection with the sequencer will be described later. Note that a personal computer may be used instead of the sequencer as a control device for performing automatic control.

FIG. 2 is a diagram showing a configuration of the BCD output circuit. The BCD output circuit 40 generates a clock signal and outputs the clock signal to a clock signal line 61, a clock (CK) output circuit 62, a clock (CK) input circuit 63 that inputs a clock signal from the clock signal line 61, and a strobe signal (ST).
B_OUT) to generate a strobe signal line (STB1)
65 strobe signal (STB) output circuit 6
6. A strobe signal (ST) for inputting a strobe signal (STB_IN) from a strobe signal line (STB2) 67
B) It has an input circuit 69, a master / slave identification circuit 71, and a data (DATA) output circuit 72.

The output of the CK output circuit 62 and the clock (C
K) between the signal line and between the input of the CK input circuit 63 and the clock (CK) signal line.
3, 74 are provided. Also, the STB output circuit 66
Is provided between the strobe signal line (STB1) 65 and the output of the buffer 75. Similarly, the input of the STB input circuit 69 and the strobe signal line (STB2) 67
A buffer 76 is also provided between. further,
A buffer 78 is also provided between the output of the DATA circuit 72 and the data signal line 77.

The master / slave identification circuit 71
The strobe signal (STB_) output from the output circuit 66
OUT) and a strobe signal (STB_IN) from a strobe signal line (STB2) 67.
Strobe signals (STB_OUT), (STB_I
N), the counter 11 identifies whether it is a master or a slave.

When the master / slave identification circuit 71 identifies the master, the CK output circuit 62 and the STB
An active master output signal is output to the output circuit 66 to make it active, and the CK input circuit 63 and the STB input circuit 69 are made inactive by outputting inactive slave output signals. On the other hand, when the master / slave identification circuit 71 identifies the slave, the master / slave identification circuit 71 outputs an active slave output signal to the CK input circuit 63 and the STB input circuit 69 to activate the CK output circuit 62 and the STB output circuit 66. Output an inactive master output signal to deactivate it.

FIG. 3 is a diagram showing the configuration of the master / slave identification circuit 71. The master / slave identification circuit 71
It comprises a comparator 82 and a latch circuit 84. The comparator 82 compares the two input strobe signals (STB_OUT) and (STB_IN) and outputs the same to the latch circuit 84. The latch circuit 84 outputs a master output signal and a slave output signal according to the comparison output signal from the comparator 82. Generate

Next, the operation when a plurality of counters having the above-described configuration are connected to a sequencer and installed will be described. FIG. 4 is a diagram showing connection of signal lines when a plurality of counters are connected to the sequencer. Here, a case where two counters are connected to the sequencer is shown for simplicity of explanation. Input terminals P0 and P of sequencer 91
, P2, P3,..., Pn
Are provided with a plurality of connectors 92a and 92b corresponding to the number of the counters 11, respectively.
By attaching the connector 41 of the counter 11 to the connector 92 b, the plurality of counters 11 are connected to the sequencer 91.

Among the plurality of connectors, the master connector 92a includes a clock signal line, an STB1 signal line, and an STB signal line.
Two signal lines and data lines are connected. In the master connector 92a, the STB1 signal line and the STB2 signal line are short-circuited. Other slave connector 92
b, a clock signal line connected to the clock signal line of the master connector 92a;
The STB2 signal line connected to the TB2 signal line and the data line reaching the input terminal P3 of the sequencer 91 are connected.

Therefore, in the counter 11 to which the master connector 92a is attached, the clock signal line STB1
Three signal lines and data lines are connected to the input terminals P0, P1, and P2 of the sequencer 91, respectively.
On the other hand, in the counter 11 to which the slave connector 92b is attached, only one of the data lines is connected to the input terminal P3 of the sequencer.

FIG. 5 is a timing chart showing changes in signals of the master / slave discriminating circuit when connectors of the respective counters are mounted on the master connector and the slave connector. Counter 1 is connected to master connector 92a.
1 is connected, the master connector 92a
Since the TB1 signal line and the STB2 signal line are short-circuited, the STB1 signal (STB_OUT) output from the STB output circuit 66 and the STB2 signal input from the strobe signal line (STB2) as shown in FIG. (S
TB_IN) are in-phase signals. Therefore, the comparison output of the comparator 82 to which these signals have been input becomes L level, an L level master output signal indicating active is output from the Q terminal of the latch circuit 84, and the CK output circuit 62 and the STB output circuit 66 is input. On the other hand, an H level slave output signal indicating inactive is output from the * Q terminal of the latch circuit 84, and the CK input circuit 63 and the STB input circuit 69
Is input to As a result, the counter 11 connected to the master connector 92a activates the CK output circuit 62 to output a clock signal to the clock signal line 61, and activates the STB output circuit 66 to output a strobe signal to the strobe signal line 65. (STB1) is output.

Next, when the counter 11 is connected to the slave connector 92b, the slave connector 92b
, The strobe signal (STB1) line 65 is open (unused), and the strobe signal (STB2) line 67 is connected to the strobe signal (STB) of the master connector 92a.
B2) Since they are connected to the line 67, the STB1 signal (STB_OUT) and the STB2 signal (STB_IN) output from the STB output circuit 66 as shown in FIG.
Means signals having different phases. Therefore, the comparator 82 to which these signals are input generates an H-level pulse signal as a comparison output. The latch operation is performed by this H level pulse signal, and the latch circuit 8
A master output signal of H level indicating inactive is output from the Q terminal of No. 4 and input to the CK output circuit 62 and the STB output circuit 66. On the other hand, an L-level slave output signal indicating active is output from the * Q terminal of the latch circuit 84 and input to the CK input circuit 63 and the STB input circuit 69. As a result, the counter 11 connected to the slave connector 92b reads C
The K input circuit 63 is operated to input a clock signal from the clock signal line 61, and the STB input circuit 69 is operated to operate the STB2 signal (S
TB_IN).

According to the STB2 signal (STB_IN) input from the strobe signal line 67, the BC
The data output circuit 72 in the D output circuit 40 determines the start of data transmission, and synchronizes with the clock signal to the data line 77.
Output data to At this time, since all the counters 11 output data in synchronization with the same clock signal, the sequencer 91 on the data receiving side outputs
Data can be simultaneously received from the plurality of counters 11 in synchronization with the clock signals input via the input terminals P0 and P3 of each data line.

FIG. 6 is a timing chart showing changes in signals at various parts of the BCD output circuit. In the BCD output circuit 40, when the start of data transmission is instructed at the rise of the strobe signal (STB_IN), the hold (H
OLD) signal goes low and data is held.
Then, the data acquired in synchronization with the rise of the clock (CK) signal is output to the data signal line 77. 6
One set of data including BCD data for one digit is transmitted as one cycle from the rising of the strobe signal (STB_IN) to the rising of the next strobe signal (STB_IN).

FIG. 7 is a diagram showing the format of a set of data to be transmitted. In the present embodiment, one set of data is composed of 32 bits, of which BC digits of 6 digits are included.
The D data (D1 to D6) has 24 bits (= 4 bits ×
6 digits). The four bits of the D7 data are used as a switch bit and a sign (SIGN) bit of a bank memory (BANK). Here, BANK indicates a target value setting register 47 in which a target value is set, and eight B bits are set by the upper three bits.
ANK, that is, eight target value setting registers 47 can be selected. For example, in BANK0, that is, in the target value setting register 47 (1), two target values for performing three tolerance determinations of -NG, OK, and NG are set. In addition, BANK1 to BANK7, that is, the target value setting register 47
(2-8) include -NG, -NG, OK, + NG, +
Four target values for performing five tolerance determinations of + NG are set. Further, the sign (SIGN) bit determines the plus or minus sign of each target value.

The remaining 4 bits of the D8 data are a group of bits indicating the mode (MODE1, MODE2), the presence / absence of a hold (HOLD) signal, and the error / normal (NOM). The type of data, that is, the current value and the maximum value (MA)
X), the minimum value (MIN), and the difference (TIR).

As described above, in the present embodiment, when the installation work for connecting a plurality of counters 11 to one sequencer 91 is performed, the signal lines 94 are provided at the end of the signal line group 94 connected to the sequencer 91. When the connector 41 of the counter 11 is attached to the master connector 92a among the plurality of connectors, it functions as a master counter, and the other connectors 4b of the counter 11 are attached to the slave connectors 92b.
When 1 is attached, it functions as a slave counter.
Therefore, the operator does not need to set the counter to the master or the slave in advance, and can easily install the counter.

Signal lines other than the data lines connected from the counter 11 to the sequencer 91 include a clock signal line 61 and a strobe signal line (STB) from the master counter.
1) Only two lines of 65 can be used, and wiring can be reduced compared to the case where these signal lines are wired from all the counters 11. Further, since the sequencer 91 can acquire the data output from all the counters 11 at once in synchronization with the same clock signal, it is possible to reduce the load of the data fetching process on the sequencer side.

Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations of the embodiments, and the functions described in the claims or the configurations of the embodiments are not limited to the embodiments. Any configuration can be applied as long as it has the function that it has. For example, in the above embodiment, the strobe signal line (ST
B1) is open (unused), but may be connected to the strobe signal line (STB1) of the master connector. In this case, the connector has no distinction between master and slave, and the counter connected to the first connector becomes the master counter and the strobe signal line (STB1).
, The counter connected to the next connector can be set as a slave.

[0035]

According to the present invention, when data transmission is performed by connecting to an external device such as a sequencer, the processing load on the data receiving side can be reduced, and installation can be simplified while saving. Wiring can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a counter according to an embodiment.

FIG. 2 is a diagram illustrating a configuration of a BCD output circuit.

FIG. 3 is a diagram showing a configuration of a master / slave identification circuit.

FIG. 4 is a diagram illustrating connection of signal lines when a plurality of counters are connected to a sequencer.

FIG. 5 is a timing chart showing changes in signals of a master / slave identification circuit when connectors of respective counters are mounted on a master connector and a slave connector.

FIG. 6 is a timing chart showing a change in a signal in each section of the BCD output circuit.

FIG. 7 is a diagram showing the format of a set of data to be transmitted.

[Explanation of symbols]

 11 Counter 40 BCD output circuit 41, 92a, 92b Connector 62 Clock (CK) output circuit 63 Clock (CK) input circuit 66 Strobe signal (STB) output circuit 69 Strobe signal (STB) input circuit 71 Master / slave identification circuit 72 Data (DATA) output circuit 82 comparator 84 latch circuit 91 sequencer 94 signal line group

Claims (5)

[Claims] 1. A data output device that serially outputs data to an external device according to a timing signal transmitted via a timing signal line connected between at least one of a plurality of data output devices and an external device. Timing signal output means for outputting the timing signal; timing signal input means for inputting a timing signal from the timing signal line; timing signal input from the timing signal line and output from the timing signal output means A timing signal is compared with a timing signal, and when both timing signals match and it is determined that the master is a master, the timing signal output from the timing signal output means is output to the timing signal line, If they do not match and are identified as slaves, A data output device comprising: master / slave identification control means for stopping output from a timing signal line to a timing signal line; and data transmission means for transmitting the data in accordance with the timing signal. 2. The transmission of data output in synchronization with a clock signal transmitted via a clock signal line connected between at least one of a plurality of data output devices and the external device. A strobe signal for instructing start, comprising: a clock signal output unit that outputs the clock signal toward the clock signal line; and a clock signal input unit that inputs a clock signal from the clock signal line. The identification control means outputs the clock signal output from the clock signal output means to the clock signal line when the identification is made as the master, and outputs the clock signal output when the identification is made as the slave. 2. The data output device according to claim 1, wherein output from said means to said clock signal line is stopped. . 3. The data output device according to claim 1, wherein when the output line of the timing signal output means is attached to a connector connected to the timing signal line, the two timing signals match. . 4. The data output device according to claim 1, wherein when the output line of the timing signal output means is attached to a connector that is not connected to the timing signal line, the two timing signals do not match. . 5. Serially outputting data from the data output device to the external device according to a timing signal transmitted via a timing signal line connected between at least one of the plurality of data output devices and the external device. Outputting the timing signal; inputting a timing signal from the timing signal line; and comparing the output timing signal with a timing signal input from the timing signal line. Outputting the timing signal to the timing signal line if both timing signals match as a result of the comparison and being identified as a master; and, as a result of the comparison, the two timing signals do not match. When it is identified as a slave, the timing signal is sent to the timing signal line. Data output method characterized by comprising the step of stopping power, and a step of transmitting the data according to the timing signal.