JP2001306491A - Circuit and method for transferring data between asynchronous systems - Google Patents

Abstract

PROBLEM TO BE SOLVED: To guarantee the normal transfer of data and also to improve the data transfer efficiency. SOLUTION: A circuit 16 is set at the same time when the data are set at a transmitting register 14. The transmitting register effective flags outputted from the circuit 16 are set at FF circuits 18-24 and 56-60 respectively, and the output signals of an FF circuit 58 are set at FF circuits 34-38. Five transmitting register set signals are outputted in response to the output signals of FF circuits 18-24, 36 and 38 respectively, and the data on the register 14 are set at a receiving register 54 in response to the output signals of FF circuits 58 and 60. One of those five reset signals is selected by the selection signal sent from a clock ratio detection circuit 66 and the circuit 16 is reset by the selected selection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous inter-system data transfer circuit and an inter-asynchronous data transfer method, and more particularly, to guaranteeing normal data transfer between data buses operating asynchronously. The present invention relates to an asynchronous data transfer circuit and an asynchronous data transfer method capable of efficiently transferring data.

[0002]

2. Description of the Related Art Some computer systems include a plurality of buses for transferring data between circuits constituting the computer system. In this type of computer system, there is a computer system in which a bus bridge circuit is provided between buses to transfer data between buses. For example, a bus bridge circuit is provided between a peripheral bus connecting the central processing unit and the peripheral device and a local bus provided inside the peripheral device, and data is transferred between the two buses.

The reason for providing this bus bridge circuit is that the bus specifications of the peripheral bus and the local bus are different from each other,
This is to absorb the difference in the bus specifications, for example, the difference in the frequency of the clock used in each bus. Such a technical problem also occurs in data transfer between registers having different operating frequencies.

For example, when the operating frequency of the transmitting / receiving circuit as shown in FIG. 11, that is, the clock frequency is different between the transmitting side and the receiving side, data is transmitted between the register of the transmitting side circuit and the register of the receiving side circuit. The asynchronous inter-system data transfer circuit 100 for transferring the
2, a transmission-side register 101 and a transmission-side register valid flag circuit (flip-flop circuit (FF)) 105
, Flip-flop circuits 107 to 113, and an AND circuit 115 are provided, and the reception-side circuit portion 104 includes a reception-side register 103 and flip-flop circuits 117 to 117.
121, an AND circuit 123, and a receiving-side output data valid flag circuit (flip-flop circuit) 125 are provided.

The transmission-side input data is set in the transmission-side register 101 in response to a transmission-side clock when a data transmission request signal is input to the transmission-side register 101.
Simultaneously with this setting, the transmission side register valid flag circuit 105 responding to the data transmission request signal and the transmission side clock
Is set, and the transmission side register valid flag 106 is sent out from the transmission side register valid flag circuit 105. The transmission-side register valid flag 106 is supplied to the data transmission source as a data transmission suppression signal. The transmission of the next data is suppressed until the transmission of the transmission-side register valid flag 106 is stopped.

The transmitted-side register valid flag 10
6 is a flip-flop circuit 1 in response to the sequential reception clock after the transmission register valid flag 106 is transmitted.
17 to 121 are sequentially set. Output signals of the flip-flop circuits 119 and 121 are supplied to an AND circuit 123. The receiving-side register set signal 124 is output from the AND circuit 123 and supplied to the receiving-side register 103. Data 101A appearing at the output of the transmitting register 101 is set in the receiving register 103 in response to the receiving clock applied to the receiving register 103 after the supply.

Flip-flop circuits 107 to 113 and an AND circuit 115 are provided to generate the time until this data is set in the reception-side register 103, and the reception-side register 103 of the transmission-side input data is provided.
Upon completion of the setting, the transmission-side register reset signal is output from the AND circuit 115, and the transmission-side register valid flag circuit 105 is reset. When the transmission-side register validity flag circuit 105 stops transmitting the transmission-side register validity flag, the data transmission source cancels the transmission of the data that has been suppressed by the transmission-side register validity flag and starts transmitting the next data. Is done.

Simultaneously with the setting of the transmission-side input data in the reception-side register 103, the reception-side register set signal 124 and the reception-side output data valid flag circuit 125 responding to the reception-side clock are set, and the reception-side output data validity is set. The flag is the output data valid flag circuit 125 on the receiving side.
Sent from. The transmitted reception-side output data valid flag is supplied to the reception processing unit that receives the data set in the reception-side register 103. After the reception process is completed, the reception-side output data valid flag circuit 125 is reset by a data reception completion signal transferred from a data reception completion signal generation circuit (not shown), and the reception processing unit waits for reception of the next reception data. enter.

A circuit shown in FIG. 12 is known as such an asynchronous data transfer circuit. The asynchronous inter-system data transfer circuit 100 shown in FIG. 11 is a circuit in which a signal source for generating a transmission-side register reset signal is provided in the transmission-side circuit portion 102, whereas the asynchronous inter-system data transfer circuit shown in FIG. Reference numeral 200 denotes a handshake type asynchronous inter-system data transfer circuit in which a signal source for generating a transmitting-side register reset signal is placed in the receiving-side circuit portion 204. The other configuration and operation are the same as those shown in FIG. It is almost the same as the transfer circuit 100. That is, the generation of the transmission-side register reset signal requires the reception-side circuit portion 204
The output signal of the flip-flop 217 is received by the flip-flop 207, and the signal is set in the flip-flop circuits 207 to 211 with the sequential transmission side clock,
Then, the flip-flop 209,
There is a great difference from the asynchronous inter-system data transfer circuit 100 shown in FIG. 11 in that the transmission-side register reset signal is generated in response to the output signal of 211.

[0010]

In the above-mentioned asynchronous inter-system data transfer circuit 100, the flip-flop circuit 107 is used.
And the AND circuit 115, and in the asynchronous intersystem data transfer circuit 200, the flip-flop circuit 2
07 to 211 and the AND circuit 213 are controlled so that the data in the transmission-side registers 101 and 201 is maintained for a certain period of time or longer. The transmission side registers 101 and 20
The data holding for a certain period of time or more is performed by the transmission side registers 101 and 201 from the reception side registers 103 and 203.
Transfer of data to the receiving side registers 103 and 2
If the data in the transmission-side registers 101 and 203 changes at a timing at which the setup time and the hold time of 03 cannot be satisfied, the contents of the data set in the reception-side registers 103 and 203 cannot be guaranteed. From the receiving side registers 101 and 201 to the receiving side register 10
This is a circuit operation performed in order to correctly transfer data to 3,203.

The holding time during which data is held for a fixed time by this circuit operation is a time determined in advance by the frequency of the operating clock of the receiving register, the setup time and the holding time of the receiving register, clock skew, and the like.

When the clock frequency of the data transmission side and the clock frequency of the data reception side are not fixed, for example, the clock frequency of the data transmission source transmitting the data on the transmission side may be different from that of the system. If the technique according to the asynchronous inter-system data transfer circuit 100 shown in FIG. 11 is to be applied as it is when the operation is started at the start of the operation, the clock frequency of one or both of the transmission side and the reception side is changed. When there is a change or change in the clock frequency, no matter what value the clock frequency takes within the clock frequency range, it becomes necessary to secure the above-mentioned holding time. , The holding time is appropriate, but the time required to hold the data in the transmitting register at other clock frequencies is required It becomes long on top, as a result, occurs inconvenience that reduces the data transfer performance.

When the clock frequency on the data transmission side and the clock frequency on the data reception side are not fixed, the technique relating to the asynchronous intersystem data transfer circuit 200 shown in FIG. If this is attempted, data transfer between registers operating at an arbitrary clock frequency ratio can be performed more reliably than the asynchronous inter-system data transfer circuit shown in FIG. As compared with the transfer circuit 100, the time required to generate the transmission-side register reset signal is increased by the amount of time required to ensure the transfer of the data, so that the time required for the data transfer is lengthened accordingly. Is disadvantageously reduced.

The present invention has been made in view of such technical problems, and always guarantees normal data transfer between asynchronous systems in which the clock frequency of a data transmitting device and the clock frequency of a data receiving device are not fixed. It is an object of the present invention to provide a data transfer circuit between asynchronous systems and a data transfer method between asynchronous systems which can improve data transfer efficiency.

[0015]

According to an aspect of the present invention, there is provided a data transmitting apparatus which operates to transmit at a first timing and receives at a second timing different from the first timing. An inter-asynchronous data transfer circuit that is interposed between an operating data receiving device and that transfers data from the data transmitting device to the data receiving device for each transfer unit, and that receives data input from the data transmitting device. A data holding circuit for temporarily holding the data in a transfer unit; outputting a data holding valid signal at a timing having a predetermined relationship with the first timing when the data is held in the data holding circuit; A signal is supplied to the data transmission device to suppress the transfer of the next data, and the output of the data holding valid signal is stopped when the reset signal is supplied. And when the timing is changed from the output time of the data holding valid signal upon receipt of the data holding valid signal, the data is transmitted from the data holding circuit to the data holding circuit. Generating a reset signal corresponding to the changed timing at a time when a predetermined time elapses until the data is normally transferred to the receiving device in a transfer unit, and generating a reset signal for supplying the reset signal to the first circuit; When the output of the data holding valid signal is stopped from the first circuit by the supply of the reset signal, the suppression is released and the next data is sent from the data transmitting device to the data holding circuit. It is characterized by being transferred.

According to a second aspect of the present invention, there is provided the asynchronous inter-system data transfer circuit according to the first aspect, wherein the reset signal generating circuit includes a pair of the first timing and the second timing which can be changed. A reset signal candidate generating circuit for generating a corresponding reset signal candidate; a select signal output circuit for outputting a select signal corresponding to each pair of the first timing and the second timing; A selection circuit that selects a reset signal candidate corresponding to the selection signal output from the selection signal output circuit from among the reset signal candidates output from the circuit, and outputs the selected reset signal as a reset signal. And

According to a third aspect of the present invention, there is provided the data transfer circuit according to the second aspect, wherein the reset signal candidate generating circuit and the selecting circuit are constituted by fixed logic circuits. And

According to a fourth aspect of the present invention, there is provided the data transfer circuit according to the second aspect of the present invention, wherein the reset signal candidate generating circuit and the selection circuit include configuration data storage means for storing configuration data; And a circuit capable of setting a logic corresponding to the configuration data read from the configuration data storage means.

According to a fifth aspect of the present invention, there is provided the data transfer circuit between asynchronous systems according to the second, third or fourth aspect, wherein the selection signal output circuit includes a clock frequency of the data transmission device and a clock frequency of the data reception device. , And supplies a selection signal corresponding to the detected ratio to the selection circuit.

According to a sixth aspect of the present invention, there is provided the data transfer circuit according to the second, third or fourth aspect, wherein the selection signal output circuit is connected to a transmission side bus and outputs a standard change signal. And a circuit for supplying a selection signal corresponding to the standard change signal supplied from the controller via the transmission-side bus to the selection circuit.

The invention according to claim 7 relates to the data transfer circuit between asynchronous systems according to claim 2, 3 or 4, wherein the selection signal output circuit is connected to a transmission side bus and outputs an operation mode signal. And a circuit for supplying a selection signal corresponding to the operation mode signal supplied from the controller via the transmission-side bus to the selection circuit.

[0022] Further, the invention described in claim 8 is based on claim 2,
In the data transfer circuit between asynchronous systems according to 3 or 4, the selection signal output circuit is a changeover switch that outputs a reset signal output by switching, and the selection signal output by switching the changeover switch is a selection signal. Is supplied to the selection circuit.

According to a ninth aspect of the present invention, there is provided an asynchronous inter-system data transfer circuit according to any one of the first to eighth aspects.
The setting of the data in the first circuit is performed based on the clock of the data transmission device, and the generation of the reset signal in the reset signal generation circuit is performed in accordance with the clock of the data transmission device and the clock of the data transmission device. The operation is performed based on one of a clock and a clock of the data receiving apparatus.

According to a tenth aspect of the present invention, there is provided the asynchronous inter-system data transfer circuit according to the first aspect, wherein the reset signal generating circuit is configured to control the changeable first timing and the second timing.
A first signal generation circuit that generates an enable signal for a pair to be changed among pairs of timings and a prohibition signal for a pair that is not to be changed, and outputs a prohibition signal for each pair. And a reset signal output corresponding to the inhibit signal supplied from the first signal generation circuit. And a second signal generation circuit for generating a reset signal at a reset signal output corresponding to the permission signal supplied from the first signal generation circuit, and a separate output of the second signal generation circuit. And an output circuit for outputting only the generated reset signal.

According to an eleventh aspect of the present invention, there is provided the inter-asynchronous data transfer circuit according to the tenth aspect, wherein the first signal generating circuit includes a clock frequency of the data transmitting device and a clock frequency of the data receiving device. When the detected ratio is a change target, an enable signal is output to the output corresponding to the change target, and when the detected ratio is a change non-target, the enable signal is prohibited to the output corresponding to the change non-target. It is characterized by generating a signal.

According to a twelfth aspect of the present invention, there is provided the data transfer circuit according to the tenth aspect, wherein the first signal generation circuit is connected to a transmission-side bus and outputs a standard change signal. A signal conversion circuit connected to the transmission-side bus, and when the standard change signal output from the controller is to be changed, the signal conversion circuit
The signal conversion circuit outputs a permission signal to an output corresponding to the change target, and outputs a prohibition signal to an output corresponding to the non-change target when the standard change signal is non-change target.

According to a thirteenth aspect of the present invention, there is provided the data transfer circuit according to the tenth aspect, wherein the first signal generation circuit is connected to a transmission side bus and outputs an operation mode signal. A signal conversion circuit connected to the transmission side bus, wherein when the standard change signal output from the controller is a change target, the signal conversion circuit outputs a permission signal to an output corresponding to the change target, and the standard change signal The signal conversion circuit outputs a prohibition signal to an output corresponding to a non-change target when is not a change target.

According to a fourteenth aspect of the present invention, there is provided the data transfer circuit according to the tenth aspect, wherein the first signal generating circuit is a changeover switch for outputting a reset signal output by switching. An enable signal is output to an output corresponding to a change target of the changeover switch, and a prohibition signal is output to an output corresponding to a nonchangeable change of the changeover switch.

The invention according to claim 15 relates to the data transfer circuit between asynchronous systems according to any one of claims 10 to 14, wherein the second signal generation circuit and the output circuit are fixed logic circuits. It is characterized by being composed.

According to a sixteenth aspect of the present invention, there is provided the data transfer circuit according to any one of the tenth to fourteenth aspects, wherein the second signal generating circuit and the output circuit store configuration data. It is characterized by comprising a configuration data storage means and a circuit capable of setting a logic corresponding to the configuration data read from the configuration data storage means.

The invention as defined in claim 17 is based on claims 1 and 1
In the data transfer circuit between asynchronous systems according to any one of 0 to 16, the setting of the data in the first circuit is performed based on a clock of the data transmission device, and the setting of the data in the reset signal generation circuit is performed. The generation of the reset signal is performed based on one of a clock of the data transmission device, a clock of the data transmission device, and a clock of the data reception device.

According to the present invention, the data is transmitted for each transfer unit from the data transmitting apparatus which performs the transmitting operation at the predetermined first timing to the data receiving apparatus which performs the receiving operation at the second timing different from the first timing. When the data to be transferred is held in the data holding means of the data transmitting device from the data sending means of the data sending device, the data is transferred from the data holding means to the data receiving device. During a predetermined time until the data is normally transferred in units, the transfer of the next data from the data sending means to the data holding means is suppressed, and when the required time has elapsed, the suppression is released, When the inhibition is released, the next data is transmitted from the data transmission means to the data holding means in a transfer unit, and the next data is transferred. According to the asynchronous inter-system data transfer method to be started, when the timing is changed, the predetermined time is changed to a time corresponding to the changed timing, and the inhibition is released when the changed time elapses. The next data is transmitted from the data transmitting device to the data receiving device in units of transfer by causing the data transmitting unit to store the next data in the data holding unit.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. FIG. 1 is a block diagram of a data transfer circuit between asynchronous systems according to a first embodiment of the present invention, and FIG. 2 is a diagram showing a PCI of a computer system having the data transfer circuit between asynchronous systems. FIG. 3 is a schematic configuration diagram of the bus bridge circuit, FIG. 3 is an operation timing chart of the asynchronous inter-system data transfer circuit when the transmission / reception clock frequency ratio is a predetermined value, and FIG.
FIG. 5 is an operation timing chart of the asynchronous inter-system data transfer circuit when the frequency of the transmission-side clock in the operation timing chart shown in FIG.
5 is an operation timing chart showing selection of a transmission-side register reset signal different from that of FIG. 4 at the operation timing of FIG. 4.

Asynchronous data transfer circuit 1 of this embodiment
0 is a case where the clock frequency of the transmitting side and the clock frequency of the receiving side are not fixed, and in the bus bridge circuit where the ratio of both clock frequencies is five, the data transfer is always performed while the normal data transfer is guaranteed. According to a circuit capable of improving the efficiency, a transmission side circuit portion 12 of the circuit includes a transmission side register 14, a transmission side register valid flag circuit (flip-flop circuit (FF)) 16, and flip-flop circuits 18 to 24. And AND circuits 26-3
2, a flip-flop circuit 34 to 38, an AND circuit 40, and a selector 42, and the receiving circuit portion 52 includes a receiving register 54, flip-flop circuits 56 to 60, an AND circuit 62, Reception-side output data valid flag circuit (flip-flop circuit (FF)) 64
It is composed of

The flip-flop circuit 18 of the transmission-side circuit portion 12 is connected to the output of the transmission-side register valid flag circuit 16, and the flip-flop circuits 18 to 24 are connected in series in this order to sequentially transmit the transmission-side register valid flag. Set sequentially in response to the transmitting clock. The transmission side clock is transferred from the PCI bus 72 (FIG. 2) to the data transfer unit 82 via the PCI bus interface unit 78, and is supplied to the asynchronous intersystem data transfer circuit 10.

The flip-flop circuit 56 of the reception-side circuit portion 52 is connected to the output of the transmission-side register valid flag circuit 16, and the flip-flop circuits 56 to 60
The transmission-side register validity flags output from the transmission-side register validity flag circuit 16 are serially connected in this order, and are sequentially set in response to successive reception-side clocks. The receiving clock is transferred from the local bus 74 (FIG. 2) to the data transfer unit 82 via the local bus interface unit 84, and is supplied to the asynchronous intersystem data transfer circuit 10.

The AND circuit 26 receives the transmission-side register validity flag output from the transmission-side register validity flag circuit 16 and the output signal of the flip-flop circuit 18 at its inputs, and outputs the output signal to the first transmission-side register. The reset signal 27 is supplied to the selector 42. AND circuit 2
8 receives the output signal of the flip-flop circuit 18 and the output signal of the flip-flop circuit 20 at its input, and supplies the output signal to the selector 42 as a second transmission-side register reset signal 29. The AND circuit 30 receives the output signal of the flip-flop circuit 20 and the output signal of the flip-flop circuit 22 at its inputs, and supplies the output signal to the selector 42 as the third transmission-side register reset signal 31. The AND circuit 32 receives the output signal of the flip-flop circuit 22 and the output signal of the flip-flop circuit 24 at its inputs, and supplies the output signal to the selector 42 as a fourth transmission-side register reset signal 33.

The flip-flop circuit 34 is connected to the output of the flip-flop 56,
4 to 38 are connected in series in this order,
The output signals of the two flip-flop circuits 58 are sequentially set in response to the sequential transmission side clocks. AND circuit 40
Receives the output signal of the flip-flop circuit 36 and the output signal of the flip-flop circuit 38 at its input, and supplies the output signal to the selector 42 as a fifth transmission-side register reset signal 41.

The selector 42 includes a clock ratio detection circuit 66
Receives the select signal output from the select input. The clock ratio detection circuit 66 is determined according to the ratio between the clock frequency on the transmission side and the clock frequency on the reception side among the five select signals according to the ratio between the clock frequency on the transmission side and the clock frequency on the reception side. One of the select signals is output. Therefore, the selector 42
In response to the supplied select signal, one of the transmission-side register reset signals output from each of the AND circuits 26 to 40 is selected and the selected transmission-side register reset signal is transmitted to the transmission-side register valid flag circuit 16.
To supply.

The AND circuit 62 receives the output signal of the flip-flop circuit 58 and the output signal of the flip-flop circuit 60 at its input, and outputs the output signal, that is, the receiving register set signal 63 to the receiving register 54 and the receiving register 54. It is supplied to the set input of the side output data valid flag circuit 64. The receiving-side output data valid flag circuit 64 is set in response to the receiving-side clock after receiving the receiving-side register set signal at its set input, and sends out the receiving-side output data valid flag to its output. The data reception completion signal output from the reception completion signal generation circuit is reset in response to a receiving clock after receiving the data reception completion signal at its reset input.

The asynchronous data transfer circuit 10 shown in FIG.
Will be described with reference to FIG. FIG. 2 illustrates the PCI in the computer system.
A bus 72 (corresponding to the peripheral bus described in the section of "Prior Art"; hereinafter, also referred to as a PCI bus or the like including connection of the central processing unit to the PCI bus 72) and a local bus 74 (hereinafter, peripheral device). Is also referred to as a local bus including the connection to the local bus 74.) A PCI bus bridge circuit 76 for controlling the transfer of data, addresses, control signals, and the like to and from the local bus 74 is shown. Is provided with an asynchronous data transfer circuit 10.

The PCI bus bridge circuit 76 shown in FIG.
PCI bus interface unit 78 connected to CI bus 72 (corresponding to the peripheral bus described in the section of "prior art")
And a PC connected to the PCI bus interface unit 78
An I register 80, a data transfer unit 82 connected to the PCI bus interface unit 78, a local bus interface unit 84 connected to the data transfer unit 82, and a local bus register 86 connected to the local bus interface unit 84. Be composed.

The PCI bus interface unit 76 includes a PC
This circuit takes an interface between the I bus 72 and the PCI bus bridge circuit 76, and executes bus transaction issue control, bus transaction reception control, data transmission control, data reception control, and the like with the PCI bus 72. The PCI register 80 is a group of registers that can read from and write to the PCI bus 72, and stores setting information and the like as a PCI bus device.

The local bus interface 84 is a group of registers that can read from and write to the local bus 74, and stores setting information and the like as a local bus device.

The data transfer section 82 is a circuit for mutually transferring data between the PCI bus interface section 78 and the local bus interface section 84. The data transfer section 82 has therein the asynchronous inter-system data transfer circuit 10 shown in FIG. Is provided. A bus clock ratio detection circuit 66 is connected to the asynchronous intersystem data transfer circuit 10. The bus clock ratio detecting circuit 66 detects the ratio between the frequency of the clock for operating the PCI bus 72 and the frequency of the clock for operating the local bus 74, and outputs a select signal corresponding to the detected clock frequency ratio to the asynchronous transfer circuit 10. Selector 42
(FIG. 1).

Next, the operation of this embodiment will be described with reference to FIGS. When data transfer from the PCI bus 72 to the local bus 74 in FIG. 2 is performed, control of the data transfer is applied from the PCI bus interface unit 78 to the data transfer unit 82 in the same manner as in the related art. A data transmission request signal R output from a data transmission request signal output unit (not shown) is used to input a data set to the transmission register 14 of the asynchronous inter-system data transfer circuit 10 of FIG. At the same time as input ((c) in FIG. 3), the transmission-side input data D is input to the data input of the transmission-side register 14. The transmitting clock C at the time of these inputs
When LKA ((b) in FIG. 3) is input to the clock input of the transmission-side register 14, the transmission-side input data D is set in the transmission-side register 14 in response to the rising edge ((d) in FIG. 3). ). FIG. 3A shows a scale on the time axis of the entire operation timing chart of FIG.

At the same time that the transmission-side input data D is set in the transmission-side register 14, the transmission-side register valid flag circuit 16 is set, and the transmission-side register valid flag is transmitted from its output (FIG. 3 (e)). ). The transmission-side register valid flag is also transmitted as a data transmission inhibition signal I from the asynchronous inter-system data transfer circuit 10 to the data transfer unit 8.
2, a PCI bus interface unit 78,
The data is supplied to a data transmission source (not shown) via the PCI bus 72. By this supply, transmission of the next data from the data transmission source is suppressed until the transmission side register valid flag is reset.

The transmission-side register valid flag is supplied to the set inputs of the flip-flop circuit 18 of the transmission-side circuit portion 12 and the flip-flop circuit 56 of the reception-side circuit portion 52. The transmission-side register valid flag supplied to the set input of the flip-flop circuit 18 is sequentially set in the flip-flop circuits 18 to 24 by the successive rise of the transmission-side clock CLKA ((f) to (f) in FIG. 3).
(I)). Further, the transmission-side register valid flag supplied to the set input of the flip-flop 56 is sequentially set in the flip-flop circuits 56 to 60 by the successive rising of the reception-side clock CLKB ((w) in FIG. 3) (FIG. 3). (N) to (p)). Flip-flop circuit 58
Are sequentially set in the flip-flop circuits 34 to 38 at the successive rise of the transmission side clock ((r) to (t) in FIG. 3).

When each flip-flop circuit is set in this way, first, the transmission register valid flag output from the transmission register valid flag circuit 16 and the output signal of the flip-flop circuit 18 are supplied. The circuit 26 receives the first transmission-side register reset signal 2
7 and supplies this signal to the selector 42. The output signal of the flip-flop circuit 18 and the flip-flop circuit 20
The AND circuit 28 to which the output signal of the flip-flop circuit 20 and the output signal of the flip-flop circuit 22 are supplied, and the AND circuit 28 to which the output signal of The transmission-side register reset signal 31 and the flip-flop circuit 22
And the output signal of the flip-flop circuit 24 are supplied to the AND circuit 32 to sequentially supply the fourth transmission-side register reset signal 33 to the selector 42 ((j) to (m) in FIG. 3).

In the receiving circuit portion 52, the flip-flop circuit 56 is set in response to the rise of the receiving clock immediately after the transmitting register valid flag is output from the transmitting register valid flag circuit 16 ( In FIG. 3 (n), the flip-flop circuits 58 and 60 are set in response to the successive rise of the receiving clock CLKB following this set ((o) in FIG. 3).
(P)).

The set output signal of the flip-flop circuit 58 is a sequential transmission-side clock CL immediately following this set.
Flip-flop circuit 3 in response to rising of KA
4, 36, 38 are set ((r) of FIG. 3)
(T)) The AND circuit 40 to which the output signal of the flip-flop circuit 36 and the output signal of the flip-flop circuit 38 are supplied outputs the fifth register reset signal 41 to the selector 4.
2 ((u) in FIG. 3).

The AND circuit 62 to which the output signal of the flip-flop circuit 58 and the output signal of the flip-flop circuit 60 are supplied supplies the receiving-side register set signal 63 to the set input of the receiving-side register 54 (see FIG. q)),
The receiving register 54 responding to the rise of the receiving clock CLKB supplied after the supply sets the data output from the transmitting register 14 ((v) in FIG. 3) and simultaneously sets the receiving output data valid flag. Circuit 6
4 is set, and the receiving-side output data valid flag circuit 64 outputs the receiving-side output data valid flag. When the data reception processing unit (not shown) in the data transfer unit 82 (FIG. 2) that has received the reception-side output data valid flag completes the reception processing of the reception-side register 54, the data reception completion signal generation circuit , And sends a data reception completion signal to the reception side output data valid flag circuit 64.

During the operation of the transmission side circuit section 12 and the reception side circuit section 52, the bus clock ratio detection circuit 66
Detects the ratio between the frequency of the transmission clock CLKA of the PCI bus 27 and the frequency of the reception clock CLKB of the local bus 74, and supplies the detection signal as a selector signal to the selector 42 of the asynchronous intersystem data transfer circuit 10. . In this embodiment, the selector signal is a signal for selecting any one of the first transmission-side register reset signal 27 to the fifth transmission-side register reset signal 41.

This first transmission side register reset signal 2
The criterion for selecting any one of the seventh to fifth transmission-side register reset signals 41 is based on the transmission-side register 14.
, The transmission-side register 14 keeps holding the data for a time sufficient for data transfer to the reception-side register 54 to be performed normally, and stores the data in the reception-side register 5.
A transmission-side register reset signal that can reset the transmission-side register valid flag circuit 16 at the earliest time within a time allowable range that can be normally set to 4 is selected.

The transmission side register 14 to the reception side register 5
In order to perform a normal data transfer to the transmission-side register 1,
A typical criterion for determining the length of time that the data must be kept as valid data after setting the data in the transmitter 4 is the frequency ratio between the transmitting clock and the receiving clock, the transmitting circuit portion 12 and Receiving side circuit part 5
It depends on the characteristics of the constituent elements of the two circuits.

For example, as shown in FIG. 3, when it is necessary to keep the receiving clock for two or more cycles after setting the data in the transmitting register 14 in accordance with the above-described representative criterion, As a transmission-side register reset signal that can continue to hold the transmission-side register validity flag set in the transmission-side register validity flag circuit 16,
The fourth transmission-side register reset signal that is valid at the earliest time is selected from the first transmission-side register reset signal to the fifth transmission-side register reset signal.

In this embodiment, as described above, the select signal output from the bus clock ratio detection circuit 66 is the select signal for selecting the fourth transmission-side register reset signal 33 output from the AND circuit 32. Therefore, the fourth transmission-side register reset signal 33 is selected by the selector 40 and supplied to the transmission-side register valid flag circuit 16 to reset it ((m) in FIG. 3,
(E)). Due to this reset, the transmission of the data transmission inhibition signal I from the transmission side register valid flag circuit 16 is stopped ((e) in FIG. 3), the data inhibition from the data transmission source is stopped, and the next data transmission is started. You.

The reset of the transmission-side register validity flag circuit 16 is performed during the time required for normal data transfer from the transmission-side register 14 to the reception-side register 54 to hold the data in the transmission-side register 14. Of the data transmission source which has been inhibited at the earliest time and the data transfer of which has been inhibited up to that time may be released from the inhibition and start the data transfer. It is possible to normally transfer data from the transmission side register 14 to the reception side register 54 with the highest transfer efficiency while guaranteeing normal data transfer to the destination register 54.

Next, an example of data transfer from the transmission side register 14 to the reception side register 54 which is different from the above-described data transfer will be described with reference to a timing chart shown in FIG. In the data transfer example, the circuit configuration of the asynchronous intersystem data transfer circuit 10 of this embodiment is the same, and the frequency of the transmission side clock is twice the frequency of the transmission side clock in the example of data transmission shown in FIG. This is an example of the data transfer in the case where.

In the timing chart shown in FIG. 4, since the circuit configuration of the asynchronous intersystem data transfer circuit 10 is the same,
FIGS. 4B to 4M are the same as FIGS. 3B to 3M except that the occurrence times and the durations of the waveforms on the time axis on the timing chart are different. 4 (a), (n) to (q), (v) and (w) of FIG.
(A), (n) to (q), (v) and (w).

In the example of data transfer shown in FIG. 4, similarly to the example of data transfer shown in FIG. 3, the select signal output from clock frequency ratio detection circuit 66 is the fourth signal output from AND circuit 32. Assuming that a select signal for selecting the transmission-side register reset signal 33 is to be output, a transmission-side register reset signal as shown in (m ') of FIG. It is reset ((e) of FIG. 4).

This reset, that is, the release of the suppression of the transmission of the data on the transmission side from the data transmission source, can be immediately read by referring to the scales on the time axis in FIGS. 3 and 4 so that the data transfer shown in FIG. In the example shown in FIG.
(A)) is a time between twelve scales and thirteen scales, and in the example of data transfer shown in FIG. 3, six scales and seven scales on the time axis ((a) in FIG. It is the time between the scale. That is, in the example of the data transfer shown in FIG. 4, the time from the suppression of transmission of data on the transmission side to the data transmission source to the release thereof is longer than that in the example of data transfer shown in FIG. Will drop.

In the data transfer example shown in FIG. 4, the select signal output from the clock frequency ratio detection circuit 66 is the second signal output from the AND circuit 28 as shown in FIG. 5 (k '). 5 is a select signal for selecting the transmission-side register reset signal 29 of FIG.
(K ') is supplied to the selector 42 and the transmission-side register valid flag circuit 16
Is reset (FIG. 5 (e)). Note that (a) to (m), (n) to (q), (v), and (w) in FIG.
(A) to (m), (n) to (q), (v),
Same as (w).

As described above, the frequency of the transmission side clock in the data transfer shown in FIG.
In FIG. 4 showing the data transfer when the data transfer rate is changed to double, that is, 66 MHz, a select for selecting the fourth transmission-side register reset signal 33 output from the AND circuit 32 as a select signal in the data transfer shown in FIG. If the select signal for selecting the second transmission-side register reset signal 29 output from the AND circuit 28 is supplied to the selector 42 instead of the signal, the transmission-side register reset signal 29 The register valid flag circuit 16 is reset ((e) of FIG. 5).

The release of the suppression of the transmission-side data from the data transmission source can be canceled by referring to the scale on the time axis (FIG. 5 (a)) of FIG. The time is between the scale and the scale of nine. That is, FIG.
In the example of the data transfer shown in (1), the time from the suppression of the transmission of data on the transmission side to the data transmission source to the release thereof is
Although the data transfer is shorter than the data transfer shown in FIG. 4 and the data transfer efficiency is inferior to the data transfer as shown in FIG.
Is improved over the data transfer shown in FIG.

As described above, according to this embodiment, even when the frequency of the clock on the transmitting side is changed, the same register reset signal as that before the frequency change is not selected. As a result, the transmission-side register valid flag circuit 16 is reset by the transmission-side register 1
4 during the time required for normal data transfer from the receiving side register 54 to the receiving side register 54.
In the case where the transmission-side register reset signal is performed earlier than the time when the transmission-side data transmission to the data transmission source is suppressed and released, regardless of before and after the frequency change, Is shorter than
In addition, since the data transmission source, which had been inhibited from data transfer at the time of release, can start data transfer, the transmission side register 14 to the reception side register 5
4 can be normally transferred from the transmission side register 14 to the reception side register 54 at the optimum transfer efficiency while guaranteeing normal data transfer to the transmission side register 4.

Second Embodiment FIG. 6 is a block diagram of an asynchronous inter-system data transfer circuit according to a second embodiment of the present invention. The configuration of this embodiment is significantly different from that of the first embodiment in that the select signal is supplied from the PCI bus 72. That is, a known controller (not shown) is connected to the PCI bus 72 (FIG. 2), and the controller 42 transmits a select signal from the controller via the PCI bus 72 to the selector 42A of the asynchronous intersystem data transfer circuit 10A (FIG. 2). (Not shown). The selector 42A is the same as the selector 42 of FIG. 1 except for the points described below.

The controller operates when an operation clock for transferring data from the PCI bus 72 to the local bus 74 (FIG. 2), that is, when the frequency of the transmitting clock is changed, that is, when the standard of the PCI bus 72 is changed. When the old standard is changed to the new standard, for example, when the transmission side clock is changed from 33 MHz to 66 MHz, a standard change signal indicating this is transmitted to the PCI bus 72.
This standard change signal is used as a select signal of the selector 42A of the asynchronous data transfer circuit 10A. Therefore, in this embodiment, the transmission-side register reset signal input to the selector 42A is two. For example, the fourth transmission-side register reset signal 33 in FIG. 3 and the second transmission-side register reset signal 29 in FIG. The other components of this embodiment are the same as those of the first embodiment, so those components are denoted by the same reference numerals as those of the first embodiment, and description thereof will be omitted.

Next, the operation of this embodiment will be described with reference to FIGS. 3, 5 and 6. When the standard of the PCI bus 72 is changed from the old standard shown in the timing chart shown in FIG. 3 to the new standard shown in the timing chart shown in FIG.
Via the selector 4 of the asynchronous intersystem data transfer circuit 10A
The above standard change signal is transferred to 2A. When the asynchronous system data transfer circuit 10A receives this standard change signal, the asynchronous system data transfer circuit 10A
5 operates from the example of the data transfer of the timing chart shown in FIG.

As described above, according to the configuration of this embodiment,
When the standard of the PCI bus 72 is changed, the second transmission-side register reset signal 29 ((k), (k ′) in FIG. 4) after the standard change is selected, and Since the fourth transmission-side register reset signal 33 ((m) in FIG. 5) corresponding to the fourth transmission-side register reset signal 33 ((m) in FIG. 3) is no longer selected,
As described in the first embodiment, the time from the suppression of the transmission of data on the transmission side by the data transmission source to its release is:
After the standard change, the fourth transmission-side register reset signal 33
((M) in FIG. 5) is shorter than when (m) in FIG. 5 is selected. As a result, the asynchronous inter-system data transfer circuit 10A always guarantees normal data transfer from the transmission-side register 14 to the reception-side register 54, and at the same time, increases the data transfer efficiency after changing the operation clock. Data can be transferred with the optimum data transfer efficiency for the changed operation clock, not the data transfer efficiency when the register reset signal 33 is selected.

Third Embodiment FIG. 7 is a block diagram of a data transfer circuit between asynchronous systems according to a third embodiment of the present invention. The configuration of this embodiment is significantly different from that of the first embodiment in that the logic of the circuit constituting the data transfer circuit between asynchronous systems can be set by use of configuration data. (Field programmable gate array; FP
The point is that the configuration is made up of a GA (Field Programmable Gate Array) and a configuration data ROM.

That is, the bus bridge circuit 76B is entirely composed of an FPGA and a configuration data ROM.
In the bus bridge circuit 76B, the PCI bus interface unit 78, the PCI register 80, the local bus interface unit 84, and the local bus register 86 in FIG.
Normally, the operation is performed with the same logic before and after the clock frequency is changed, but the logic configuration may be changed by changing the clock frequency as needed. The same can be said of the data transfer unit 82 in FIG. 2, but the asynchronous intersystem data transfer circuit in the data transfer unit 82 is different from the data transfer shown in FIG. FPGA configured such that a logic circuit therein can be set by configuration data so as to perform the data transfer shown in FIG.
90, configuration data ROMs 92 and 94 for separately registering two configuration data that can set a logic circuit in the FPGA 90 to two setting states, and a selector 4 for selecting one of the configuration data ROMs 92 and 94 by a select signal.
2B.

The configuration data ROM 92 registers configuration data that can set the data transfer logic of the timing chart shown in FIG.
Registers configuration data that can set the logic of data transfer in the timing chart shown in FIG. Then, the clock ratio detection circuit 66B outputs the fourth transmission-side register reset signal 33 in the data transfer of the timing chart shown in FIG. 3 and the second transmission-side register reset signal 29 in the data transfer of the timing chart shown in FIG. And outputs a select signal for selecting one of the two. The asynchronous inter-system data transfer circuit thus configured is referred to by reference numeral 10B in FIG.

In the thus configured asynchronous inter-system data transfer circuit 10 B, the transmission side circuit portion of the logic circuit set in the FPGA 90 by the configuration data read from the configuration data ROM 92 responds to the transmission side clock. That the transmission-side register valid flag is generated, and that the circuit that generates the fourth transmission-side register reset signal 33 in response to the sequential transmission-side clock after the generation of the transmission-side register valid flag operates. 1 is the same as the asynchronous inter-system data transfer circuit 10 of FIG. 1, and the receiving side circuit portion responds to the sequential receiving side clock after the generation of the transmitting side register valid flag in response to the receiving side register set signal 63. Is generated in the same manner as in the asynchronous intersystem data transfer circuit 10 of FIG.

When the configuration data is read from the configuration data ROM 94, when the transmission side circuit portion of the logic circuit set in the FPGA 90 is operated, the sequential transmission side after the generation of the transmission side register valid flag is performed. Instead of generating the fourth transmission-side register reset signal 33 in response to the clock, the second transmission-side register reset signal 29
The configuration data RO
The same operation as when the configuration data is read from M92 is performed. It is known that an asynchronous inter-system data transfer circuit is configured using a PFGA and a configuration data ROM. The other components of this embodiment are the same as those of the first embodiment, so those components are denoted by the same reference numerals as those of the first embodiment, and description thereof will be omitted.

Next, the operation of this embodiment will be described with reference to FIGS. 3, 5, and 7. In the data transfer in which the operation clock (transmission clock CJKA) of the PCI bus 72 is (b) in FIG. 3 and the operation clock (reception clock CLKB) of the local bus 74 is (w) in FIG. When the power is turned on, the configuration data ROM 9
Simultaneously with the reading of 2, the select signal for selecting the configuration data read from the configuration data ROM 92 is output from the clock ratio detection circuit 66B, and the logic of the PFGA 90 is set to the logic capable of performing the data transfer shown in FIG. Therefore, a PCI connection is established from a data source (not shown).
The data transferred via the bus 72 is transferred to the local bus 74 via the PFGA 90 set to the above-described logic.

From this data transfer, the operating clock (transmitting clock CLKA) of the PCI bus 72 is set to (b) in FIG. 5, and the operating clock (receiving clock CLKB) of the local bus 74 is set to (w) in FIG. When the mode is changed to data transfer, the configuration data ROM 94 is read, and at the same time, the clock ratio detection circuit 66B outputs the changed select signal, that is, the select signal for selecting the configuration data read from the configuration data ROM 94. Is output. When this select signal is received by the asynchronous system data transfer circuit 10B, the asynchronous system data transfer circuit 10B
Is switched from the data transfer of the timing chart shown in FIG. 3 to the data transfer of the timing chart shown in FIG.

As described above, according to this embodiment, the PCI
When the operation clock of the bus 72 is changed, the second transmission-side register reset signal 29 ((k), (k ′) in FIG. 5) after the change of the operation clock is selected, and the operation clock is changed. Since the fourth transmission-side register reset signal 33 ((m) in FIG. 5) corresponding to the fourth transmission-side register reset signal 33 ((m) in FIG. 3) before the change is not selected, As described in the first embodiment, the time from the suppression of transmission-side data transmission from the data transmission source to its release is shorter than the case where the fourth transmission-side register reset signal 33 is selected after the operation clock is changed. Be shorter. As a result, the asynchronous system data transfer circuit 10
In B, normal data transfer from the transmission-side register 14 to the reception-side register 54 is always guaranteed, and the data transfer efficiency is such that the fourth transmission-side register reset signal 33 is selected after the operation clock is changed. The data can be transferred with the optimum data transfer efficiency for the changed operation clock instead of the data transfer efficiency in the case.

FIG. 8 is a configuration diagram of a data transfer circuit between asynchronous systems according to a fourth embodiment of the present invention. The configuration of this embodiment is significantly different from that of the first embodiment in that the selection signal is generated manually. That is, prior to transferring the data output from the data transmission source to the local bus 74 from the PCI bus 72, each select signal equivalent to each select signal shown in FIG. Switch 66C is provided. The select signal output from the changeover switch 66C is connected to a selector 42C (not shown) similar to the selector 42 in FIG. 1 in the bus bridge circuit 76C.
To supply.

Therefore, also in this embodiment, the second
As in the embodiment, the transmission-side register reset signal input to the selector 42C is two. For example, the fourth transmission-side register reset signal 33 in FIG. 3 and the second transmission-side register reset signal 29 in FIG. The other components of this embodiment are the same as those of the first embodiment, so those components are denoted by the same reference numerals as those of the first embodiment, and description thereof will be omitted.

Next, the operation of this embodiment will be described with reference to FIGS. 3, 5, and 8. In the example of data transfer in which the operation clock (transmitting clock CLKA) of the PCI bus 72 is (b) in FIG. 3 and the operating clock (receiving clock CLKB) of the local bus 74 is (w) in FIG.
When the operating clock (transmitting clock) of the PCI bus 72 is changed to (b) in FIG. 5 and the operating clock (receiving clock) of the local bus 74 is changed to (w) in FIG. After this change, prior to performing data transfer, the switching circuit 66C switches from the pre-change select signal to the post-change select signal. That is, the switching circuit 66C outputs the fourth transmission-side register reset signal 33 shown in FIG.
The transmission of the select signal for selecting the fourth transmission-side register reset signal 33 shown in FIG. 3 (m) is stopped, and the second transmission-side register reset signal 29 shown in FIG. 5 (k) is selected. Is transmitted.

When this select signal is received by the asynchronous data transfer circuit 10C, the asynchronous data transfer circuit 1
0C operates from the data transfer of the timing chart shown in FIG. 3 to the data transfer of the timing chart shown in FIG. 5 described above.

As described above, according to the structure of this embodiment,
When the operation clock of the PCI bus 72 is changed, the second transmission-side register reset signal 29 ((k), (k ′) in FIG. 5) after the change of the operation clock is selected. Since the fourth transmission-side register reset signal 33 ((m) in FIG. 5) corresponding to the fourth transmission-side register reset signal 33 ((m) in FIG. 3) before the clock change is no longer selected, As described in the first embodiment, the time from the suppression of transmission-side data transmission from the data transmission source to its release is shorter than that when the fourth transmission-side register reset signal 33 is selected after the operation clock is changed. Become shorter. As a result, the asynchronous intersystem data transfer circuit 10 </ b> C
4 is always assured of normal data transfer,
The data transfer efficiency is not the data transfer efficiency when the fourth transmission-side register reset signal 33 is selected after the operation clock is changed, but the data can be transferred with the optimum data transfer efficiency for the changed operation clock. .

Fifth Embodiment FIG. 9 is a block diagram of an asynchronous inter-system data transfer circuit according to a fifth embodiment of the present invention. The configuration of this embodiment is significantly different from that of the first embodiment in that the select signal is generated from the bus operation mode. That is, prior to transferring the data output from the data transmission source from the PCI bus 72 to the local bus 74,
A bus bridge circuit 76D from a controller (not shown) constituting the computer system via the PCI bus 72
Of the two operation modes of the PCI bus 72 is set in the setting register 66D, and a select signal corresponding to the set operation mode is output from the setting register 66D. The signal is supplied to a selector 42D (not shown) corresponding to the selector 42 in FIG. 1 in the asynchronous data transfer circuit 10D.

Therefore, in this embodiment, the second
As in the embodiment, two transmission-side register reset signals are input to the selector 42D. For example, the fourth transmission-side register reset signal 33 in FIG. 3 and the second transmission-side register reset signal 29 in FIG. Other configurations of this embodiment are the same as those of the first embodiment, and therefore, the same reference numerals are used for those components as those of the first embodiment.

Next, the operation of this embodiment will be described with reference to FIGS. 3, 5, and 9. In the example of data transfer in which the operation clock (transmitting clock CLKA) of the PCI bus 72 is (b) in FIG. 3 and the operating clock (receiving clock CLKB) of the local bus 74 is (w) in FIG.
When the operation clock (transmission clock) of the PCI bus 72 is changed to (a) in FIG. 5 and the operation clock (reception clock) of the local bus 74 is changed to the example of data transfer in FIG. Prior to performing data transfer after the change, the controller sets the changed operation mode to the PCI bus 7 instead of the operation mode before the change.
2. The setting is made in the setting register 66D in the data transfer unit 82 via the PCI bus interface unit 78.

With this setting, the setting register 66D stores
The transmission of the select signal for selecting the fourth transmission-side register reset signal 33 shown in (m) of FIG. 3 is stopped, and the second transmission-side register reset signal 29 shown in (k) and (k ′) of FIG. Is sent out. When the asynchronous inter-system data transfer circuit 10D receives this select signal, the asynchronous inter-system data transfer circuit 10D
5 operates from the example of the data transfer of the timing chart shown in FIG.

As described above, according to the configuration of this embodiment,
When the operation clock of the PCI bus 72 is changed, the second transmission-side register reset signal 29 ((k), (k ′) in FIG. 5) after the change of the operation clock is selected. Since the fourth transmission-side register reset signal 33 ((m) in FIG. 5) corresponding to the four transmission-side register reset signals 33 ((m) in FIG. 3) before the clock change is no longer selected, the fourth As described in the first embodiment, the time from the suppression of transmission of data on the transmission side by the data transmission source to the release thereof is changed to the fourth after the operation clock is changed.
Is shorter than when the transmission-side register reset signal 33 is selected. As a result, the data transfer circuit 10D between the asynchronous system
At the same time as normal data transfer is guaranteed, the data transfer efficiency is not the data transfer efficiency when the fourth transmission-side register reset signal 33 is selected after the operation clock is changed, but the changed operation. Data can be transferred at the optimum data transfer efficiency for the clock.

Sixth Embodiment FIG. 10 is a block diagram of an asynchronous inter-system data transfer circuit according to a sixth embodiment of the present invention. The configuration of this embodiment is significantly different from that of the first embodiment in that the generation of the reset signal itself is controlled according to the change of the clock frequency on the transmission side. However, in this embodiment, without changing the clock frequency on the receiving side, the clock frequency on the transmitting side is changed from the first frequency, for example, 66 MHz to the second frequency, which is half the frequency, for example, 33 MHz.
It is assumed that the present embodiment is changed to the embodiment.

That is, the AND circuit 19 is connected between the output of the flip-flop circuit 18 and the non-inverting input of the AND circuit 28 in the first embodiment, and between the output of the flip-flop circuit 22 and the non-inverting input of the AND circuit 32. The AND circuit 23 is connected to the other input terminal, and the other input of the AND circuit 19 is connected to the first output of the clock ratio detection circuit 66E. The other output of the AND circuit 23 is connected to the second output of the clock ratio detection circuit 66E.

The clock ratio detection circuit 66E detects the ratio between the clock frequency on the transmission side and the clock frequency on the reception side, and responds to either the permission signal or the inhibition signal according to the detected ratio. Occurs at the first and second outputs. That is, a permission signal is generated at the second output before the clock frequency is changed, a prohibition signal is generated at the first output, and a permission signal is generated at the first output after the clock frequency is changed, An inhibit signal is generated at the second output.

The output of the AND circuit 28 and the output of the AND circuit 30 are connected to the OR circuit 42E.
The output of the OR circuit 42E is connected to the transmission side register valid flag circuit 16. Other configurations of this embodiment are the same as those of the first embodiment, and therefore, these components include
The description is omitted by using the same reference numerals as those of the components of the first embodiment. Therefore, the asynchronous inter-system data transfer circuit in this embodiment is referred to by reference numeral 10E.

Next, referring to FIG. 3, FIG. 5 and FIG.
The operation of this embodiment will be described. In the data transfer in which the operation clock (transmission clock CLKA) of the PCI bus 72 is (b) in FIG. 3 and the operation clock (reception clock CLKB) of the local bus 74 is (w) in FIG. When the power supply is turned on, the clock ratio detection circuit 66E detects the ratio between the transmission side clock CLKA and the reception side clock CLKB, generates a permission signal at its second output, and outputs a prohibition signal at the first output. appear.

In the state where such a permission signal and a prohibition signal are generated, no signal is output from the AND circuit 19 even if the flip-flop circuit 18 is set. The circuit 23 outputs a signal. Therefore, the second transmission-side register reset signal 29 is not output from the AND circuit 28, but the fourth transmission-side register reset signal 33 is output from the AND circuit 32.

Therefore, the asynchronous data transfer circuit 1
0E operates as in the example of the data transfer in the timing chart shown in FIG. 3 described above.

From the data transfer example of the timing chart shown in FIG. 3, the operating clock (transmitting clock) of the PCI bus 72 is shown in FIG. 5A, and the operating clock (receiving clock) of the local bus 74 is shown in FIG. (W), the clock ratio detection circuit 66E detects the ratio between the transmission clock CLKA and the reception clock CLKB and outputs an enable signal to the first output thereof. And an inhibit signal is generated at the second output.

When the flip-flop circuit 18 is set in a state where such a permission signal and a prohibition signal are generated, a signal is generated from the AND circuit 19, but even if the flip-flop circuit 22 is set, No signal is generated from the AND circuit 23. Therefore, the transmission-side register reset signal 29 is output from the AND circuit 28, but the transmission-side register reset signal 33 is not output from the AND circuit 32.

Therefore, the asynchronous data transfer circuit 1
0E operates as in the example of the data transfer in the timing chart shown in FIG. 5 described above.

Thus, according to the structure of this embodiment,
When the operation clock of the PCI bus 72 is changed, the second transmission-side register reset signal 29 ((k), (k ′) in FIG. 5) after the change of the operation clock is transmitted to the transmission-side register valid flag circuit. The fourth transmission-side register reset signal 33 ((m) in FIG. 5) corresponding to the fourth transmission-side register reset signal 33 ((m) in FIG. 3) before the change of the operation clock. ) Is no longer supplied to the transmission-side register valid flag circuit 16, and as described in the first embodiment, the time from the suppression of transmission-side data transmission from the data transmission source to its release is determined by the operation clock. After the change, the fourth transmission-side register reset signal 33 is shorter than when supplied to the transmission-side register valid flag circuit 16. As a result, the asynchronous inter-system data transfer circuit 10E always guarantees normal data transfer from the transmission-side register 14 to the reception-side register 54, and at the same time, the data transfer efficiency increases after the change of the operation clock. The data can be transferred with the optimum data transfer efficiency for the changed operation clock instead of the data transfer efficiency when the side register reset signal 33 is supplied to the transmission side register valid flag circuit 16.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific structure of the present invention is not limited to these embodiments, and does not depart from the gist of the present invention. Even if there is a change in the design, etc., they are included in the present invention. For example, the invention disclosed in any of the embodiments may be configured to be used for data transfer from the local bus 74 to the PCI bus 72. In addition, the bus may be in any of the above-mentioned forms, and may be in the form of another bus.

In each of these embodiments, the clock is a signal corresponding to another type of clock supplied via the bus, or an equivalent signal provided in a bus bridge circuit or an asynchronous data transfer circuit. It may be replaced. In addition, the transmission side input data is expressed as a transfer unit as follows:
Bit parallel or bit serial may be used. Further, in the data transfer between asynchronous systems without using a bus, the inventive idea of the present application can be implemented. In any of the above-described embodiments, data transmission and reception may be performed in a wireless format.

[0102]

As described above, according to the present invention,
When the operating clock on the transmitting side is changed, instead of selecting the reset signal before the change, the reset signal corresponding to the operating clock after the change is selected. The time from the suppression to the release thereof is shorter than when a reset signal corresponding to the reset signal before the change of the operation clock is selected.
Therefore, the asynchronous inter-system data transfer circuit always guarantees normal data transfer from the transmission side to the reception side, and at the same time, selects a reset signal corresponding to the reset signal before the change of the operation clock in data transfer efficiency. It is possible to transfer data with the optimum data transfer efficiency for the changed operation clock instead of the data transfer efficiency in the case where the data transfer is performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transfer circuit between asynchronous systems according to a first embodiment of the present invention;

FIG. 2 is a schematic configuration diagram of a bus bridge circuit of a computer system including the asynchronous inter-system data transfer circuit.

FIG. 3 is an operation timing chart of the asynchronous inter-system data transfer circuit when a transmission / reception clock frequency ratio is a predetermined value.

FIG. 4 is an operation timing chart of the asynchronous inter-system data transfer circuit when the frequency of the transmission-side clock in the operation timing chart shown in FIG. 3 is reduced to half;

5 is an operation timing chart showing selection of a transmission-side register reset signal different from that of FIG. 4 at the operation timing of FIG. 4;

FIG. 6 is a configuration diagram of a data transfer circuit between asynchronous systems according to a second embodiment of the present invention;

FIG. 7 is a configuration diagram of a data transfer circuit between asynchronous systems according to a third embodiment of the present invention;

FIG. 8 is a configuration diagram of an asynchronous inter-system data transfer circuit according to a fourth embodiment of the present invention.

FIG. 9 is a configuration diagram of a data transfer circuit between asynchronous systems according to a fifth embodiment of the present invention.

FIG. 10 is a configuration diagram of a data transfer circuit between asynchronous systems according to a fifth embodiment of the present invention.

FIG. 11 is a configuration diagram of a conventional one-type asynchronous inter-system data transfer circuit.

FIG. 12 is a configuration diagram of another conventional asynchronous inter-system data transfer circuit.

[Explanation of symbols]

10, 10A, 10B, 10C, 10D Data transfer circuit between asynchronous systems 14 Transmitter register (data holding circuit) 16 Transmitter register valid flag circuit (first circuit) 18-22, 34-38, 56, 58 Flip-flop Circuits (part of reset signal generation circuit) 19, 23, 26 to 32, 40, 42A AND circuit (remaining reset signal generation circuit) 42, 42B Selector (selection circuit) 66, 66B Clock ratio detection circuit (selection signal output) Circuit) 66C changeover switch (selection signal output circuit) 66D setting register (selection signal output circuit) 72 PCI bus etc. (data transmission device) 74 Local bus etc. (data reception device)

Claims (18)

[Claims] 1. A data transmission device, which performs transmission at a first timing, and a data reception device, which performs reception at a second timing different from the first timing, is inserted between the data transmission device and the data transmission device. An asynchronous inter-system data transfer circuit that transfers data to a receiving device for each transfer unit, a data holding circuit that temporarily holds data input from the data transmitting device in a transfer unit, and wherein the data is stored in the data holding circuit. Outputting a data holding valid signal at a timing having a predetermined relationship with the first timing when the data is held, and supplying the data holding valid signal to the data transmitting device to suppress transfer of the next data; A first circuit for stopping the output of the data holding valid signal when a reset signal is supplied, and a first circuit connected to an output of the first circuit, A predetermined time elapses from the output time of the data holding valid signal in response to the signal until the data is normally transferred from the data holding circuit to the data receiving device in a transfer unit when the timing is changed. And a reset signal generating circuit for generating a reset signal corresponding to the changed timing and supplying the reset signal to the first circuit at a time when the reset signal is supplied. An asynchronous inter-system data transfer circuit, wherein when the output of the data holding valid signal is stopped, the inhibition is released and the next data is transferred from the data transmitting device to the data holding circuit. 2. The reset signal generation circuit, wherein the reset signal generation circuit generates reset signal candidates corresponding to each of the pair of the first timing and the second timing which can be changed; A selection signal output circuit that outputs a selection signal corresponding to each pair of timing and the second timing; and an output from the selection signal output circuit from among the reset signal candidates output from the reset signal candidate generation circuit. 2. The asynchronous inter-system data transfer circuit according to claim 1, further comprising a selection circuit for selecting a reset signal candidate corresponding to the selected selection signal and outputting the selected reset signal as a reset signal. 3. The asynchronous inter-system data transfer circuit according to claim 2, wherein said reset signal candidate generation circuit and said selection circuit are constituted by fixed logic circuits. 4. The reset signal candidate generation circuit and the selection circuit include configuration data storage means for storing configuration data, and a circuit capable of setting logic corresponding to configuration data read from the configuration data storage means. 3. The asynchronous inter-system data transfer circuit according to claim 2, wherein the circuit is configured. 5. The selection signal output circuit detects a ratio between a clock frequency of a data transmission device and a clock frequency of a data reception device, and supplies a selection signal corresponding to the detected ratio to the selection circuit. 5. The asynchronous inter-system data transfer circuit according to claim 2, wherein the circuit is a circuit. 6. The controller according to claim 1, wherein the selection signal output circuit is connected to a transmission-side bus and outputs a standard change signal, and the controller selects the selection signal corresponding to the standard change signal supplied from the controller via the transmission-side bus. 5. A circuit for supplying a signal to a circuit.
2. The asynchronous inter-system data transfer circuit according to 1. 7. The selection signal output circuit is connected to a transmission-side bus and outputs an operation mode signal. The selection signal output circuit selects the selection signal corresponding to the operation mode signal supplied from the controller via the transmission-side bus. 5. The asynchronous data transfer circuit according to claim 2, further comprising a circuit for supplying the data to the circuit. 8. The selection signal output circuit is a changeover switch that outputs a reset signal output by switching, and a switching signal output by switching the changeover switch is supplied to the selection circuit as a selection signal. 5. The asynchronous data transfer circuit according to claim 2, 3 or 4. 9. The data setting in the first circuit is performed based on a clock of the data transmission device, and the generation of the reset signal in the reset signal generation circuit is performed in synchronization with a clock of the data transmission device. 9. The asynchronous inter-system data transfer circuit according to claim 1, wherein the transfer is performed based on one of a clock of the data transmission device and a clock of the data reception device. 10. The reset signal generation circuit outputs a permission signal to a change target pair among the changeable first timing and the second timing pair, and to a non-change target pair. A first signal generation circuit for generating an inhibit signal at a corresponding output, and an input corresponding to each output of the first signal generation circuit, and a reset signal output corresponding to the input. The reset signal output corresponding to the inhibit signal supplied from the first signal generation circuit does not generate a reset signal,
A second signal generation circuit for generating a reset signal at a reset signal output corresponding to a permission signal supplied from the signal generation circuit, and a reset signal generated by being connected to each other output of the second signal generation circuit 2. The asynchronous inter-system data transfer circuit according to claim 1, further comprising an output circuit for outputting only the data. 11. The first signal generation circuit detects a ratio between a clock frequency of a data transmission device and a clock frequency of a data reception device, and when the detected ratio is a change target, the first signal generation circuit determines the change target. 2. The apparatus according to claim 1, wherein a permission signal is generated at a corresponding output, and a prohibition signal is generated at an output corresponding to the non-change target when the detected ratio is non-change target.
0. The asynchronous inter-system data transfer circuit according to 0. 12. The first signal generation circuit includes a controller connected to a transmission bus and outputting a standard change signal, and a signal conversion circuit connected to the transmission bus.
When the standard change signal output from the controller is a change target, the signal conversion circuit outputs a permission signal to an output corresponding to the change target, and when the standard change signal is non-change target, the signal conversion circuit changes the enable signal. 11. The asynchronous intersystem data transfer circuit according to claim 10, wherein a prohibition signal is output to an output corresponding to an asymmetric object. 13. The first signal generation circuit includes a controller connected to a transmission-side bus and outputting an operation mode signal, and a signal conversion circuit connected to the transmission-side bus, and a standard output from the controller. When the change signal is a change target, the signal conversion circuit outputs a permission signal to an output corresponding to the change target, and when the standard change signal is not a change target, the signal conversion circuit outputs a prohibition signal to an output corresponding to the non-change target. 11. The asynchronous inter-system data transfer circuit according to claim 10, wherein 14. The first signal generation circuit is a changeover switch that outputs a reset signal that is output by switching, and an enable signal is output to an output corresponding to a change target of the changeover switch. The asynchronous inter-system data transfer circuit according to claim 10, wherein a prohibition signal is output to an output corresponding to a non-change target. 15. The data transfer circuit according to claim 10, wherein the second signal generation circuit and the output circuit are configured by fixed logic circuits. 16. A configuration data storage unit configured to store configuration data, wherein the second signal generation circuit and the output circuit store configuration data.
15. The asynchronous inter-system data transfer circuit according to claim 10, comprising a circuit capable of setting a logic corresponding to the configuration data read from said configuration data storage means. 17. The data setting in the first circuit is performed based on a clock of the data transmission device,
The generation of the reset signal in the reset signal generation circuit is performed based on one of a clock of the data transmission device, a clock of the data transmission device, and a clock of the data reception device. 1,
17. The asynchronous inter-system data transfer circuit according to any one of 10 to 16. 18. A data transmission apparatus that performs transmission operation at a predetermined first timing from a second data transmission device different from the first timing.
When data is to be transferred to the data receiving device operating at the timing of the transfer in units of transfer, the data to be transferred is transferred from the data transmitting unit of the data transmitting device to the data holding unit of the data transmitting device in units of transfer. When the data is held, during a predetermined time until the data is normally transferred from the data holding unit to the data receiving device in a transfer unit, the next data from the data sending unit to the data holding unit is transferred from the data sending unit to the data holding unit. Inhibiting the transfer, releasing the inhibition when the required time elapses, and releasing the inhibition when the inhibition is released, causing the data sending unit to hold the next data from the data sending unit to the data holding unit, and In the asynchronous inter-system data transfer method for initiating data transfer, the method further comprises: The data is transmitted from the data transmitting device to the data transmitting device, and the data is transmitted from the data transmitting device to the data retaining device. A data transfer method between asynchronous systems, wherein data is transferred to a receiving device in a transfer unit.