JP2001306161A - Fet switching circuit - Google Patents
Fet switching circuitInfo
- Publication number
- JP2001306161A JP2001306161A JP2000126481A JP2000126481A JP2001306161A JP 2001306161 A JP2001306161 A JP 2001306161A JP 2000126481 A JP2000126481 A JP 2000126481A JP 2000126481 A JP2000126481 A JP 2000126481A JP 2001306161 A JP2001306161 A JP 2001306161A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- terminal
- circuit
- power supply
- shunt regulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Voltage And Current In General (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、短絡遮断機能付き
直流電源装置からの出力電圧をオン／オフさせるＦＥＴ
スイッチ回路に関するものであり、負荷側が短絡した場
合、上記直流電源装置の短絡機能が動作するまでに、Ｆ
ＥＴに瞬時ピーク電流が流れて、破損に到らないよう、
ＦＥＴの特性を利用し、ゲート電圧を制御することで最
大ドレイン電流を抑える保護回路を実現しようとするも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FET for turning on / off an output voltage from a DC power supply having a short-circuit cutoff function.
This is related to a switch circuit, and when a short circuit occurs on the load side, F is required until the short circuit function of the DC power supply device operates.
To prevent instantaneous peak current from flowing through the ET and damage it,
An object of the present invention is to realize a protection circuit that suppresses the maximum drain current by controlling the gate voltage by utilizing the characteristics of the FET.
【０００２】[0002]
【従来の技術】図２は、従来使用されている出力電圧オ
ン／オフ用ＦＥＴスイッチ回路であり、出力を短絡させ
ると、直流電源装置の短絡機能が動作する前に、ＦＥＴ
のドレイン電流を制御できないため、過大なドレイン電
流が流れ、ＦＥＴが破損していた。そこで、図３の回路
のように、図４のＦＥＴの出力特性を利用してゲート・
ソース間に定電圧ダイオードを接続すれば、瞬時ピーク
電流を抑えることが可能になるが、ツェナー電圧のばら
つきによってドレイン電流がばらついてしまい、精度の
高い電流抑制ができず、容量の大きなＦＥＴが必要にな
り、コスト高になるという問題があった。2. Description of the Related Art FIG. 2 shows a conventional FET switch circuit for turning on / off an output voltage. When an output is short-circuited, an FET is turned off before a short-circuit function of a DC power supply device operates.
Since the drain current cannot be controlled, an excessive drain current flows and the FET is damaged. Therefore, as shown in the circuit of FIG.
If a constant voltage diode is connected between the sources, it is possible to suppress the instantaneous peak current.However, the drain current varies due to the variation of the Zener voltage, so it is not possible to suppress the current with high accuracy, and an FET with a large capacity is required. And there is a problem that the cost increases.
【０００３】[0003]
【発明が解決しようとする課題】このように、ＦＥＴの
ゲート・ソース間に接続した定電圧ダイオードのツェナ
ー電圧のばらつきによってゲート電圧およびドレイン電
流がばらつき、精度の高い電流抑制ができず、ＦＥＴの
大容量品（大型品）が必要になり、コスト高となるとい
う問題があったため、容量の大きなＦＥＴを用いること
なく、電流制御ができる保護回路が要求されていた。As described above, the gate voltage and the drain current fluctuate due to the fluctuation of the zener voltage of the constant voltage diode connected between the gate and the source of the FET. There is a problem that a large-capacity product (large-sized product) is required and the cost is increased. Therefore, a protection circuit capable of controlling current without using a large-capacity FET has been required.
【０００４】[0004]
【課題を解決するための手段】本発明は、上記の課題を
解決したもので、図４に示す、ゲート電圧によって、最
大ドレイン電流を抑えることが可能なＦＥＴ特性を利用
し、ＦＥＴのゲート・ソース間にシャントレギュレータ
ＩＣと分圧抵抗を接続し、精度の高いドレイン電流の抑
制を行い、ＦＥＴの破損を防止するとともに、小容量
（小型）のＦＥＴを使用できるようにしてコストを低減
しようとするものである。すなわち、短絡遮断機能付き
直流電源装置からの出力電圧をオン／オフさせるＦＥＴ
スイッチ回路において、ＦＥＴ Ｑ１のソース端子を上
記直流電源装置の正極に、またドレイン端子を負荷回路
の正極側に接続し、さらにゲート端子を抵抗Ｒ３および
スイッチＳ１を介して上記直流電源装置の負極・負荷回
路の負極に接続し、ソース端子にシャントレギュレータ
ＩＣ ＩＣ１のカソード端子、ゲート端子にシャントレ
ギュレータＩＣ ＩＣ１のアノード端子を接続し、ＦＥ
Ｔ Ｑ１のゲート電圧を分圧する第１の抵抗Ｒ１および
第２の抵抗Ｒ２にシャントレギュレータＩＣ ＩＣ１の
リファレンス端子を接続してなる保護回路を設けたこと
を特徴とするＦＥＴスイッチ回路。SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and utilizes the FET characteristics shown in FIG. 4 which can suppress the maximum drain current by the gate voltage. By connecting a shunt regulator IC and voltage-dividing resistor between the sources to control the drain current with high accuracy, prevent damage to the FET, and reduce the cost by using a small-capacity (small) FET. Is what you do. That is, an FET for turning on / off an output voltage from a DC power supply device having a short-circuit breaking function
In the switch circuit, the source terminal of the FET Q1 is connected to the positive terminal of the DC power supply, the drain terminal is connected to the positive terminal of the load circuit, and the gate terminal is connected to the negative terminal of the DC power supply via a resistor R3 and a switch S1. FE is connected to the negative terminal of the load circuit, the source terminal is connected to the cathode terminal of the shunt regulator IC IC1, the gate terminal is connected to the anode terminal of the shunt regulator IC IC1,
An FET switch circuit comprising a protection circuit formed by connecting a reference terminal of a shunt regulator IC IC1 to a first resistor R1 and a second resistor R2 for dividing a gate voltage of TQ1.
【０００５】[0005]
【発明の実施の形態】図１のように、ＦＥＴ Ｑ１のソ
ース端子を短絡遮断機能付き直流電源装置の正極に接続
し、ドレイン端子を負荷回路の正極側に接続し、ゲート
端子を抵抗Ｒ３およびスイッチＳ１を介して上記直流電
源装置の負極−負荷回路の負極に接続し、ソース端子に
シャントレギュレータＩＣ ＩＣ１のカソード端子、ゲ
ート端子にシャントレギュレータＩＣ ＩＣ１のアノー
ド端子を接続し、ＦＥＴ Ｑ１のゲート電圧を分圧する
第１の抵抗Ｒ１および第２の抵抗Ｒ２にシャントレギュ
レータＩＣ ＩＣ１のリファレンス端子を接続する。負
荷側が短絡された時、直流電源装置の短絡機能が動作す
るまでの間に、ＦＥＴ Ｑ１のゲート電圧を第１の抵抗
Ｒ１および第２の抵抗Ｒ２で分圧して、シャントレギュ
レータＩＣ ＩＣ１のリファレンス端子に入力し、該シ
ャントレギュレータＩＣ ＩＣ１により、１％以下の精
度でゲート電圧を制御する。分圧抵抗により、０．５％
以下の精度でゲート電圧が安定化され、ＦＥＴ Ｑ１に
流れる瞬時ピーク電流（最大ドレイン電流）が抑えら
れ、ＦＥＴの安全動作領域を維持して破損に到らないよ
う、ＦＥＴ Ｑ１の最大ドレイン電流を抑えることがで
きる。DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a source terminal of an FET Q1 is connected to a positive terminal of a DC power supply having a short-circuit cutoff function, a drain terminal is connected to a positive terminal of a load circuit, and a gate terminal is connected to a resistor R3 and a resistor R3. The negative terminal of the DC power supply device is connected to the negative terminal of the load circuit via the switch S1, the cathode terminal of the shunt regulator IC IC1 is connected to the source terminal, the anode terminal of the shunt regulator IC IC1 is connected to the gate terminal, and the gate voltage of the FET Q1 is connected. The reference terminal of the shunt regulator IC IC1 is connected to the first resistor R1 and the second resistor R2 for dividing the voltage. When the load side is short-circuited, the gate voltage of the FET Q1 is divided by the first resistor R1 and the second resistor R2 until the short-circuit function of the DC power supply operates, and the reference terminal of the shunt regulator IC IC1 is divided. , And the shunt regulator IC controls the gate voltage with an accuracy of 1% or less. 0.5% due to voltage divider resistance
The gate voltage is stabilized with the following accuracy, the instantaneous peak current (maximum drain current) flowing through the FET Q1 is suppressed, and the maximum drain current of the FET Q1 is reduced to maintain the safe operation area of the FET and prevent damage. Can be suppressed.
【０００６】[0006]
【実施例】図１は本発明の実施例による保護回路図であ
り、図２は保護回路を使用しない従来例による回路図、
図３は図２のゲート・ソース間に定電圧ダイオードを接
続した従来例による保護回路図である。図１、３の保護
回路を用い、負荷短絡時のＦＥＴ Ｑ１のゲート電圧Ｖ
ＧＳおよびドレイン電流ＩＤを測定し比較した。併せ
て、図２の従来例による回路を使用した時の状態も確認
した。その結果を表１に示す。1 is a protection circuit diagram according to an embodiment of the present invention, FIG. 2 is a circuit diagram according to a conventional example using no protection circuit,
FIG. 3 is a protection circuit diagram of a conventional example in which a constant voltage diode is connected between the gate and the source of FIG. Using the protection circuit of FIGS. 1 and 3, the gate voltage V of the FET Q1 when the load is short-circuited
GS and drain current ID were measured and compared. At the same time, the state when the circuit according to the conventional example of FIG. 2 was used was also confirmed. Table 1 shows the results.
【０００７】[0007]
【表１】 表１において明らかなように、ＦＥＴ Ｑ１のゲート電
圧ＶＧＳおよびドレイン電流ＩＤのバラつきは、定電圧
ダイオードＤ１を接続した図３ではある程度抑えられる
が、なおバラつき大であり、ＩＤも大きいのに対し、図
３の回路の定電圧ダイオードＤ１をシャントレギュレー
タＩＣ ＩＣ１に置き替え、ＦＥＴ Ｑ１のゲート電圧
を第１の抵抗Ｒ１および第２の抵抗で分圧して、上記シ
ャントレギュレータＩＣ ＩＣ１のリファランス端子に
入力する、本発明の実施例では、ゲート電圧ＶＧＳも安
定し、ドレイン電流ＩＤが小さくなり、バラつきも抑え
られていることが分かる。[Table 1] As is apparent from Table 1, the variation in the gate voltage V GS and the drain current ID of the FET Q1 can be suppressed to some extent in FIG. 3 in which the constant voltage diode D1 is connected, but the variation is still large and the ID is large. In contrast, the constant voltage diode D1 in the circuit of FIG. 3 is replaced with a shunt regulator IC IC1, and the gate voltage of the FET Q1 is divided by the first resistor R1 and the second resistor, and the reference terminal of the shunt regulator IC IC1 is divided. In the embodiment of the present invention, the gate voltage V GS is also stable, the drain current ID is small, and the variation is suppressed.
【０００８】[0008]
【発明の効果】上記したとおり、本発明による保護回路
は、ＦＥＴのゲート電圧を第１の抵抗と第２の抵抗で分
圧して、シャントレギュレータＩＣのリファレンス端子
に入力し、該シャントレギュレータＩＣによりゲート電
圧を制御し、分圧抵抗によりゲート電圧を安定化するこ
とで最大ドレイン電流を抑えることができるので、負荷
側を短絡した場合、直流電源装置の短絡機能が動作する
までの間に、ＦＥＴが破損することがなくなり、また、
ＦＥＴの小容量品が使用可能となり、ＦＥＴの小型化、
低コスト化を図ることができる。As described above, in the protection circuit according to the present invention, the gate voltage of the FET is divided by the first resistor and the second resistor and input to the reference terminal of the shunt regulator IC. Since the maximum drain current can be suppressed by controlling the gate voltage and stabilizing the gate voltage with a voltage dividing resistor, if the load side is short-circuited, the FET must be connected before the short-circuit function of the DC power supply operates. Will not be damaged,
FET small-capacity products can be used, miniaturizing FETs,
Cost reduction can be achieved.
【図１】本発明の実施例による保護回路図である。FIG. 1 is a protection circuit diagram according to an embodiment of the present invention.
【図２】従来例による保護回路図である。FIG. 2 is a protection circuit diagram according to a conventional example.
【図３】図２のゲート・ソース間に定電圧ダイオードを
接続した従来例による保護回路図である。3 is a protection circuit diagram according to a conventional example in which a constant voltage diode is connected between the gate and the source in FIG.
【図４】本発明に使用するＦＥＴの出力静特性図であ
る。FIG. 4 is an output static characteristic diagram of an FET used in the present invention.
Ｑ１ ＦＥＴ Ｄ１ 定電圧ダイオード ＩＣ１ シャントレギュレータＩＣ Ｒ１ 第１の抵抗 Ｒ２ 第２の抵抗 Ｒ３ 抵抗 Ｓ１ スイッチ Q1 FET D1 Constant voltage diode IC1 Shunt regulator IC R1 First resistor R2 Second resistor R3 Resistor S1 Switch
Claims (1)
力電圧をオン／オフさせるＦＥＴスイッチ回路におい
て、 ＦＥＴのソース端子を上記直流電源装置の正極に、また
ドレイン端子を負荷回路の正極側に接続し、さらにゲー
ト端子を抵抗およびスイッチを介して上記直流電源装置
の負極・負荷回路の負極に接続し、ソース端子にシャン
トレギュレータＩＣのカソード端子、ゲート端子にシャ
ントレギュレータＩＣのアノード端子を接続し、ＦＥＴ
のゲート電圧を分圧する第１および第２の抵抗にシャン
トレギュレータＩＣのリファレンス端子を接続してなる
保護回路を設けたことを特徴とするＦＥＴスイッチ回
路。1. An FET switch circuit for turning on / off an output voltage from a DC power supply having a short-circuit breaking function, wherein a source terminal of the FET is connected to a positive electrode of the DC power supply, and a drain terminal is connected to a positive electrode of a load circuit. Further, the gate terminal is connected to the negative electrode of the DC power supply device and the negative electrode of the load circuit via a resistor and a switch, the cathode terminal of the shunt regulator IC is connected to the source terminal, and the anode terminal of the shunt regulator IC is connected to the gate terminal. FET
An FET switch circuit comprising: a protection circuit formed by connecting a reference terminal of a shunt regulator IC to first and second resistors for dividing a gate voltage of the FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000126481A JP2001306161A (en) | 2000-04-26 | 2000-04-26 | Fet switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000126481A JP2001306161A (en) | 2000-04-26 | 2000-04-26 | Fet switching circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001306161A true JP2001306161A (en) | 2001-11-02 |
Family
ID=18636258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000126481A Pending JP2001306161A (en) | 2000-04-26 | 2000-04-26 | Fet switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001306161A (en) |
-
2000
- 2000-04-26 JP JP2000126481A patent/JP2001306161A/en active Pending
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