JP2005045957A - Rush current prevention circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a rush current prevention circuit that can reduce a rush current with a simple constitution. <P>SOLUTION: The rush current prevention circuit comprises: a load 3 connected to a DC power supply 1 and an input capacitor 4 connected to the load 3 in parallel therewith; a field effect transistor 5 that restrains the rush current to the input capacitor 4; a time constant circuit that comprises bias resistors 7, 8 for generating gate voltages of the field-effect transistor 5, and a capacitor 6; and a capacitor 9 that is connected in parallel between a drain and a gate of the field effect transistor 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an inrush current suppressing circuit that suppresses an inrush current generated when a circuit having a large capacity input capacitor is connected to a power source.

  In a conventional electric / electronic circuit, a relatively large-capacity input capacitor is connected to the power supply input portion of the circuit in order to stabilize the operation of the circuit and to suppress the influence of the circuit operation on the outside. For this reason, the inrush current that flows at the moment when the power supply is connected becomes very large due to the large amount of charging current that flows to the input capacitor. In order to suppress such a large inrush current, an inrush current prevention circuit is provided in the power supply circuit as necessary (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 9-37456 (FIG. 2)

  The conventional inrush current prevention circuit as described above has the following problems. In general, the on-resistance of a field effect transistor decreases rapidly as the gate-source voltage increases, and slowly decreases as it approaches 0Ω. In a steady state of the circuit, a region where the on-resistance is lowered is used in order to reduce loss due to the field effect transistor. On the other hand, in a transient state in which the inrush current is suppressed, a region where an appropriate resistance value is obtained for limiting the current is used. However, in the region where the appropriate resistance value is obtained, the on-resistance changes suddenly due to a slight change in the gate-source voltage. Therefore, if the inrush current is controlled only by the time constant circuit as described above, the resistance The inrush current varies greatly due to variations in the capacitance of the capacitor and the characteristics of the field effect transistor. When it is necessary to keep the inrush current low and constant, it is difficult to realize with a conventional inrush current prevention circuit.

  If the gate-source voltage does not rise to a certain extent, the on-resistance is not reduced and no current flows. Therefore, it takes time until the current flows after the circuit is closed. If a large time constant is taken in order to keep the inrush current low, more time is required and the rise of the entire circuit is delayed.

  Furthermore, depending on the type of load such as a DC / DC converter, the load operation may be started when a certain voltage is input to the load before the input capacitor is fully charged. At this time, unless sufficient current can be supplied for the load to operate, the voltage of the input capacitor drops and the operation of the load cannot be maintained.

  Therefore, in addition to a simple time constant circuit, there is a method to detect the current with a shunt resistor and apply a negative feedback so that the inrush current does not exceed a certain level. The circuit used has a large number of parts, and a significant increase in cost is inevitable.

  The present invention has been made to solve the above-described problems, and provides an inrush current prevention circuit capable of suppressing an inrush current with a simple configuration.

  In addition, the time from when the power is turned on until the current flows out is accelerated, and the rise time of the entire circuit is accelerated.

  Further, when the load starts to operate while the inrush current is suppressed, the current is quickly supplied to the load circuit, and the influence on the load by the inrush current preventing circuit is reduced.

  An inrush current prevention circuit according to the present invention includes a load connected to a DC power source, an input capacitor connected in parallel with the load, a field effect transistor for limiting an inrush current to the input capacitor, and the field effect transistor A time constant circuit having a bias resistor and a first capacitor for generating a gate voltage, and a second capacitor connected in parallel between the drain and gate of the field effect transistor are provided.

  A resistor is connected in series with the second capacitor.

According to the present invention, with a simple configuration, negative feedback is applied to the charging current to the input capacitor, and the charging current can be kept constant.
In addition, a voltage is generated in the capacitor between the gate and the source immediately after the power is turned on, so that the on-resistance of the field effect transistor can be quickly reduced and an inrush current can be passed quickly.
Since this negative feedback is applied to the charging current to the input capacitor, no current other than the charging current will be negatively fed. Even if the load starts to operate while the inrush current is suppressed, the current is supplied to the load. Can be performed promptly.

Embodiment 1 FIG.
An inrush current preventing circuit according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a configuration of an inrush current preventing circuit according to a first embodiment of the present invention, and FIG. 2 is a graph showing a relationship between a gate-source voltage and a drain-source on-resistance of a MOS field effect transistor. FIG. 3 is a graph showing changes in the voltage between the gate and source of the MOS field effect transistor, and FIG. 4 is a graph showing changes in the input current supplied from the DC power supply.
In FIG. 1, 1 is a DC power source, 2 is a switch, 3 is a load, and 4 is an input capacitor. 101 is an inrush current prevention circuit unit, 5 is a MOS field effect transistor (hereinafter referred to as FET as appropriate), 6 and 9 are capacitors, 7 and 8 are resistors, and the voltage change between the drain and source of the FET 5 is constant. The gate voltage of the FET 5 is adjusted so that
In this embodiment, the DC power source 1 is 24 V, the input capacitor 4 is 47 μF, the FET 5 is 2SK1590 (manufactured by NEC Electronics), the capacitor 6 is 0.22 μF, the resistor 7 is 390 kΩ, the resistor 8 is 820 kΩ, the capacitor 9 is 0.022 μF.

  Immediately after the switch is closed from the state where the voltage of each capacitor 4, 6 and 9 is 0V, each capacitor 4, 6 and 9 is connected in series. Voltage is generated. Further, since the capacity of the input capacitor 4 is larger than that of the capacitors 6 and 9, almost no voltage is generated in the input capacitor 4, and most of the voltage is generated in the capacitors 6 and 9. In this embodiment, about 2.2 V is generated in the capacitor 6 and about 21.8 V is generated in the capacitor 9. Since the voltage of the capacitor 6 at this time becomes the gate-source voltage of the FET 5, the on-resistance of the FET 5 decreases according to the voltage, and the charging current to the input capacitor 4 flows quickly. In this embodiment, the charging current flows about 45 mA. In order to make this current an expected inrush current, the gate-source voltage of the FET 5, that is, the voltage of the capacitor 6 is determined according to the characteristics of FIG. 2, and the capacitance of each capacitor is set so as to be this voltage.

  Immediately after the switch 2 is closed, the current flowing through the resistor 8 charges the capacitor 6 to increase the voltage of the capacitor 6, that is, the voltage between the gate and source of the FET 5, and decrease the on-resistance of the FET 5, thereby reducing the input capacitor. 4 to increase the charging current to 4. At the same time, charging of the input capacitor 4 increases the voltage of the input capacitor 4 and decreases the drain-source voltage of the FET 5 by the same amount. As the drain-source voltage of the FET 5 decreases, the voltage of the capacitor 9 also decreases. For this reason, a current flows through the capacitor 9, and this current acts in a direction to suppress the voltage increase of the capacitor 6.

  When the voltage of the capacitor 6 is substantially constant, the voltage change between the drain and source of the FET 5 is equal to the voltage change of the capacitor 9. For this reason, the current flowing through the capacitor 9 is proportional to the differentiation of the drain-source voltage of the FET 5. Further, the voltage of the input capacitor 4 is proportional to the integral of the charging current to the input capacitor 4, but when differentiated, it can be said that the differentiation of the voltage of the input capacitor 4 is proportional to the charging current to the input capacitor 4. Further, when the voltage of the input capacitor 4 increases, the drain-source voltage of the FET 5 decreases by the same amount. Therefore, it can be said that the differentiation of the drain-source voltage of the FET 5 is proportional to the charging current to the input capacitor 4. From the above, it can be said that the current flowing through the capacitor 9 is proportional to the charging current of the input capacitor 4.

  Since the current flowing through the capacitor 9 is proportional to the charging current to the input capacitor 4, the current flowing through the capacitor 9 is small when the charging current to the input capacitor 4 is small. For this reason, the current flowing through the resistor 8 exceeds the current flowing through the capacitor 9 and the resistor 7, and the excess current flows into the capacitor 6, so the voltage of the capacitor 6 rises, the on-resistance of the FET 5 decreases, and the input capacitor 4 The charging current to increases. Similarly, when the charging current to the input capacitor 4 is large, the current flowing through the capacitor 9 also increases, so that the current flowing through the resistor 8 is less than the current flowing through the capacitor 9 and the resistor 7, and the current flows from the capacitor 6 to the capacitor 9. Therefore, the voltage of the capacitor 6 decreases, the on-resistance of the FET 5 increases, and the charging current to the input capacitor 4 decreases. By these actions, negative feedback is applied to the charging current to the input capacitor 4, and the charging current converges to a constant value.

  In the converged state, the current flowing through the resistor 8 and the sum of the current flowing through the resistor 7 and the capacitor 9 are substantially equal. At this time, the voltage of the capacitor 6, that is, the gate-source voltage of the FET 5 is almost changed. Therefore, the on-resistance of the FET 5 is substantially constant, and the charging current to the input capacitor 4 is kept constant. Therefore, the expected inrush current value can be obtained by determining the values of the resistor 7, the resistor 8, and the capacitor 9 so as to satisfy the above conditions. In this embodiment, about 27 μA flows through the resistor 8, about 6 μA flows through the resistor 7 and about 21 μA flows through the capacitor 9, and the voltage of the capacitor 6 hardly changes.

  Further, after the input capacitor 4 is fully charged, the charging current to the input capacitor 4 becomes almost zero, so that the current flowing through the capacitor 9 in proportion is also almost zero. For this reason, the voltage of the capacitor 6 rises again due to the current flowing through the resistor 8, and the gate-source voltage of the FET 5 converges to a voltage determined by the divided voltage of the resistors 7 and 8. By making this voltage within the range A in which the on-resistance of the FET 5 is sufficiently low according to FIG. 2, the circuit loss in the steady state after the inrush current suppression is reduced. In this embodiment, the gate-source voltage of the FET 5 converges to about 7.7 V, and the on-resistance is sufficiently low.

  The change in the voltage between the gate and source of the FET 5 described above is shown in FIG. It is assumed that the load 3 starts operating upon completion of charging of the input capacitor 4. In the graph of FIG. 3, the solid line 201 indicates the gate-source voltage of the FET 5 in this embodiment, and the broken line 301 indicates the gate-source voltage of the FET 5 in the conventional general inrush current prevention circuit. Similarly, FIG. 4 shows a change in the input current supplied from the DC power source 1. In the graph of FIG. 4, a solid line 202 indicates a change in input current in this embodiment, and a broken line 302 indicates a change in input current in a conventional general inrush current prevention circuit.

In this embodiment, the input capacitor 4 and the load 3 are connected in parallel. However, depending on the type and circuit system of the load 3, the load 3 may be charged before the charging of the input capacitor 4 is completed. May be activated and current may flow into the load 3. At this time, when the current flows into the load 3, the current flowing into the input capacitor 4 correspondingly decreases, or the current flows out from the input capacitor 4 to the load 3.
However, as described above, the on-resistance of the FET 5 operates so as to keep the charging current to the input capacitor 4 constant. Therefore, the on-resistance of the FET 5 is reduced by the amount of decrease in the charging current to the input capacitor 4. A large amount of current flows between the drain and source of the FET 5. That is, the amount of current flowing through the load 3 causes the FET 5 to operate so that a large amount of current flows by weakening the current limit, thereby preventing the load 3 from becoming unstable due to insufficient current.

Embodiment 2. FIG.
An inrush current preventing circuit according to a second embodiment of the present invention will be described with reference to FIG. In FIG. 5, reference numeral 102 denotes an inrush current prevention circuit unit. In the first embodiment described above, when electromagnetic noise such as a surge is mixed into the power supply 1 when the on-resistance of the FET 5 is large, a noise voltage is applied between the drain and gate of the FET 5. There is a possibility that noise enters the gate of the FET 5 through the capacitor 9 and destroys the FET 5. In the second embodiment, by providing a resistor 10 of an appropriate size in series with the capacitor 9, noise applied to the FET 5 can be reduced and the gate of the FET 5 can be protected from noise.

  In the description of the first and second embodiments described above, an N-type FET is used as shown in FIGS. 1 and 5, but a P-type FET 15 is used as shown in FIG. Is the same. In FIG. 6, reference numeral 103 denotes an inrush current prevention circuit unit.

The circuit diagram which shows the structure of the inrush current prevention circuit by 1st Embodiment of this invention. The graph which showed the relationship between the gate-source voltage and the drain-source on-resistance of a MOS field effect transistor. The graph which showed the difference between this invention and the conventional thing about the gate-source voltage of FET5. The graph which showed the difference of this invention and a conventional thing about the change of the input current supplied from the DC power supply 1. FIG. The circuit diagram which shows the structure of the inrush current prevention circuit by 2nd Embodiment of this invention. The circuit diagram which shows the structure of the inrush current prevention circuit using P-type FET in 2nd embodiment of this invention.

Explanation of symbols

1 DC power supply 2 Switch 3 Load 4 Input capacitor 5, 15 MOS field effect transistor (FET)
6,9 Capacitor 7,8,10 Resistor 101,102,103 Inrush current prevention circuit

Claims (2)

  A load connected to the DC power supply and an input capacitor connected in parallel with the load; a field effect transistor for limiting an inrush current to the input capacitor; and a bias resistor for generating a gate voltage of the field effect transistor; An inrush current prevention circuit comprising: a time constant circuit having a first capacitor; and a second capacitor connected in parallel between the drain and gate of the field effect transistor.   The inrush current prevention circuit according to claim 1, wherein a resistor is connected in series with the second capacitor.

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