JP2001298337A - Variable gain amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier circuit capable of accurately performing signal amplification by excluding the influence on the ON resistance of an analog switch. SOLUTION: The variable gain amplifier circuit is provided with a resistor group for gain switching formed by serially connecting resistors R1-Rn+1, analog switches S1-Sn, an operational amplifier 11 and a decoder 12 or the like and is constituted of elements of an MOS process. Besides, the center points of the respective resistors R1-Rn+1 are respectively connected through the analog switches S1-Sn to the inverting input terminal((-) terminal) of the operational amplifier 11. Since any one analog switch selectively turned on by the decoder 12 is positioned on a connecting line between the node of input resistor and feedback resistor and the inverting input terminal ((-) terminal) of the operational amplifier 11, no current flows through this switch and the influence of the ON resistance of this switch can be ignored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier circuit for amplifying an input signal (sensor signal output signal) having a variation in amplitude and adjusting the signal to a predetermined signal amplitude. In particular, in a semiconductor type sensor having a sensor element and a signal processing circuit for converting a constant physical quantity into an electric signal, a signal processing circuit for handling a small signal having a sensitivity variation in an electric signal obtained for a constant physical quantity. An amplifier circuit can be suitably applied.

[0002]

2. Description of the Related Art As a prior art, a variable gain type amplifier mainly manufactured in a MOS process, which switches a resistance value using a resistor and a switch (an analog switch using a MOS transistor) to change a gain. There is a circuit. For example, in the amplifier circuit disclosed in Japanese Patent Application Laid-Open No. 9-326654, a plurality of resistors for gain switching are connected in series, and an analog switch is connected in parallel to each resistor, and this analog switch is selectively turned on. By doing so, the gain of the amplifier circuit is adjusted.

In this method, since the on-resistance of the analog switch cannot be ignored, it is necessary to design the ratio between the value of the gain switching resistor and the on-resistance of the analog switch so that the required adjustment accuracy is not more than the required value. . As a result, a design to increase the size of the analog switch to reduce the on-resistance is indispensable, and there is a disadvantage that the chip size increases.

Another conventional technique is disclosed in Japanese Patent Application Laid-Open No. 9-13 / 1997.
Japanese Patent No. 5132 is known, but also in the amplifier circuit of the same publication, there arises a problem such as an increase in chip size due to the influence of the on-resistance of the analog switch.

Furthermore, in the amplifier circuit disclosed in Japanese Patent Application Laid-Open No. 61-242405, a gain switching resistor and an analog switch are used to cancel the gain error due to the ON resistance of the analog switch and the temperature and voltage characteristics of the ON resistance. Combine multiple units (series circuits) consisting of switches and
The size ratio of each analog switch is changed according to the resistance value of the gain switching resistor. However, in this case, the resistance value fluctuates because the analog switches are turned on or off at the same time, and the gain error cannot be completely canceled. Further, since a plurality of resistors having different values are required, there is a problem that the circuit scale becomes large.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to eliminate the influence of the on-resistance of an analog switch and to perform signal amplification with high accuracy. And a variable gain amplifier circuit.

[0007]

In the variable gain amplifier circuit according to the present invention, when any one of all the analog switches is selectively turned on by the selection means, the gain switching resistance group is changed to the input resistance. And the resistor on the feedback resistor side. Thereby, the resistance value as the input resistance and the resistance value as the feedback resistance are determined, and the input signal is amplified according to the determined resistance value. At this time,
Since the turned on analog switch is provided between the connection point between the input resistance side and the feedback resistance side and the input terminal of the operational amplifier, it is possible to eliminate the influence of the on resistance of this analog switch. it can.

That is, in FIG. 7 showing the basic configuration of the inverting amplifier circuit, considering the current path of the inverting amplifier circuit, the input bias current of the operational amplifier OP manufactured in the MOS process is zero.
Therefore, no current flows through the connection line from the connection point of the input resistance Ra and the feedback resistance Rb to the inverting input terminal (-terminal) of the operational amplifier OP. In the present invention, since an analog switch is arranged on this connection line to switch the resistance value, the influence of the on-resistance of the analog switch can be ignored. As a result, in the present invention, it is possible to eliminate the influence of the on-resistance of the analog switch and perform signal amplification with high accuracy.

In the variable gain amplifier circuit according to the present invention, the gain switching resistor group is provided between an input resistor including a fixed resistor, a feedback resistor also including a fixed resistor, and the input resistor and the feedback resistor. And a plurality of gain adjustment resistors. In this case, the variable range of the gain is substantially determined by the input resistance and the feedback resistance, and the gain is adjusted in multiple stages according to the gain adjustment resistance within the variable range.

In the variable gain amplifier circuit according to the third aspect of the present invention, the weighting of each resistance value of the gain adjustment resistor is changed, so that the gain required precision (linearity ) Can be satisfied. Therefore, it is possible to completely cancel the gain error. In particular, in this case, as described in claim 4, it is preferable that the individual resistance values of the gain adjustment resistors are set such that the resistance value near the input resistance is small and the resistance value near the feedback resistance is large.

In the variable gain amplifying circuit according to the present invention, the gain adjusting resistors are each constituted by a unit resistor including a contact resistor. In this case, each value of the gain adjustment resistor is set by a ratio of the unit resistors, and the ratio of each value does not vary even if a process variation of the resistance value occurs.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The variable gain amplifier circuit according to the present embodiment is applied, for example, to a sensor signal processing circuit that inputs a signal from an element unit of a rotation sensor that detects the rotation speed of a gear.

FIG. 1 shows a circuit configuration diagram of a variable gain amplifier circuit according to the present embodiment. This circuit has R1, R
2,..., Rn-1, Rn, Rn + 1, a gain switching resistor group in which all n + 1 resistors are connected in series;
.., Sn-1 and Sn, all n analog switches;
It comprises an operational amplifier 11, a decoder 12 for selectively turning on the analog switches S1 to Sn, and a reference power supply 13, and amplifies and outputs an input signal obtained from a sensor element. That is, an inverting amplifier is basically configured, and the gain is variably adjusted by switching its input resistance and feedback resistance. This circuit is MOS
It consists of the elements of the process.

A gain switching resistor group composed of resistors R1 to Rn + 1 has one end (first resistor R1) connected to a signal input terminal and the other end (n + 1th resistor Rn + 1) connected to an operational amplifier 11. Output terminal. Of which
The resistor R1 is an input resistor (fixed resistor on the input side) formed of a fixed resistor, the resistor Rn + 1 is a feedback resistor (fixed resistor on the feedback side) formed of a fixed resistor, and the resistors R2 to Rn are gain adjustment resistors. That is, the resistors R1 and Rn + 1 are resistors that determine the variable range of the gain, and the resistors R2 to Rn are resistors that determine the step of switching the gain. Also, each of the resistors R1 to R
The midpoint of n + 1 is connected to the inverting input terminal (-terminal) of the operational amplifier 11 via the analog switches S1 to Sn, respectively.

The m-bit adjustment data is input to the decoder 12, and the decoder 12 determines and outputs the address (0 to 2 ^ m-1) of the switching signal based on the input adjustment data. The analog switches S1 to Sn are selectively turned on at only one position by a switching signal of the decoder 12. At this time, assuming that the number of bits required for adjustment is m, 2 ^ m + 1 resistors are required as a gain switching resistor group. Also, 2 ^ m analog switches are required.

In the amplifier circuit having the above configuration, for example, when the address of the switching signal output from the decoder 12 is "0", the analog switch S1 is turned on, and the input resistance becomes R.
1, the feedback resistance becomes (R2 + R3 +... + Rn + 1). Therefore, the equation for the gain G is as follows: G =-(R2 + R3 +... + Rn + 1) / R1, and the maximum value of the gain can be set. At this time, the analog switch S1 to be turned on is located on a connection line between the connection point on the input resistance side and the feedback resistance side (connection point of R1 and R2) and the inverting input terminal (-terminal) of the operational amplifier 11. Therefore, no current flows through the analog switch S1, and the influence of the ON resistance of the switch S1 can be ignored.

When the address of the decoder 12 is "2 ^ m-
1 (maximum value), the analog switch S
n is turned on, and the input resistance is (R1 + R2 + R3 +... + R
n), the feedback resistance becomes Rn + 1. Therefore, the equation for the gain G is as follows: G = −Rn + 1 / (R1 + R2 + R3 +... + Rn), whereby the minimum value of the gain can be set. At this time, the analog switch Sn to be turned on again has a connection line between a connection point on the input resistance side and a feedback resistance side (a connection point between Rn and Rn + 1) and an inverting input terminal (−terminal) of the operational amplifier 11. , The analog switch Sn
No current flows through the switch Sn, and the effect of the ON resistance of the switch Sn can be ignored.

As can be seen from the equation of the gain G, when the resistance values of the resistors R2 to Rn are constant, the linearity of the gain is impaired. Therefore, it is considered that the linearity is maintained by designing the resistance values of the resistors R2 to Rn by weighting.

Hereinafter, the case where the linearity correction is not performed, that is, the case where the values of the gain adjustment resistors (R2 to Rn) are fixed, and the case where the linearity correction is performed, that is, the gain adjustment resistors (R2 to Rn) 2 to 4 will be described with reference to specific numerical values. Here, FIG. 2 shows an arrangement of gain values when linearity correction is not performed, FIG. 3 shows an arrangement of gain values when linearity correction is performed, and FIG.
(A) and (b) are graphs of the data of FIGS. 2 and 3. In FIG. 2 and FIG.
In the resistance values shown in the stages, the upper stage shows the value of the input resistance, and the lower stage shows the value of the feedback resistor. Here, as an example, the variable range of the gain = about 8 to 5.5 times, the required accuracy (linearity) <1%, the number of switching bits = 4 bits (16 gradations), the gain monotonicity = monotonically decreasing, and the gain. Each condition is set such that the unit resistance value of the adjustment resistor = 0.5 kΩ. The total resistance value of the input resistance and the feedback resistance> 50 kΩ (depending on the capability of the operational amplifier).

First, in the case where the linearity correction is not performed,
This will be described with reference to FIG. 2 and FIG. Here, the resistance value of the input side fixed resistor R1 is 8 kΩ, and the gain adjustment resistors R2
When the resistance value of R16 is 0.2 kΩ and the resistance value of fixed resistor R17 on the feedback side is 60 kΩ, the variable range of the gain can satisfy the specification (about 8 to 5.5 times).
The required accuracy (linearity) specification (less than 1%) cannot be satisfied.

That is, when the values of the gain adjustment resistors R2 to R16 are fixed, as can be seen from the above-described equation of the gain G, the case where an address having a small numerical value is selected and the input resistance and the feedback resistance are switched, Comparing the case where an address having a large numerical value is selected and the input resistance and the feedback resistance are switched, the error between addresses (gain change amount) for one address (1 LSB) is greatly different, and the error between addresses is smaller when the address is smaller. growing. Therefore, the characteristic of the gain with respect to the address becomes a downward convex arc shape (hyperbolic shape),
Error rate (%) near the center of the address (addresses 7 and 8)
Becomes large. According to FIG. 2, up to 2.94%
It can be seen that an error occurs.

On the other hand, in FIGS. 3 and 4 (b) for performing the linearity correction, the required accuracy (linearity) is obtained by giving a weight to the gain adjustment resistor corresponding to each address.
Can be satisfied. In this case, as described above, the smaller the address, the larger the error between addresses and the greater the effect on the gain change. Therefore, basically, the value of the gain adjustment resistor with the smaller address is reduced, and the gain is adjusted as the address becomes larger. Set a large resistance value. In FIG. 3, the values of the resistors R2 to R7 are 0.167 k.
Ω, the values of the resistors R8 to R12 are 0.2 kΩ,
The value of R16 is 0.25 kΩ.

At this time, an error rate of 0% can be achieved as a design value by setting the value of the gain adjustment resistor linearly. However, there is always a variation in the resistance value due to the structure and manufacturing of the resistor. As a result, the required accuracy cannot be satisfied. Specifically, first of all, the resistor has a diffusion resistance of a semiconductor or a resistance of polysilicon or the like, and also has a contact resistance when connected to the wiring layer AL.
The design value of the resistor is determined by its sheet resistance value ρs, width W, and length L. If the above-mentioned contact resistance is not taken into consideration, assuming that ρs is constant, the resistor is designed only with W and L.

That is, as shown in FIGS. 5A and 5B,
When the gain adjustment resistor is designed linearly, there is a contact resistance Rc in the contact portion 23 where the diffusion resistor (or polysilicon resistor) 21 and the AL wiring 22 are in contact, and the Rc is included in the value of the gain adjustment resistor. . Therefore, the gain adjustment resistor must be designed in consideration of the value of the contact resistance Rc. Further, even if the contact resistance is designed, the error occurs due to the process variation of the contact resistance and the process variation of the diffusion resistance (or polysilicon resistance), and the gain adjustment resistor deviates from the designed value.

Therefore, as shown in FIGS. 6A and 6B,
The unit resistance 31 is configured to include the contact resistance, and is designed to be nearly linear. In FIG. 6, each unit resistor 31 includes a contact resistor Rc and is manufactured in the same step and the same size. Then, by connecting the unit resistors 31 in parallel, the gain adjustment resistor is designed in a nearly linear manner. In the figure, reference numerals 21, 22,
Reference numeral 23 denotes a diffusion resistor (or polysilicon resistor), an AL wiring, and a contact portion, as in FIG. In the case of FIG. 6, since the gain adjustment resistor is designed by the ratio of the unit resistors 31, even if a process variation of the resistance value occurs, the occurrence of the error is canceled.

According to the embodiment described above, the following effects can be obtained. When one of the analog switches S1 to Sn is selectively turned on by the decoder 12 to amplify the input signal, the turned on analog switch is connected to the connection point between the input resistance side and the feedback resistance side and the operational amplifier 11
Therefore, the influence of the on-resistance of the analog switch can be eliminated. As a result, the present amplifier circuit can accurately perform signal amplification irrespective of temperature characteristics and voltage characteristics. Also, at this time, the size of each of the analog switches S1 to Sn can be designed to be the minimum size because the ON resistance of the analog switches is not affected. Further, since the size of the analog switches S1 to Sn becomes the minimum size,
The effect of the leakage current of the transistors constituting 1 to Sn at high temperatures is also minimized.

The gain adjustment resistors (R2 to Rn in FIG. 1) and the weights of the individual resistance values are respectively changed. Particularly, the resistance value near the input-side fixed resistor (R1 in FIG. 1) is small.
Since each resistance value is set so that the resistance value near the feedback-side fixed resistance (Rn + 1 in FIG. 1) becomes large, the required accuracy (linearity) can be satisfied in gain adjustment. Also,
Since the gain adjustment resistor is constituted by the unit resistor, even if a process variation of the resistance value occurs, the occurrence of the error is canceled, and a desired resistance ratio can be set. Therefore, it is possible to completely cancel the gain error.

In the above embodiment, the present invention is embodied as an inverting amplifier circuit. However, it is needless to say that the present invention can be embodied as a non-inverting amplifier circuit or a differential amplifier circuit. Further, the present invention can be appropriately applied to uses other than the sensor signal processing circuit for detecting the rotation speed of the gear.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing an outline of a variable gain amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a diagram in which numerical values of gains are arranged when linearity correction is not performed.

FIG. 3 is a diagram in which numerical values of gains are arranged when performing linearity correction.

FIG. 4 is a graph of the data of FIGS. 2 and 3;

FIG. 5 is a diagram illustrating a configuration in a case where a resistance is linearly varied.

FIG. 6 is a diagram illustrating a configuration in the case where a resistor is configured by a unit resistor.

FIG. 7 is an electric circuit diagram showing a general inverting amplifier circuit.

[Explanation of symbols]

11 ... operational amplifier, 12 ... decoder as selection means,
31: unit resistance, R1 to Rn + 1: resistance, S1 to Sn: analog switch.

Claims (6)

[Claims] An operational amplifier, a gain switching resistor group in which a plurality of resistors are connected in series, and a plurality of resistors respectively connected between an intermediate point of each resistor of the gain switching resistor group and an input terminal of the operational amplifier. A variable gain amplifier circuit comprising: an analog switch; and selection means for selectively turning on one of all analog switches. 2. The gain switching resistor group includes an input resistor comprising a fixed resistor, a feedback resistor also comprising a fixed resistor,
2. The variable gain amplifier circuit according to claim 1, comprising a plurality of gain adjusting resistors provided between the input resistor and the feedback resistor. 3. The variable gain amplifying circuit according to claim 2, wherein the gain adjusting resistor is obtained by changing the weighting of each resistance value. 4. The variable gain amplifier circuit according to claim 3, wherein each of said gain adjustment resistors is set such that a resistance value near an input resistance is small and a resistance value near a feedback resistance is large. Variable gain amplifier circuit. 5. The variable gain amplifying circuit according to claim 3, wherein said gain adjusting resistors are each constituted by a unit resistor including a contact resistor. 6. A variable gain amplifier circuit according to claim 1, wherein said circuit is manufactured in a semiconductor process, particularly in a MOS process.