JP2001298333A - Differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential amplifier circuit which stops the current when operation is not required, and is recovered quickly when needed. SOLUTION: Between the source of transistors 2 and 3 of the input part of a differential circuit 17 and one of power sources, the serial circuit of a transistor 1 having a bias potential in the gate and a transistor 14 having a sleep signal in the gate is interposed, an AND circuit 18 of which the one input is connected to the output line of the differential circuit 17 and the other input receives the sleep signal, is provided and a signal output corresponding to the inputted signal is extracted from the output of the AND circuit 18. By switching the sleep signal, a power supply current is cut off and by not fixing an internal circuit voltage to the power source GND but floating in a sleep state, when the sleep state is canceled, operation can be recovered quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a differential amplifier circuit, and more particularly, to a differential amplifier circuit used for a liquid crystal driver for driving a liquid crystal panel.

[0002]

2. Description of the Related Art In the case of an integrated circuit, many such differential amplifier circuits operable with a small-amplitude input signal are provided side by side on a single semiconductor substrate. It is configured as shown.

This differential amplifier circuit, which takes out a signal output corresponding to a signal input to an inverting input terminal (-) and a non-inverting input terminal (+) from an output terminal Vout, has an input portion composed of Pch transistors 2 and 3. Differential circuit 17 and the inverters INV1, IV1 connected to the output of the differential circuit 17.
NV2 is configured as a main part.

[0004] Pch transistors 2 and 3 connected to each other
Is connected to one of the power supplies via the current source Pch transistor 1. The drain of the Pch transistor 2 is connected to the other power supply via an Nch current mirror transistor 4 that mirrors the current of the Pch transistor 2. The drain of the Pch transistor 3 is connected to the other power supply via an Nch current mirror transistor 5 that mirrors the current of the Pch transistor 3.

[0005] Reference numeral 8 denotes an Nch current mirror transistor for mirroring the current of the Nch transistor 4, and reference numeral 9 denotes an Nch current mirror transistor for mirroring the current of the Nch transistor 5. 6 is a P that mirrors the current of the Nch transistor 8
The ch current mirror transistor 7 is a Pch current mirror transistor that mirrors the current of the Pch transistor 6.

The inverter INV1 is configured by connecting a Pch transistor 10 and an Nch transistor 11 in series.
Are connected to the output of the differential circuit 17.

The inverter INV2 is constructed by connecting a Pch transistor 12 and an Nch transistor 13 in series.
Is connected to the output of the inverter INV1.

[0008] The operation of the differential amplifier thus configured will be described below. First, an optimal bias potential VB is applied to the Pch transistor 1, and a steady current flows through the Pch transistor 1.

Next, assuming that the difference between the differential input voltages VIN + and VIN− is VIN, when VIN is positive, the current flowing through the Pch transistor 2 and the current flowing through the Pch transistor 3 are compared. A lot of current flows.

The current flowing through the Pch transistor 2 is mirrored by the Nch transistor 4 and flows through the Nch transistor 8. Similarly, the current flowing through the Pch transistor 3 is Nch
The current is mirrored by the transistor 5 and flows to the Nch transistor 9. The current flowing through the Nch transistor 8 is mirrored by the Pch transistor 6 and flows through the Pch transistor 7.

Since the current flowing through the Pch transistor 7 is larger than the current flowing through the Nch transistor 9, the voltage V1 rises and the voltage at the output terminal Vout matches the power supply voltage.
Conversely, when VIN is negative, the current flowing through the Pch transistor 7 is smaller than the current flowing through the Nch transistor 9, so that the voltage V1 drops and the output terminal Vout becomes GND.

[0012]

In this conventional configuration,
During the operation period, the current source Pch transistor 1 and the inverters INV1, 6, 7, INV2
Useless current flows through As a specific example, the differential circuit 17
There is a through current of the inverter generated due to the output potential V1 of the intermediate potential, and in particular, as in the case of the differential amplifier circuit used for the liquid crystal driver, a large number of differential amplifier circuits are provided on one semiconductor substrate. When they are provided side by side, the power consumption increases, which hinders a reduction in power consumption.

In order to reduce the power consumption by eliminating this waste, if the application of the power supply voltage is simply turned off during an unnecessary period, the rise when the power supply voltage is turned on again is increased. There is a problem that is slow.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a differential amplifier circuit which can reduce unnecessary current flow when operation is unnecessary, can easily reduce power consumption, and has a fast sleep recovery time when operation is required. I do.

[0015]

According to a first aspect of the present invention, there is provided a differential amplifier circuit comprising a first Pc having an inverting input terminal at a gate.
The input of the differential circuit is formed by connecting the source of the h transistor and the source of the second Pch transistor having a non-inverting input terminal at the gate, and one of the power supply and the first and second Pc
A series circuit of a third Pch transistor having a gate having a bias potential and a fourth Pch transistor having a gate having a sleep signal is interposed between the connection point of the transistor and the source of the h transistor, and the output of the differential circuit is provided. A line is connected to one input and an AND circuit in which the sleep signal is input to the other input is provided, and a signal output corresponding to a signal input to the inverting input terminal and the non-inverting input terminal is output from the AND circuit. It is characterized by taking out.

According to a second aspect of the present invention, there is provided a differential amplifier circuit comprising:
2. The output of the first inverter according to claim 1, wherein the AND circuit includes first and second inverters connected in series, a fifth Pch transistor interposed between the first inverter and one of the power supplies. A first Nch transistor is interposed between the connection point between the power supply and the input of the second inverter and the other of the power supply, and the sleep signal is applied to the gate of the fifth Pch transistor and the gate of the first Nch transistor. It is characterized by having done.

[0017]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 shows a differential amplifier circuit according to an embodiment of the present invention, which is different from the conventional circuit shown in FIG.
Transistors 14, 15, and 16 are added to prevent a through current of the inverter even when V1 is at an intermediate potential.
Also, when the differential amplifier circuit does not need to operate, the operating current can be reduced by switching the sleep signal,
In addition, since the potentials V1, V2, V3, and V4 are not fixed to the power supply or GND, it is possible to quickly return to the operating point during operation.

More specifically, the source of a Pch transistor 2 as a first Pch transistor having an inverting input terminal (-) at the gate and a second Pch transistor having a non-inverting input terminal (+) at the gate.
The input of the differential circuit 17 is formed by connecting the source of the Pch transistor 3 as a Pch transistor, and the bias potential VB is applied between the connection point of one of the power supplies and the sources of the Pch transistors 2 and 3. Pch transistor 1 as a third Pch transistor having a gate and sleep signal SLE
A series circuit of a Pch transistor 14 as a fourth Pch transistor having EP as a gate is provided.

Further, on the output side of the differential circuit 17, there is provided an AND circuit 18 in which the output signal V1 of the differential circuit 17 is connected to one input and the sleep signal SLEEP is input to the other input. A signal output is taken out from an output terminal Vout of an output terminal 18.

Here, the AND circuit 18 includes an inverter I
In the series circuit of NV1 and INV2, transistors 15, 1
6 is added. Specifically, a Pch transistor 15 as a fifth Pch transistor is connected between the inverter INV1 as the first inverter and one power supply.
An Nch transistor 16 as a first Nch transistor is interposed between a connection point between an output of the inverter INV1 and an input of the inverter INV2 as a second inverter and the other of the power supplies, and a Pch transistor 15 is provided. The sleep signal is supplied to the gate of
It is configured by applying SLEEP.

The operation of the thus configured differential amplifier will be described below. FIG. 2 shows a timing chart. First, the optimal bias potential VB is applied to the Pch transistor 1, and the Pch transistor 1
Steady current is flowing. The Pch transistor 14 is turned on by the sleep signal SLEEP, and the Pch transistor 15 is
The N and Nch transistors 16 are off.

Next, if the difference between the differential input voltages VIN + and VIN− is VIN, and if VIN is positive, comparing the currents flowing through the Pch transistors 2 and 3, the Pch transistor 2 has a higher current. It flows a lot.

The current flowing through the Pch transistor 2 is mirrored by the Nch transistor 4 and flows through the Nch transistor 8. Similarly, the current flowing through the Pch transistor 3 is Nch
The current is mirrored by the transistor 5 and flows to the Nch transistor 9. The current flowing through the Nch transistor 8 is mirrored by the Pch transistor 6 and flows through the Pch transistor 7. Pch
Since the current flowing through the transistor 7 is larger than the current flowing through the Nch transistor 9, the voltage V1 rises and the output terminal Vo
ut matches the power supply voltage.

Conversely, when VIN is negative, the current flowing through the Pch transistor 7 is smaller than the current flowing through the Nch transistor 9, so that the voltage V1 falls and the output terminal Vout is connected to GND.
Becomes Also, the Pch transistor 14 has the sleep signal SLE
EP turns off, Pch transistor 15 turns off, and Nch transistor 16 turns on.

In this case, since the current of the current source transistor 1 is cut off, the potentials of the nodes V2 and V3 decrease and stop decreasing at a point where the gate potential is balanced. At this time, no current flows through the Nch transistors 4 and 5.

Similarly, the Nch transistors 8 and 9 which mirror the Nch transistors 4 and 5 do not flow current. Here, when the sleep signal SLEEP becomes L level,
Nodes V1, V2, V3, and V4 are completely at the power supply voltage, or
Since it is not GND, it can be immediately restored to the potential at the time of operation.

[0027]

As described above, according to the present invention, the source of the first P-channel transistor having an inverting input terminal at the gate and the source of the second P-channel transistor having a non-inverting input terminal at the gate are connected. A third P-channel transistor having a gate with a bias potential between a power supply and a connection point between one of the power supplies and the sources of the first and second P-channel transistors. A series circuit of a fourth P-channel transistor having a signal at its gate, an AND circuit having an output line of the differential circuit connected to one input and the sleep signal input to the other input, Since a signal output corresponding to the signals input to the inverting input terminal and the non-inverting input terminal is extracted from the output of the AND circuit, low power consumption can be easily achieved, and further, three Even when the power saving state is set, the nodes are not fixed to the power supply or GND. It can be restored.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a differential amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of the embodiment.

FIG. 3 is a configuration diagram of a conventional differential amplifier circuit.

[Explanation of symbols]

Reference Signs List 1 Pch current source transistor (third P-channel transistor) 2 Pch differential input transistor (first P-channel transistor) 3 Pch differential input transistor (second P-channel transistor) 4 Nch current mirror transistor 5 Nch current mirror Transistor 6 Pch current mirror transistor 7 Pch current mirror transistor 8 Nch current mirror transistor 9 Nch current mirror transistor 10 Pch transistor 11 Nch transistor 12 Pch transistor 13 Nch transistor 14 Sleep control transistor (fourth P channel transistor) 15 Sleep control Transistor (fifth P-channel transistor) 16 Sleep control transistor (first N-channel transistor) 17 Differential circuit 18 AND circuit (-) Inverting input terminal (+) Non-inverting input terminal Vin + Non-inverting input signal Vin- Inverting input signal SLEEP Sleep signal VB Bias potential INV1, INV2 First and second inverter Vout output terminal

 ──────────────────────────────────────────────────続 き Continued from the front page F term (reference) 5J066 AA01 AA12 AA54 CA36 CA65 CA78 FA18 HA10 HA17 HA39 KA04 KA09 KA33 MA21 ND01 ND12 ND22 ND23 PD02 SA08 TA06 5J069 AA01 AA12 AA54 AC02 CA36 CA65 CA78 FA18 KA04 HA17 KA09 SA08 TA06 5J092 AA01 AA12 AA54 CA36 CA65 CA78 FA18 HA10 HA17 HA39 KA04 KA09 KA33 MA21 SA08 TA06

Claims (2)

[Claims] An input section of a differential circuit is formed by connecting a source of a first P-channel transistor having an inverting input terminal to a gate and a source of a second P-channel transistor having a non-inverting input terminal to a gate. A third P-channel transistor having a bias potential at its gate and a fourth P-channel transistor having a sleep signal at its gate are provided between one of the power supplies and a connection point between the source of the first and second P-channel transistors. An AND circuit having a series circuit of channel transistors interposed, an output line of the differential circuit being connected to one input and the sleep signal being input to the other input, and an inverting input terminal from the output of the AND circuit; And a differential amplifier circuit for extracting a signal output corresponding to the signal input to the non-inverting input terminal. 2. The AND circuit according to claim 1, wherein a first and a second inverter are connected in series, a fifth P-channel transistor is interposed between the first inverter and one of the power supplies, A first N-channel transistor is interposed between the output, the input of the second inverter, the connection point, and the other of the power supplies, and the sleep is provided between the gate of the fifth P-channel transistor and the gate of the first N-channel transistor. 2. The differential amplifier circuit according to claim 1, wherein a signal is applied.